sys/arch/i386/isa/ahc_isa.c

460

ahc_outb(ahc, BCTL, ENABLE);

sys/arch/luna88k/dev/lcd.c

275

p1->portC = POWER | READ_BUSY | ENABLE;

sys/arch/luna88k/dev/lcd.c

279

msb = p1->portA & ENABLE;

sys/arch/luna88k/dev/lcd.c

299

p1->portC = POWER | WRITE_DATA | ENABLE;

sys/arch/luna88k/dev/lcd.c

316

p1->portC = POWER | WRITE_CMD | ENABLE;

sys/dev/eisa/ahc_eisa.c

315

ahc_outb(ahc, BCTL, ENABLE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

156

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

92

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

406

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

392

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

377

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

266

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

289

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

417

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2416

tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

248

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

252

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

220

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

224

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

220

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

224

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

246

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

250

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

700

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

702

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

719

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

723

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1127

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1212

doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

516

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

744

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

850

doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

772

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

776

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

992

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

617

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

621

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

892

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

555

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

559

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

885

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

551

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

555

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

905

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

448

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

470

if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

477

} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

150

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

153

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

191

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

195

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

227

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

231

ENABLE, 0);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

291

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

373

ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

375

WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

255

doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1314

unsigned char ENABLE : 1;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1351

unsigned char ENABLE : 1;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1362

unsigned char ENABLE : 1;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

113

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

114

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

115

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

116

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

111

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

112

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

113

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

114

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

80

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

81

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

82

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

83

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

102

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

103

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

104

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

105

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

108

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

109

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

110

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

111

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

779

ENABLE, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

809

ENABLE, enable);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

404

type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

136

if (psr_configuration.bits.ENABLE) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1063

alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

523

alpm_config.bits.ENABLE = (enable ? true : false);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

742

psr_configuration.bits.ENABLE = 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

789

vtotal_control.bits.ENABLE = true;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

543

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

548

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

594

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

599

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

659

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

664

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

665

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

670

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2990

smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);

usr.sbin/config/gram.y

103

%token WITH NEEDS_COUNT NEEDS_FLAG RMOPTIONS ENABLE

usr.sbin/config/gram.y

345

device_instance AT attachment ENABLE { enabledev($1, $3); } |

usr.sbin/smtpd/parse.y

174

%token EHLO ENABLE ENCRYPTION ERROR EXPAND_ONLY

usr.sbin/tokenadm/tokenadm.c

149

what = ENABLE;

usr.sbin/tokenadm/tokenadm.c

241

case ENABLE:

usr.sbin/vmd/parse.y

121

%token ADD AGENTX ALLOW BOOT CDROM CONTEXT DEVICE DISABLE DISK DOWN ENABLE

usr.sbin/vmd/parse.y

759

disable : ENABLE { $$ = 0; }

usr.sbin/vmd/parse.y

834

{ "enable", ENABLE },