DISPLAY_INFO
return DISPLAY_INFO(display)->color.gamma_lut_tests;
return DISPLAY_INFO(display)->color.degamma_lut_tests;
return DISPLAY_INFO(display)->color.gamma_lut_size;
return DISPLAY_INFO(display)->color.degamma_lut_size;
DISPLAY_INFO(display)->color.degamma_lut_size,
u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
degamma_lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
DISPLAY_INFO(display)->color.degamma_lut_size);
for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
intel_display_device_info_print(DISPLAY_INFO(display),
DISPLAY_INFO(display) = info;
&DISPLAY_INFO(display)->__runtime_defaults,
DISPLAY_INFO(display) = &no_display;
#define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
#define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi)
#define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst)
#define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb)
#define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg)
#define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch)
#define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug)
#define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc)
#define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
#define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
#define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking)
#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
intel_display_device_info_print(DISPLAY_INFO(display),
u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;
unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;
unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
#define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
memcpy(&snapshot->info, DISPLAY_INFO(display), sizeof(snapshot->info));
if (DISPLAY_INFO(display)->has_hti)
if (DISPLAY_INFO(display)->color.degamma_lut_size) {
DISPLAY_INFO(display)->cursor_needs_physical;
DISPLAY_INFO(display)->dbuf.slice_mask,
return DISPLAY_INFO(display)->dbuf.size /
hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);
WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);