vgtif_reg
vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
vgtif_reg(pdp[i].lo),
vgtif_reg(pdp[i].hi),
intel_uncore_write(uncore, vgtif_reg(g2v_notify), msg);
vgtif_reg(avail_rs.fence_num));
plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
intel_uncore_write(&i915->uncore, vgtif_reg(display_ready),
intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));