Symbol: vgpu_vreg_t
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1403
stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1404
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1407
stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1409
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1429
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1432
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1434
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1437
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1439
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1444
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
sys/dev/pci/drm/i915/gvt/display.c
196
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
sys/dev/pci/drm/i915/gvt/display.c
202
vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
sys/dev/pci/drm/i915/gvt/display.c
204
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
205
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
206
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
sys/dev/pci/drm/i915/gvt/display.c
207
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
sys/dev/pci/drm/i915/gvt/display.c
211
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=
sys/dev/pci/drm/i915/gvt/display.c
215
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
220
vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
sys/dev/pci/drm/i915/gvt/display.c
222
vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
sys/dev/pci/drm/i915/gvt/display.c
226
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
sys/dev/pci/drm/i915/gvt/display.c
231
vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
sys/dev/pci/drm/i915/gvt/display.c
234
vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/display.c
236
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
238
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
240
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
243
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
sys/dev/pci/drm/i915/gvt/display.c
244
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
sys/dev/pci/drm/i915/gvt/display.c
246
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
sys/dev/pci/drm/i915/gvt/display.c
247
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
sys/dev/pci/drm/i915/gvt/display.c
249
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
sys/dev/pci/drm/i915/gvt/display.c
251
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
252
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
sys/dev/pci/drm/i915/gvt/display.c
254
vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
255
vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
263
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
264
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
272
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
sys/dev/pci/drm/i915/gvt/display.c
273
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
sys/dev/pci/drm/i915/gvt/display.c
274
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
sys/dev/pci/drm/i915/gvt/display.c
275
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
sys/dev/pci/drm/i915/gvt/display.c
276
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
sys/dev/pci/drm/i915/gvt/display.c
280
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
sys/dev/pci/drm/i915/gvt/display.c
281
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
sys/dev/pci/drm/i915/gvt/display.c
283
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
sys/dev/pci/drm/i915/gvt/display.c
285
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
287
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
290
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
294
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
296
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
298
vgpu_vreg_t(vgpu,
sys/dev/pci/drm/i915/gvt/display.c
302
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
304
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
309
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
310
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
sys/dev/pci/drm/i915/gvt/display.c
311
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
sys/dev/pci/drm/i915/gvt/display.c
313
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
sys/dev/pci/drm/i915/gvt/display.c
315
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
sys/dev/pci/drm/i915/gvt/display.c
317
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
sys/dev/pci/drm/i915/gvt/display.c
320
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
sys/dev/pci/drm/i915/gvt/display.c
324
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
sys/dev/pci/drm/i915/gvt/display.c
326
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
sys/dev/pci/drm/i915/gvt/display.c
328
vgpu_vreg_t(vgpu,
sys/dev/pci/drm/i915/gvt/display.c
333
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
335
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
340
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
341
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
sys/dev/pci/drm/i915/gvt/display.c
342
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
sys/dev/pci/drm/i915/gvt/display.c
344
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
sys/dev/pci/drm/i915/gvt/display.c
346
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
sys/dev/pci/drm/i915/gvt/display.c
348
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
sys/dev/pci/drm/i915/gvt/display.c
351
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
sys/dev/pci/drm/i915/gvt/display.c
355
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
sys/dev/pci/drm/i915/gvt/display.c
357
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
sys/dev/pci/drm/i915/gvt/display.c
359
vgpu_vreg_t(vgpu,
sys/dev/pci/drm/i915/gvt/display.c
364
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
366
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
373
vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
sys/dev/pci/drm/i915/gvt/display.c
381
vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
sys/dev/pci/drm/i915/gvt/display.c
383
vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
sys/dev/pci/drm/i915/gvt/display.c
396
vgpu_vreg_t(vgpu, DPLL_CTRL1) =
sys/dev/pci/drm/i915/gvt/display.c
398
vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
sys/dev/pci/drm/i915/gvt/display.c
400
vgpu_vreg_t(vgpu, LCPLL1_CTL) =
sys/dev/pci/drm/i915/gvt/display.c
402
vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
sys/dev/pci/drm/i915/gvt/display.c
409
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
sys/dev/pci/drm/i915/gvt/display.c
410
vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
sys/dev/pci/drm/i915/gvt/display.c
411
vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
sys/dev/pci/drm/i915/gvt/display.c
412
vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
sys/dev/pci/drm/i915/gvt/display.c
413
vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
sys/dev/pci/drm/i915/gvt/display.c
417
vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
sys/dev/pci/drm/i915/gvt/display.c
419
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
421
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
423
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
424
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
427
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
432
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
sys/dev/pci/drm/i915/gvt/display.c
434
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
sys/dev/pci/drm/i915/gvt/display.c
437
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
438
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/display.c
439
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
443
vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
sys/dev/pci/drm/i915/gvt/display.c
445
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
447
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
449
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
450
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
453
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
458
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
sys/dev/pci/drm/i915/gvt/display.c
460
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
sys/dev/pci/drm/i915/gvt/display.c
463
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
464
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/display.c
465
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
469
vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
sys/dev/pci/drm/i915/gvt/display.c
471
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
473
vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
sys/dev/pci/drm/i915/gvt/display.c
475
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
476
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
sys/dev/pci/drm/i915/gvt/display.c
479
vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
sys/dev/pci/drm/i915/gvt/display.c
484
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
sys/dev/pci/drm/i915/gvt/display.c
486
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
sys/dev/pci/drm/i915/gvt/display.c
489
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
490
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/display.c
491
vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
499
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
sys/dev/pci/drm/i915/gvt/display.c
504
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
507
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
sys/dev/pci/drm/i915/gvt/display.c
509
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
sys/dev/pci/drm/i915/gvt/display.c
514
vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
sys/dev/pci/drm/i915/gvt/display.c
518
vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
519
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
520
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
sys/dev/pci/drm/i915/gvt/display.c
521
vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
sys/dev/pci/drm/i915/gvt/display.c
524
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
sys/dev/pci/drm/i915/gvt/display.c
661
vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;
sys/dev/pci/drm/i915/gvt/display.c
696
vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
sys/dev/pci/drm/i915/gvt/display.c
698
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
700
vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
sys/dev/pci/drm/i915/gvt/display.c
702
vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
704
vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
sys/dev/pci/drm/i915/gvt/display.c
705
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
711
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
714
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
sys/dev/pci/drm/i915/gvt/display.c
717
vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
sys/dev/pci/drm/i915/gvt/display.c
719
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
721
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
727
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
729
vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
sys/dev/pci/drm/i915/gvt/display.c
732
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
sys/dev/pci/drm/i915/gvt/display.c
734
vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
sys/dev/pci/drm/i915/gvt/display.c
737
vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
sys/dev/pci/drm/i915/gvt/display.c
739
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
741
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
747
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
sys/dev/pci/drm/i915/gvt/display.c
749
vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
sys/dev/pci/drm/i915/gvt/display.c
752
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
sys/dev/pci/drm/i915/gvt/display.c
754
vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
sys/dev/pci/drm/i915/gvt/display.c
757
vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
sys/dev/pci/drm/i915/gvt/display.c
759
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
sys/dev/pci/drm/i915/gvt/display.c
76
if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
sys/dev/pci/drm/i915/gvt/display.c
761
vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
sys/dev/pci/drm/i915/gvt/display.c
93
if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
sys/dev/pci/drm/i915/gvt/edid.c
134
vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
sys/dev/pci/drm/i915/gvt/edid.c
136
vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
sys/dev/pci/drm/i915/gvt/edid.c
168
vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
sys/dev/pci/drm/i915/gvt/edid.c
169
vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
sys/dev/pci/drm/i915/gvt/edid.c
175
vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
sys/dev/pci/drm/i915/gvt/edid.c
177
vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
sys/dev/pci/drm/i915/gvt/edid.c
204
vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
sys/dev/pci/drm/i915/gvt/edid.c
205
vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
sys/dev/pci/drm/i915/gvt/edid.c
253
vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
sys/dev/pci/drm/i915/gvt/edid.c
265
vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
sys/dev/pci/drm/i915/gvt/edid.c
303
if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
sys/dev/pci/drm/i915/gvt/fb_decoder.c
161
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
224
val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
258
plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
274
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
sys/dev/pci/drm/i915/gvt/fb_decoder.c
277
plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
sys/dev/pci/drm/i915/gvt/fb_decoder.c
281
val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
356
val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
382
plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
sys/dev/pci/drm/i915/gvt/fb_decoder.c
393
val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
399
plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
sys/dev/pci/drm/i915/gvt/fb_decoder.c
400
plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
sys/dev/pci/drm/i915/gvt/gtt.c
993
u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
sys/dev/pci/drm/i915/gvt/handlers.c
1033
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1035
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
sys/dev/pci/drm/i915/gvt/handlers.c
1037
if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)
sys/dev/pci/drm/i915/gvt/handlers.c
1055
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1057
if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
sys/dev/pci/drm/i915/gvt/handlers.c
1077
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1078
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
sys/dev/pci/drm/i915/gvt/handlers.c
1080
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1418
if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRRD) {
sys/dev/pci/drm/i915/gvt/handlers.c
1421
sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));
sys/dev/pci/drm/i915/gvt/handlers.c
1445
if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRWR) {
sys/dev/pci/drm/i915/gvt/handlers.c
1448
sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));
sys/dev/pci/drm/i915/gvt/handlers.c
1450
write_virtual_sbi_register(vgpu, sbi_offset, vgpu_vreg_t(vgpu, SBI_DATA));
sys/dev/pci/drm/i915/gvt/handlers.c
1704
u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
sys/dev/pci/drm/i915/gvt/handlers.c
1900
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
sys/dev/pci/drm/i915/gvt/handlers.c
1902
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
sys/dev/pci/drm/i915/gvt/handlers.c
1907
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
sys/dev/pci/drm/i915/gvt/handlers.c
1909
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
sys/dev/pci/drm/i915/gvt/handlers.c
360
vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
sys/dev/pci/drm/i915/gvt/handlers.c
392
vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
sys/dev/pci/drm/i915/gvt/handlers.c
393
vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
sys/dev/pci/drm/i915/gvt/handlers.c
394
vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
sys/dev/pci/drm/i915/gvt/handlers.c
395
vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
sys/dev/pci/drm/i915/gvt/handlers.c
398
vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
sys/dev/pci/drm/i915/gvt/handlers.c
477
u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
sys/dev/pci/drm/i915/gvt/handlers.c
491
switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
sys/dev/pci/drm/i915/gvt/handlers.c
503
vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
sys/dev/pci/drm/i915/gvt/handlers.c
515
wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
sys/dev/pci/drm/i915/gvt/handlers.c
517
wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
sys/dev/pci/drm/i915/gvt/handlers.c
541
vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
sys/dev/pci/drm/i915/gvt/handlers.c
577
temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
sys/dev/pci/drm/i915/gvt/handlers.c
586
vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
sys/dev/pci/drm/i915/gvt/handlers.c
587
if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
sys/dev/pci/drm/i915/gvt/handlers.c
589
vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
sys/dev/pci/drm/i915/gvt/handlers.c
591
vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
sys/dev/pci/drm/i915/gvt/handlers.c
593
vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
sys/dev/pci/drm/i915/gvt/handlers.c
595
vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
sys/dev/pci/drm/i915/gvt/handlers.c
619
if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&
sys/dev/pci/drm/i915/gvt/handlers.c
620
(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {
sys/dev/pci/drm/i915/gvt/handlers.c
621
dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &
sys/dev/pci/drm/i915/gvt/handlers.c
631
switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &
sys/dev/pci/drm/i915/gvt/handlers.c
669
port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &
sys/dev/pci/drm/i915/gvt/handlers.c
685
link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));
sys/dev/pci/drm/i915/gvt/handlers.c
686
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));
sys/dev/pci/drm/i915/gvt/handlers.c
689
htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
sys/dev/pci/drm/i915/gvt/handlers.c
690
vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
sys/dev/pci/drm/i915/gvt/handlers.c
818
vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
sys/dev/pci/drm/i915/gvt/handlers.c
836
u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
sys/dev/pci/drm/i915/gvt/handlers.c
838
u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
sys/dev/pci/drm/i915/gvt/handlers.c
879
if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
sys/dev/pci/drm/i915/gvt/handlers.c
882
if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
sys/dev/pci/drm/i915/gvt/handlers.c
884
&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
sys/dev/pci/drm/i915/gvt/handlers.c
942
vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
sys/dev/pci/drm/i915/gvt/handlers.c
948
vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
sys/dev/pci/drm/i915/gvt/handlers.c
952
vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
sys/dev/pci/drm/i915/gvt/handlers.c
973
vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
sys/dev/pci/drm/i915/gvt/mmio.c
256
vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
sys/dev/pci/drm/i915/gvt/mmio.c
259
vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
sys/dev/pci/drm/i915/gvt/mmio.c
262
vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
sys/dev/pci/drm/i915/gvt/mmio.c
265
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
sys/dev/pci/drm/i915/gvt/mmio.c
267
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
269
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
271
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
273
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
275
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
277
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
sys/dev/pci/drm/i915/gvt/mmio.c
280
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
282
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
sys/dev/pci/drm/i915/gvt/mmio.c
285
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
sys/dev/pci/drm/i915/gvt/mmio.c
287
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
sys/dev/pci/drm/i915/gvt/mmio.c
290
vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
sys/dev/pci/drm/i915/gvt/mmio_context.c
239
*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);
sys/dev/pci/drm/i915/gvt/mmio_context.c
269
*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
sys/dev/pci/drm/i915/gvt/mmio_context.c
296
*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
sys/dev/pci/drm/i915/gvt/mmio_context.c
402
vgpu_vreg_t(vgpu, reg) = 0;
sys/dev/pci/drm/i915/gvt/mmio_context.c
436
old_v = vgpu_vreg_t(pre, offset);
sys/dev/pci/drm/i915/gvt/mmio_context.c
440
new_v = vgpu_vreg_t(next, offset);
sys/dev/pci/drm/i915/gvt/mmio_context.c
454
old_v = vgpu_vreg_t(pre, l3_offset);
sys/dev/pci/drm/i915/gvt/mmio_context.c
458
new_v = vgpu_vreg_t(next, l3_offset);
sys/dev/pci/drm/i915/gvt/mmio_context.c
509
vgpu_vreg_t(pre, mmio->reg) =
sys/dev/pci/drm/i915/gvt/mmio_context.c
512
vgpu_vreg_t(pre, mmio->reg) &=
sys/dev/pci/drm/i915/gvt/mmio_context.c
514
old_v = vgpu_vreg_t(pre, mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
533
new_v = vgpu_vreg_t(next, mmio->reg) |
sys/dev/pci/drm/i915/gvt/mmio_context.c
536
new_v = vgpu_vreg_t(next, mmio->reg);
sys/dev/pci/drm/i915/gvt/scheduler.c
653
vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
972
vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
sys/dev/pci/drm/i915/gvt/scheduler.c
973
vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
sys/dev/pci/drm/i915/gvt/vgpu.c
44
vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
sys/dev/pci/drm/i915/gvt/vgpu.c
45
vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
sys/dev/pci/drm/i915/gvt/vgpu.c
46
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
sys/dev/pci/drm/i915/gvt/vgpu.c
47
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
sys/dev/pci/drm/i915/gvt/vgpu.c
49
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
sys/dev/pci/drm/i915/gvt/vgpu.c
50
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
sys/dev/pci/drm/i915/gvt/vgpu.c
51
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
sys/dev/pci/drm/i915/gvt/vgpu.c
53
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
sys/dev/pci/drm/i915/gvt/vgpu.c
55
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
sys/dev/pci/drm/i915/gvt/vgpu.c
57
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
sys/dev/pci/drm/i915/gvt/vgpu.c
59
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
sys/dev/pci/drm/i915/gvt/vgpu.c
62
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
sys/dev/pci/drm/i915/gvt/vgpu.c
64
vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
sys/dev/pci/drm/i915/gvt/vgpu.c
65
vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;