lib/libagentx/ax.c

108

uint8_t *u8;

lib/libagentx/ax.c

127

u8 = ax->ax_rbuf;

lib/libagentx/ax.c

128

header.aph_version = *u8++;

lib/libagentx/ax.c

129

header.aph_type = *u8++;

lib/libagentx/ax.c

130

header.aph_flags = *u8++;

lib/libagentx/ax.c

131

u8++;

lib/libagentx/ax.c

132

header.aph_sessionid = ax_pdutoh32(&header, u8);

lib/libagentx/ax.c

133

u8 += 4;

lib/libagentx/ax.c

134

header.aph_transactionid = ax_pdutoh32(&header, u8);

lib/libagentx/ax.c

135

u8 += 4;

lib/libagentx/ax.c

136

header.aph_packetid = ax_pdutoh32(&header, u8);

lib/libagentx/ax.c

137

u8 += 4;

lib/libagentx/ax.c

138

header.aph_plength = ax_pdutoh32(&header, u8);

lib/libagentx/ax.c

194

u8 = (ax->ax_rbuf) + AX_PDU_HEADER;

lib/libagentx/ax.c

197

nread = ax_pdutoostring(&header, &(pdu->ap_context), u8,

lib/libagentx/ax.c

202

u8 += nread;

lib/libagentx/ax.c

212

ax_pdutoh16(&header, u8);

lib/libagentx/ax.c

213

u8 += 2;

lib/libagentx/ax.c

215

ax_pdutoh16(&header, u8);

lib/libagentx/ax.c

216

u8 += 2;

lib/libagentx/ax.c

232

u8, rawlen)) == -1)

lib/libagentx/ax.c

235

u8 += nread;

lib/libagentx/ax.c

237

u8, rawlen)) == -1)

lib/libagentx/ax.c

240

u8 += nread;

lib/libagentx/ax.c

253

&(vbl->ap_varbind[vbl->ap_nvarbind]), u8, rawlen);

lib/libagentx/ax.c

257

u8 += nread;

lib/libagentx/ax.c

293

response->ap_uptime = ax_pdutoh32(&header, u8);

lib/libagentx/ax.c

294

u8 += 4;

lib/libagentx/ax.c

295

response->ap_error = ax_pdutoh16(&header, u8);

lib/libagentx/ax.c

296

u8 += 2;

lib/libagentx/ax.c

297

response->ap_index = ax_pdutoh16(&header, u8);

lib/libagentx/ax.c

298

u8 += 2;

lib/libagentx/ax.c

309

u8, rawlen);

lib/libagentx/ax.c

313

u8 += nread;

lib/libc/crypt/chacha_private.h

20

#define U8V(v) ((u8)(v) & U8C(0xFF))

lib/libc/crypt/chacha_private.h

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

lib/libc/crypt/chacha_private.h

80

chacha_ivsetup(chacha_ctx *x,const u8 *iv)

lib/libc/crypt/chacha_private.h

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

lib/libc/crypt/chacha_private.h

93

u8 *ctarget = NULL;

lib/libc/crypt/chacha_private.h

94

u8 tmp[64];

lib/libcrypto/asn1/a_bitstr.c

128

uint8_t u8 = abs->data[abs->length - 1];

lib/libcrypto/asn1/a_bitstr.c

131

u8 &= 0x100 - u8;

lib/libcrypto/asn1/a_bitstr.c

135

if ((u8 & 0x0f) != 0)

lib/libcrypto/asn1/a_bitstr.c

137

if ((u8 & 0x33) != 0)

lib/libcrypto/asn1/a_bitstr.c

139

if ((u8 & 0x55) != 0)

lib/libcrypto/asn1/a_int.c

138

uint8_t u8;

lib/libcrypto/asn1/a_int.c

143

if (!CBS_get_u8(cbs, &u8))

lib/libcrypto/asn1/a_int.c

149

val = val << 8 | u8;

lib/libcrypto/asn1/a_int.c

163

uint8_t u8;

lib/libcrypto/asn1/a_int.c

177

u8 = (val >> (i * 8)) & 0xff;

lib/libcrypto/asn1/a_int.c

178

if (!started && i != 0 && u8 == 0)

lib/libcrypto/asn1/a_int.c

180

if (!CBB_add_u8(&cbb, u8))

lib/libcrypto/bio/b_dump.c

110

uint8_t u8;

lib/libcrypto/bio/b_dump.c

112

if (!CBS_peek_last_u8(&cbs, &u8))

lib/libcrypto/bio/b_dump.c

114

if (u8 != '\0' && u8 != ' ')

lib/libcrypto/bio/b_dump.c

116

if (!CBS_get_last_u8(&cbs, &u8))

lib/libcrypto/bio/b_dump.c

148

uint8_t u8;

lib/libcrypto/bio/b_dump.c

151

if (!CBS_get_u8(&row, &u8))

lib/libcrypto/bio/b_dump.c

157

if ((written = BIO_printf(bio, "%02x%c", u8, sep)) < 0)

lib/libcrypto/bio/b_dump.c

164

if (u8 < ' ' || u8 > '~')

lib/libcrypto/bio/b_dump.c

165

u8 = '.';

lib/libcrypto/bio/b_dump.c

166

if (!CBB_add_u8(&cbb, u8))

lib/libcrypto/camellia/camellia.c

100

void Camellia_DecryptBlock_Rounds(int grandRounds, const u8 ciphertext[],

lib/libcrypto/camellia/camellia.c

101

const KEY_TABLE_TYPE keyTable, u8 plaintext[]);

lib/libcrypto/camellia/camellia.c

102

void Camellia_EncryptBlock(int keyBitLength, const u8 plaintext[],

lib/libcrypto/camellia/camellia.c

103

const KEY_TABLE_TYPE keyTable, u8 ciphertext[]);

lib/libcrypto/camellia/camellia.c

104

void Camellia_DecryptBlock(int keyBitLength, const u8 ciphertext[],

lib/libcrypto/camellia/camellia.c

105

const KEY_TABLE_TYPE keyTable, u8 plaintext[]);

lib/libcrypto/camellia/camellia.c

130

# define PUTU32(p,v) ((p)[0] = (u8)((v) >> 24), (p)[1] = (u8)((v) >> 16), (p)[2] = (u8)((v) >> 8), (p)[3] = (u8)(v))

lib/libcrypto/camellia/camellia.c

362

Camellia_Ekeygen(int keyBitLength, const u8 *rawKey, KEY_TABLE_TYPE k)

lib/libcrypto/camellia/camellia.c

480

Camellia_EncryptBlock_Rounds(int grandRounds, const u8 plaintext[],

lib/libcrypto/camellia/camellia.c

481

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

lib/libcrypto/camellia/camellia.c

524

Camellia_EncryptBlock(int keyBitLength, const u8 plaintext[],

lib/libcrypto/camellia/camellia.c

525

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

lib/libcrypto/camellia/camellia.c

532

Camellia_DecryptBlock_Rounds(int grandRounds, const u8 ciphertext[],

lib/libcrypto/camellia/camellia.c

533

const KEY_TABLE_TYPE keyTable, u8 plaintext[])

lib/libcrypto/camellia/camellia.c

576

Camellia_DecryptBlock(int keyBitLength, const u8 plaintext[],

lib/libcrypto/camellia/camellia.c

577

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

lib/libcrypto/camellia/camellia.c

96

int Camellia_Ekeygen(int keyBitLength, const u8 *rawKey,

lib/libcrypto/camellia/camellia.c

98

void Camellia_EncryptBlock_Rounds(int grandRounds, const u8 plaintext[],

lib/libcrypto/camellia/camellia.c

99

const KEY_TABLE_TYPE keyTable, u8 ciphertext[]);

lib/libcrypto/chacha/chacha-merged.c

110

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

lib/libcrypto/chacha/chacha-merged.c

119

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

lib/libcrypto/chacha/chacha-merged.c

125

u8 *ctarget = NULL;

lib/libcrypto/chacha/chacha-merged.c

126

u8 tmp[64];

lib/libcrypto/chacha/chacha-merged.c

21

u8 ks[CHACHA_BLOCKLEN];

lib/libcrypto/chacha/chacha-merged.c

22

u8 unused;

lib/libcrypto/chacha/chacha-merged.c

25

static inline void chacha_keysetup(struct chacha_ctx *x, const u8 *k, u32 kbits)

lib/libcrypto/chacha/chacha-merged.c

27

static inline void chacha_ivsetup(struct chacha_ctx *x, const u8 *iv,

lib/libcrypto/chacha/chacha-merged.c

28

const u8 *ctr)

lib/libcrypto/chacha/chacha-merged.c

31

static inline void chacha_encrypt_bytes(struct chacha_ctx *x, const u8 *m,

lib/libcrypto/chacha/chacha-merged.c

32

u8 *c, u32 bytes)

lib/libcrypto/chacha/chacha-merged.c

41

#define U8V(v) ((u8)(v) & U8C(0xFF))

lib/libcrypto/chacha/chacha-merged.c

85

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

lib/libcrypto/ec/ecx_methods.c

301

uint8_t u8;

lib/libcrypto/ec/ecx_methods.c

314

if (!CBS_get_u8(&cbs, &u8))

lib/libcrypto/ec/ecx_methods.c

323

if (BIO_printf(bio, "%02x%s", u8, sep) <= 0)

lib/libcrypto/x509/x509_obj.c

102

if (!CBB_add_u8(cbb, hex[u8 >> 4]))

lib/libcrypto/x509/x509_obj.c

104

if (!CBB_add_u8(cbb, hex[u8 & 0xf]))

lib/libcrypto/x509/x509_obj.c

113

uint8_t u8;

lib/libcrypto/x509/x509_obj.c

123

if (!CBS_get_u8(&cbs, &u8))

lib/libcrypto/x509/x509_obj.c

126

gs_mask[i++ & 0x3] |= u8;

lib/libcrypto/x509/x509_obj.c

136

if (!CBS_get_u8(&cbs, &u8))

lib/libcrypto/x509/x509_obj.c

140

if (!X509_NAME_ENTRY_add_u8_cbb(cbb, u8))

lib/libcrypto/x509/x509_obj.c

91

X509_NAME_ENTRY_add_u8_cbb(CBB *cbb, uint8_t u8)

lib/libcrypto/x509/x509_obj.c

95

if (' ' <= u8 && u8 <= '~')

lib/libcrypto/x509/x509_obj.c

96

return CBB_add_u8(cbb, u8);

lib/libssl/ssl_both.c

260

uint8_t u8;

lib/libssl/ssl_both.c

321

if (!CBS_get_u8(&cbs, &u8) ||

lib/libssl/ssl_both.c

326

s->s3->hs.tls12.message_type = u8;

libexec/ld.so/chacha_private.h

20

#define U8V(v) ((u8)(v) & U8C(0xFF))

libexec/ld.so/chacha_private.h

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

libexec/ld.so/chacha_private.h

80

chacha_ivsetup(chacha_ctx *x,const u8 *iv)

libexec/ld.so/chacha_private.h

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

libexec/ld.so/chacha_private.h

93

u8 *ctarget = NULL;

libexec/ld.so/chacha_private.h

94

u8 tmp[64];

regress/lib/libcrypto/mlkem/parse_test_file.c

720

uint8_t u8;

regress/lib/libcrypto/mlkem/parse_test_file.c

728

if (!CBS_get_last_u8(&p->cbs, &u8))

regress/lib/libcrypto/mlkem/parse_test_file.c

731

assert(u8 == '\n');

regress/lib/libssl/bytestring/bytestringtest.c

102

uint8_t u8;

regress/lib/libssl/bytestring/bytestringtest.c

111

CHECK(CBS_get_u8(&prefixed, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

112

CHECK(u8 == 2);

regress/lib/libssl/bytestring/bytestringtest.c

151

uint8_t u8;

regress/lib/libssl/bytestring/bytestringtest.c

158

CHECK(CBS_peek_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

159

CHECK(u8 == 1);

regress/lib/libssl/bytestring/bytestringtest.c

168

CHECK(CBS_peek_last_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

169

CHECK(u8 == 9);

regress/lib/libssl/bytestring/bytestringtest.c

174

CHECK(CBS_get_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

175

CHECK(u8 == 9);

regress/lib/libssl/bytestring/bytestringtest.c

176

CHECK(!CBS_get_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

70

uint8_t u8;

regress/lib/libssl/bytestring/bytestringtest.c

78

CHECK(CBS_get_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

79

CHECK(u8 == 1);

regress/lib/libssl/bytestring/bytestringtest.c

88

CHECK(CBS_get_last_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

89

CHECK(u8 == 20);

regress/lib/libssl/bytestring/bytestringtest.c

90

CHECK(CBS_get_last_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

91

CHECK(u8 == 19);

regress/lib/libssl/bytestring/bytestringtest.c

92

CHECK(!CBS_get_u8(&data, &u8));

regress/lib/libssl/bytestring/bytestringtest.c

93

CHECK(!CBS_get_last_u8(&data, &u8));

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

32

uint8_t u8;

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

40

ASSERT_INT_EQ(sshbuf_get_u8(p1, &u8), 0);

regress/usr.sbin/snmpd/agentx.c

2404

const uint8_t *u8;

regress/usr.sbin/snmpd/agentx.c

2472

const uint8_t *u8;

regress/usr.sbin/snmpd/agentx.c

2573

const uint8_t *u8;

regress/usr.sbin/snmpd/agentx.c

2666

const uint8_t *u8;

regress/usr.sbin/snmpd/agentx.c

2685

u8 = buf + sizeof(*header);

regress/usr.sbin/snmpd/agentx.c

2686

if (u8[0] != reason)

regress/usr.sbin/snmpd/agentx.c

2688

test, u8[0], reason);

regress/usr.sbin/snmpd/agentx.c

2689

if (u8[1] != 0 || u8[2] != 0 || u8[3] != 0)

sys/crypto/chacha_private.h

119

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

sys/crypto/chacha_private.h

128

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

sys/crypto/chacha_private.h

132

u8 *ctarget = NULL;

sys/crypto/chacha_private.h

133

u8 tmp[64];

sys/crypto/chacha_private.h

21

#define U8V(v) ((u8)(v) & U8C(0xFF))

sys/crypto/chacha_private.h

56

hchacha20(u32 derived_key[8], const u8 nonce[16], const u8 key[32])

sys/crypto/chacha_private.h

94

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

sys/crypto/rijndael.c

577

static const u8 Td4[256] = {

sys/crypto/rijndael.c

618

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

sys/crypto/rijndael.c

626

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/crypto/rijndael.c

713

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/crypto/rijndael.c

756

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

sys/crypto/rijndael.c

757

u8 ct[16])

sys/crypto/rijndael.c

940

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

sys/crypto/rijndael.c

941

u8 pt[16])

sys/dev/ic/qwxvar.h

1804

u8 mcast_keyidx;

sys/dev/ic/qwxvar.h

1805

u8 ucast_keyidx;

sys/dev/ic/qwzvar.h

2101

u8 addr[ETH_ALEN];

sys/dev/ic/qwzvar.h

2122

u8 mcast_keyidx;

sys/dev/ic/qwzvar.h

2123

u8 ucast_keyidx;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1247

u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1726

u8 perf_req, bool advertise);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1728

u8 dev_state, bool drv_state);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1760

u8 dev_state, bool drv_state) { return 0; }

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

428

u8 *bios, u32 length_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

665

u8 *bios, u32 length_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

708

u8 perf_req, bool advertise)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

784

u8 dev_state, bool drv_state)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

91

u8 i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1016

u8 clock_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1023

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

109

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1121

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1192

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1220

int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1225

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1284

u8 voltage_type, u8 voltage_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1288

u8 *start = (u8 *)v3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1301

u8 voltage_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1302

u8 *svd_gpio_id, u8 *svc_gpio_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1305

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1346

u8 voltage_type, u8 voltage_mode)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1349

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1381

u8 voltage_type, u8 voltage_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1385

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1416

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

142

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1452

u8 module_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1456

u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

147

void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1477

((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1480

((u8 *)reg_block + (2 * sizeof(u16)) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1483

num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1493

(u8)(format->ucPreRegDataLength);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1496

((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1501

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1522

((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1548

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1641

void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1646

u8 align_num_bytes = ALIGN(num_bytes, 4);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

174

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

181

u8 id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

211

((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

290

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

317

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

435

u8 *num_dst_objs = (u8 *)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

436

((u8 *)router_src_dst_table + 1 +

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

776

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

803

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

932

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

944

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

950

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

966

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

972

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

993

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

108

u8 pre_reg_data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

112

u8 last;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

113

u8 num_entries;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

134

u8 id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

139

void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

156

u8 clock_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

172

u8 voltage_type, u8 voltage_mode);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

175

u8 voltage_type, u8 voltage_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

179

u8 module_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

181

int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

189

u8 voltage_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

190

u8 *svd_gpio_id, u8 *svc_gpio_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

202

void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

204

u8 clock_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

86

u8 mem_vendor;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

87

u8 mem_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

93

u8 num_entries;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

94

u8 rsv[3];

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

181

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

308

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

309

u8 mem_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

310

u8 mem_vendor;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

453

((u8 *)vram_module + vram_module->v9.vram_module_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

474

((u8 *)vram_module + vram_module->v10.vram_module_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

495

((u8 *)vram_module + vram_module->v11.vram_module_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

516

((u8 *)vram_module + vram_module->v9.vram_module_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

53

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

554

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

556

u8 umc_config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

657

u8 *i2c_address)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

663

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

912

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

255

u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

336

bios = (u8 *)ISA_HOLE_VADDR(0xc0000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bios.c

667

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

492

u8 *s = (u8 *)src;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

337

memcpy((u8 *)binary, (u8 *)fw->data, fw->size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

788

u8 num_instance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

789

u8 major, minor, revision;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

790

u8 harvest;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

491

u8 out = 0x0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

492

u8 buf[8];

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

106

const u8 *p = eeprom_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

182

u8 *eeprom_buf, u32 buf_size, bool read)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

227

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

235

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

93

u8 *eeprom_buf, u32 buf_size, bool read)

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.c

95

u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

30

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_eeprom.h

34

u32 eeprom_addr, u8 *eeprom_buf,

sys/dev/pci/drm/amd/amdgpu/amdgpu_fru_eeprom.c

123

u8 csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

372

u8 slave_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

373

u8 addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

374

u8 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

376

u8 out_buf[2];

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

377

u8 in_buf[2];

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

408

u8 slave_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

409

u8 addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

410

u8 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

435

u8 val = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

466

u8 val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

249

u8 status_bits;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

250

u8 category_code;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

269

u8 level);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

271

u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

336

u8 bl_level; /* saved backlight level */

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

475

u8 h_border;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

476

u8 v_border;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

556

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

557

u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

558

u8 dp_sink_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

566

u8 id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

574

u8 plugged_state;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

581

u8 i2c_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

584

u8 ddc_mux_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

585

u8 ddc_mux_control_pin;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

586

u8 ddc_mux_state;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

589

u8 cd_mux_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

590

u8 cd_mux_control_pin;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

591

u8 cd_mux_state;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1071

u8 data[50];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1162

u8 data[tbl_hdr_fmt_size + 1];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1198

u8 dare[RAS_TABLE_RECORD_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1199

u8 data[rec_hdr_fmt_size + 1];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1255

u8 data[81];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1306

u8 csum, *buf, *pp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

176

u8 i2c_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

264

u8 buf[RAS_TABLE_HEADER_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

322

u8 *buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

358

static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

361

u8 *pp, csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

366

pp = (u8 *) &control->tbl_hdr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

374

static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

377

u8 *pp, csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

381

pp = (u8 *) &control->tbl_rai;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

394

u8 *hh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

396

u8 csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

446

u8 csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

600

u8 *buf, const u32 fri, const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

638

u8 *buf, *pp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

757

u8 *buf, *pp, csum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

921

u8 *buf, const u32 fri, const u32 num)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

969

u8 *buf, *pp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

56

u8 rma_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

57

u8 health_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

609

void *from = ((u8 *)ring->mqd_ptr) + *pos;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

354

adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

358

adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

362

adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

400

adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

402

adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

432

adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

437

adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

465

adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

467

adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

469

adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

471

adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.c

473

adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

323

u8 *save_restore_list_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

324

u8 *save_restore_list_gpm;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

325

u8 *save_restore_list_srm;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

326

u8 *rlc_iram_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

327

u8 *rlc_dram_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

328

u8 *rlcp_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

329

u8 *rlcv_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

330

u8 *global_tap_delays_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

331

u8 *se0_tap_delays_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

332

u8 *se1_tap_delays_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

333

u8 *se2_tap_delays_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

334

u8 *se3_tap_delays_ucode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

625

mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1004

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1009

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1014

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1019

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1024

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1029

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1034

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1039

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1044

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1049

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1054

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1059

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1064

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1069

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1074

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1079

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1085

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

844

u8 *ucode_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

871

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

876

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

881

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

888

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

894

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

948

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

953

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

958

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

963

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

969

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

974

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

980

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

985

ucode_addr = (u8 *)ucode->fw->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

989

ucode_addr = (u8 *)ucode->fw->data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

993

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

998

ucode_addr = (u8 *)ucode->fw->data +

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

610

u8 revision;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

122

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

123

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

71

u8 num_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

72

u8 num_shared;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

77

u8 mode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

79

u8 num_res;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

320

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

473

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

526

u32 freq, u8 clk_type, u8 clk_src)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

528

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

591

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

41

u32 freq, u8 clk_type, u8 clk_src);

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

133

u8 tx_buf[20];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

135

u8 ack, delay = 0;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

203

static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

205

u8 train_set[4])

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

207

u8 v = 0;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

208

u8 p = 0;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

212

u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

213

u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

253

const u8 dpcd[DP_DPCD_SIZE],

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

290

static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

292

u8 ucconfig, u8 lane_num)

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

308

u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

320

u8 buf[3];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

353

u8 msg[DP_DPCD_SIZE];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

379

u8 tmp;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

458

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

470

u8 power_state)

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

495

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

496

u8 train_set[4];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

497

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

498

u8 tries;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

543

u8 tmp;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

59

u8 *send, int send_bytes,

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

60

u8 *recv, int recv_size,

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

602

u8 voltage;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

61

u8 delay, u8 *ack)

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

729

u8 tmp;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.h

28

u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector);

sys/dev/pci/drm/amd/amdgpu/atombios_dp.h

38

u8 power_state);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1201

u8 frev, crev;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

123

static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

125

u8 level;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2042

u8 *record;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2046

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

2050

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

342

static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

42

u8

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

45

u8 backlight_level;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

58

u8 backlight_level)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

71

u8

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

85

u8 level)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h

27

u8

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h

31

u8 backlight_level);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h

32

u8

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.h

36

u8 level);

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

113

u8 flags;

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

162

void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

39

u8 slave_addr, u8 flags,

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

40

u8 *buf, u8 num)

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.h

31

u8 slave_addr, u8 line_number, u8 offset, u8 data);

sys/dev/pci/drm/amd/amdgpu/cik.c

1013

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1135

u8 instance_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1176

u8 instance_id;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1281

u8 *sadb = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1380

u8 stereo_freqs = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1569

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2956

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1250

u8 *sadb = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1357

u8 stereo_freqs = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1524

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2901

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1252

u8 *sadb = NULL;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1351

u8 stereo_freqs = 0;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1534

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2873

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9193

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9354

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9461

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6446

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6620

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4822

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4996

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4751

u8 me_id, pipe_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4778

u8 me_id, pipe_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6554

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6584

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1364

u8 revision;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6201

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6239

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3301

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3337

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c

85

u8 reg;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

88

u8 reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1034

u8 instance_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1074

u8 instance_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1372

u8 instance_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1412

u8 instance_id, queue_id;

sys/dev/pci/drm/amd/amdgpu/si.c

1321

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

269

u16 address, u8 *data,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

368

u16 address, u8 *data,

sys/dev/pci/drm/amd/amdgpu/vi.c

635

u8 *bios, u32 length_bytes)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3337

svms->default_granularity = min_t(u8, amdgpu_svm_default_granularity, 0x1B);

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

191

u8 form_factor;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

192

u8 device_set;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

193

u8 device_locator;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

194

u8 bank_locator;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

195

u8 memory_type;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12608

u8 link_coding_cap;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12773

u8 *data,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12829

u8 *edid_ext, int len,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12870

u8 *edid_ext, int len,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12886

u8 *edid_ext, int len,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12904

u8 *edid_ext = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12947

u8 *edid_ext = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12983

u8 *edid_ext = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1697

u8 revision;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2761

u8 buf[UUID_SIZE];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4985

u8 lower_signal, upper_signal, upper_lum, lower_lum, lum;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5008

u8 signal = caps->luminance_data[mid].input_signal;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6430

u8 bpc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6457

bpc = min_t(u8, bpc, requested_bpc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7491

u8 val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

842

u8 link_index = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

182

u8 luminance;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

183

u8 input_signal;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

230

u8 ac_level;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

234

u8 dc_level;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

238

u8 data_points;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

150

u8 *rad;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

151

u8 *next_rad;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

58

u8 lct;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

59

u8 port_num;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

60

u8 rad[8];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3250

u8 shift = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3292

u8 shift = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

134

u8 *srm, uint32_t srm_size, uint32_t *srm_version)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

197

u8 content_type,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

673

u8 *srm = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

239

u8 next_payload_vc_start = mgr->next_start_slot;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

240

u8 payload_vc_start = new_payload->vc_start_slot;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

241

u8 allocated_time_slots;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

932

dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1805

u8 dp_link_encoding;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1806

u8 link_bw_set = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1807

u8 data[16] = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

255

u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

272

u8 dsc_caps[16] = { 0 };

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

273

u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

274

u8 *dsc_branch_dec_caps = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

725

u8 retry;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

745

u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

889

u8 link_coding_cap;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

637

u8 i = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

123

__field(u8, max_requested_bpc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

124

__field(u8, max_bpc)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

69

static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

71

static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp1_execution.c

32

u8 bksv[sizeof(n)] = { };

sys/dev/pci/drm/amd/include/amd_acpi.h

100

u8 perf_req; /* performance request */

sys/dev/pci/drm/amd/include/amd_acpi.h

105

u8 ret_val; /* return value */

sys/dev/pci/drm/amd/include/amd_acpi.h

111

u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */

sys/dev/pci/drm/amd/include/amd_acpi.h

112

u8 drv_state; /* 0 = operational, 1 = not operational */

sys/dev/pci/drm/amd/include/amd_acpi.h

40

u8 command_code; /* notify command code */

sys/dev/pci/drm/amd/include/amd_acpi.h

46

u8 panel_exp_mode; /* panel expansion mode */

sys/dev/pci/drm/amd/include/amd_acpi.h

47

u8 thermal_gfx; /* thermal state: target gfx controller */

sys/dev/pci/drm/amd/include/amd_acpi.h

48

u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */

sys/dev/pci/drm/amd/include/amd_acpi.h

49

u8 forced_power_gfx; /* forced power state: target gfx controller */

sys/dev/pci/drm/amd/include/amd_acpi.h

50

u8 forced_power_state; /* forced power state: state id */

sys/dev/pci/drm/amd/include/amd_acpi.h

51

u8 system_power_src; /* system power source */

sys/dev/pci/drm/amd/include/amd_acpi.h

52

u8 backlight_level; /* panel backlight level (0-255) */

sys/dev/pci/drm/amd/include/amd_acpi.h

57

u8 requested_display; /* which display is requested */

sys/dev/pci/drm/amd/include/amd_acpi.h

63

u8 luminance; /* luminance in percent */

sys/dev/pci/drm/amd/include/amd_acpi.h

64

u8 input_signal; /* input signal in range 0-255 */

sys/dev/pci/drm/amd/include/amd_acpi.h

70

u8 error_code; /* error code */

sys/dev/pci/drm/amd/include/amd_acpi.h

71

u8 ac_level; /* default brightness on AC power */

sys/dev/pci/drm/amd/include/amd_acpi.h

72

u8 dc_level; /* default brightness on DC power */

sys/dev/pci/drm/amd/include/amd_acpi.h

73

u8 min_input_signal; /* max input signal in range 0-255 */

sys/dev/pci/drm/amd/include/amd_acpi.h

74

u8 max_input_signal; /* min input signal in range 0-255 */

sys/dev/pci/drm/amd/include/amd_acpi.h

75

u8 number_of_points; /* number of data points */

sys/dev/pci/drm/amd/include/amd_acpi.h

99

u8 req_type; /* request type */

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

50

u8 clk_idx;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

51

u8 pstate;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

161

u8 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

172

u8 count;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

177

u8 ppm_design;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

232

u8 t_hyst;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

235

u8 control_mode;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

346

u8 fan_pulses_per_revolution;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

347

u8 fan_min_rpm;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

348

u8 fan_max_rpm;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1009

(u8 *)&pi->vce_interval,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1010

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1018

(u8 *)&pi->vce_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1047

(u8)kv_get_clk_bypass(adev, table->entries[i].clk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1053

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1061

(u8 *)&pi->samu_level_count,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1062

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1072

(u8 *)&pi->samu_interval,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1073

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1081

(u8 *)&pi->samu_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1112

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1120

(u8 *)&pi->acp_level_count,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1121

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1131

(u8 *)&pi->acp_interval,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1132

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1140

(u8 *)&pi->acp_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1415

(u8 *)&value, sizeof(u16), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1448

(u8 *)&pi->fps_high_t,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1457

(u8 *)&pi->fps_low_t,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1523

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1535

static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1537

u8 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1567

(u8 *)&pi->vce_boot_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1568

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1601

(u8 *)&pi->samu_boot_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1602

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1616

static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1624

u8 acp_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1653

(u8 *)&pi->acp_boot_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1654

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1831

u8 clk_bypass_cntl;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1842

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2139

static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2159

return (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2556

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2647

u8 table_rev)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2706

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2707

u8 *power_state_offset;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2732

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2734

u8 *idx;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2744

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2752

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

606

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

622

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

636

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

663

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

691

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

782

(u8 *)&low_sclk_interrupt_t,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

801

pi->graphics_boot_level = (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

815

pi->graphics_boot_level = (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

832

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

845

(u8 *)&pi->graphics_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

856

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

914

(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

916

(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

922

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

928

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

936

(u8 *)&pi->uvd_level_count,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

937

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

947

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

954

(u8 *)&pi->uvd_level,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

984

(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

990

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

998

(u8 *)&pi->vce_level_count,

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

999

sizeof(u8),

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

100

u8 ss_divider_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

101

u8 allow_gnb_slow;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

102

u8 force_nbp_state;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

103

u8 display_wm;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

104

u8 vce_wm;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

111

u8 dpm0_pg_nb_ps_lo;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

112

u8 dpm0_pg_nb_ps_hi;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

113

u8 dpmx_nb_ps_lo;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

114

u8 dpmx_nb_ps_hi;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

125

u8 htc_tmp_lmt;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

126

u8 htc_hyst_lmt;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

151

u8 graphics_dpm_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

152

u8 uvd_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

153

u8 vce_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

154

u8 acp_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

155

u8 samu_level_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

163

u8 uvd_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

164

u8 vce_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

165

u8 acp_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

166

u8 samu_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

167

u8 uvd_interval;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

168

u8 vce_interval;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

169

u8 acp_interval;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

170

u8 samu_interval;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

171

u8 graphics_boot_level;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

172

u8 graphics_interval;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

173

u8 graphics_therm_throttle_enable;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

174

u8 graphics_voltage_change_enable;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

175

u8 graphics_clk_slow_enable;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

176

u8 graphics_clk_slow_divider;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

177

u8 fps_low_t;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

227

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

98

u8 vddc_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.h

99

u8 ds_divider_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_smc.c

123

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

139

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

177

((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

202

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

320

((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

368

((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

411

((u8 *)&array->entries[0] +

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

420

((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

427

((u8 *)&array->entries[0] +

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

438

((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

463

((u8 *)&array->entries[0] +

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

472

((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

497

((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

551

((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

556

u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

656

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2300

(u8 *)(&(smc_table->dpm2Params.TDPLimit)),

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2317

(u8 *)papm_parm,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2341

(u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2407

u8 max_ps_percent;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2475

smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2582

u8 tdep_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2634

(u8 *)dte_tables,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2827

(u8 *)cac_tables,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3015

(u8 *)spll_table,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3410

static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3412

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4340

static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4342

u8 mc_para_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4349

mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4353

static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4355

u8 mc_para_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4363

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4370

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4375

static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4379

u8 result = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4566

u8 i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4631

voltage->index = (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4653

voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4712

u16 value, u8 index,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4735

smc_voltage->phase_settings = (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4817

(u8)si_calculate_memory_refresh_rate(adev, pl->sclk);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4830

arb_regs->mc_arb_burst_time = (u8)burst_time;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4852

(u8 *)&arb_regs,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4971

table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5093

(u8)si_gen_pcie_gen_support(adev,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5193

state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5223

(u8 *)&arb_regs,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5322

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5534

level->gen2PCIE = (u8)si_pi->force_pcie_gen;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5536

level->gen2PCIE = (u8)pl->pcie_gen;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5767

(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5822

return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5842

ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5888

u8 i, j, k;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6006

u8 i, j;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6032

u8 i, j;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6061

u8 module_index = rv770_get_memory_module_index(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6123

mc_reg_table->last = (u8)i;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6208

(u8 *)smc_mc_reg_table,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6227

(u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6311

u8 request;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6591

(u8 *)(&fan_table),

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7206

u8 table_rev)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7323

u8 frev, crev;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7324

u8 *power_state_offset;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7349

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7351

u8 *idx;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7364

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7372

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

1013

u8 svd_gpio_id;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

1014

u8 svc_gpio_id;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

275

u8 last;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

276

u8 num_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

490

u8 vddc_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

491

u8 high_smio;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

563

u8 valid_vddc_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

566

u8 odt_value_0[2];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

567

u8 odt_value_1[2];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

628

u8 last;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

629

u8 num_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

644

u8 mc_wr_weight;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

645

u8 mc_rd_weight;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

646

u8 allow_ovrflw;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

647

u8 num_win_tdp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

648

u8 l2num_win_tdp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

649

u8 lts_truncate_n;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

671

u8 mvdd_high_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

672

u8 mvdd_low_index;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

850

u8 lta_window_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

851

u8 lts_truncate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

872

u8 lts_truncate_default;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

873

u8 shift_n_default;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

874

u8 operating_temp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

878

u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

888

u8 lts_truncate;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

889

u8 shift_n;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

890

u8 dc_pwr_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

901

u8 window_size;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

902

u8 temp_select;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

903

u8 dte_mode;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

904

u8 tdep_count;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

905

u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

936

u8 last;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

937

u8 num_entries;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

142

static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

237

const u8 *src;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

250

src = (const u8 *)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

55

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

395

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

140

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

181

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

249

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

531

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

651

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

781

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

813

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

995

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

100

u8 ucSclkPllRange;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

101

u8 ucSscEnable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

98

u8 ucSclkPostDiv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

99

u8 ucSclkVcoMode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

139

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

51

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

48

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

50

u8 frev, crev;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

501

smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

506

(u8 *)levels, array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

626

u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

627

u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

649

smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

650

smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

36

u8 svi_load_line_en;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

37

u8 svi_load_line_vddc;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

38

u8 tdc_vddc_throttle_release_limit_perc;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

39

u8 tdc_mawt;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

40

u8 tdc_waterfall_ctl;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

41

u8 dte_ambient_temp_base;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1644

__builtin_memcpy((u8 *)(dst) + __dst_offset, \

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1645

(u8 *)(src) + __src_offset, \

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1953

if (memcmp((u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1966

(u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

721

const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

782

u8 num_jpeg_rings_gpu_metrics;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2630

const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2755

u8 num_jpeg_rings;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1942

if (memcmp((u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1955

(u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2778

if (memcmp((u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2791

(u8 *)od_table + offset_of_voltageoffset,

sys/dev/pci/drm/apple/afk.c

214

u8 *payload, size_t payload_size)

sys/dev/pci/drm/apple/afk.c

223

u8 *props = payload + sizeof(name);

sys/dev/pci/drm/apple/afk.c

320

u8 idx = tag & 0xff;

sys/dev/pci/drm/apple/afk.c

395

u8 _unk[48];

sys/dev/pci/drm/apple/afk.c

463

u8 *data, size_t data_size)

sys/dev/pci/drm/apple/afk.c

470

u8 *payload = data + sizeof(*ehdr) + sizeof(*eshdr);

sys/dev/pci/drm/apple/afk.c

695

enum epic_type etype, enum epic_category ecat, u8 stype,

sys/dev/pci/drm/apple/afk.c

838

int afk_send_command(struct apple_epic_service *service, u8 type,

sys/dev/pci/drm/apple/afk.h

111

u8 rxcookie;

sys/dev/pci/drm/apple/afk.h

112

u8 txcookie;

sys/dev/pci/drm/apple/afk.h

116

u8 _pad0[2];

sys/dev/pci/drm/apple/afk.h

122

u8 _pad1[48];

sys/dev/pci/drm/apple/afk.h

184

enum epic_type etype, enum epic_category ecat, u8 stype,

sys/dev/pci/drm/apple/afk.h

186

int afk_send_command(struct apple_epic_service *service, u8 type,

sys/dev/pci/drm/apple/afk.h

43

u8 cmd_tag;

sys/dev/pci/drm/apple/afk.h

83

u8 data[];

sys/dev/pci/drm/apple/afk.h

87

u8 version;

sys/dev/pci/drm/apple/afk.h

89

u8 _pad;

sys/dev/pci/drm/apple/afk.h

96

u8 version;

sys/dev/pci/drm/apple/afk.h

97

u8 category;

sys/dev/pci/drm/apple/dcp-internal.h

72

u8 depth;

sys/dev/pci/drm/apple/dcp.c

113

static void dcp_recv_msg(void *cookie, u8 endpoint, u64 message)

sys/dev/pci/drm/apple/dcp.c

206

void dcp_send_message(struct apple_dcp *dcp, u8 endpoint, u64 message)

sys/dev/pci/drm/apple/dcp.h

66

void dcp_send_message(struct apple_dcp *dcp, u8 endpoint, u64 message);

sys/dev/pci/drm/apple/dptxep.c

100

int dptxport_connect(struct apple_epic_service *service, u8 core, u8 atc,

sys/dev/pci/drm/apple/dptxep.c

101

u8 die)

sys/dev/pci/drm/apple/dptxep.c

21

u8 _pad0[16];

sys/dev/pci/drm/apple/dptxep.c

27

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

29

u8 _unk1[12];

sys/dev/pci/drm/apple/dptxep.c

34

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

36

u8 _unk1[8];

sys/dev/pci/drm/apple/dptxep.c

41

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

43

u8 _unk1[8];

sys/dev/pci/drm/apple/dptxep.c

48

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

50

u8 _unk1[12];

sys/dev/pci/drm/apple/dptxep.c

55

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

57

u8 _unk1[8];

sys/dev/pci/drm/apple/dptxep.c

62

u8 _unk0[12];

sys/dev/pci/drm/apple/dptxep.c

72

int dptxport_validate_connection(struct apple_epic_service *service, u8 core,

sys/dev/pci/drm/apple/dptxep.c

73

u8 atc, u8 die)

sys/dev/pci/drm/apple/dptxep.h

63

int dptxport_validate_connection(struct apple_epic_service *service, u8 core,

sys/dev/pci/drm/apple/dptxep.h

64

u8 atc, u8 die);

sys/dev/pci/drm/apple/dptxep.h

65

int dptxport_connect(struct apple_epic_service *service, u8 core, u8 atc,

sys/dev/pci/drm/apple/dptxep.h

66

u8 die);

sys/dev/pci/drm/apple/iomfb.c

100

u8 depth = oob ? dcp->ch_oobcmd.depth : dcp->ch_cmd.depth;

sys/dev/pci/drm/apple/iomfb.c

131

static u16 dcp_packet_start(struct dcp_channel *ch, u8 depth)

sys/dev/pci/drm/apple/iomfb.c

140

static u8 dcp_push_depth(u8 *depth)

sys/dev/pci/drm/apple/iomfb.c

142

u8 ret = (*depth)++;

sys/dev/pci/drm/apple/iomfb.c

148

static u8 dcp_pop_depth(u8 *depth)

sys/dev/pci/drm/apple/iomfb.c

174

u8 depth = dcp_push_depth(&ch->depth);

sys/dev/pci/drm/apple/iomfb.c

265

u8 depth;

sys/dev/pci/drm/apple/iomfb.h

123

u8 tile_w;

sys/dev/pci/drm/apple/iomfb.h

124

u8 tile_h;

sys/dev/pci/drm/apple/iomfb.h

129

u8 count;

sys/dev/pci/drm/apple/iomfb.h

130

u8 types[7];

sys/dev/pci/drm/apple/iomfb.h

137

u8 unk1_null;

sys/dev/pci/drm/apple/iomfb.h

138

u8 unk2_null;

sys/dev/pci/drm/apple/iomfb.h

139

u8 padding[8];

sys/dev/pci/drm/apple/iomfb.h

158

u8 unk[28];

sys/dev/pci/drm/apple/iomfb.h

163

u8 frame_sync_props_null;

sys/dev/pci/drm/apple/iomfb.h

164

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

221

u8 unk;

sys/dev/pci/drm/apple/iomfb.h

222

u8 buf_null;

sys/dev/pci/drm/apple/iomfb.h

223

u8 vaddr_null;

sys/dev/pci/drm/apple/iomfb.h

224

u8 dva_null;

sys/dev/pci/drm/apple/iomfb.h

237

u8 unk;

sys/dev/pci/drm/apple/iomfb.h

238

u8 buf_null;

sys/dev/pci/drm/apple/iomfb.h

245

u8 paddr_null;

sys/dev/pci/drm/apple/iomfb.h

246

u8 dva_null;

sys/dev/pci/drm/apple/iomfb.h

247

u8 dva_size_null;

sys/dev/pci/drm/apple/iomfb.h

248

u8 padding;

sys/dev/pci/drm/apple/iomfb.h

262

u8 dva_null;

sys/dev/pci/drm/apple/iomfb.h

263

u8 dva_size_null;

sys/dev/pci/drm/apple/iomfb.h

264

u8 padding[2];

sys/dev/pci/drm/apple/iomfb.h

276

u8 swap_id_null;

sys/dev/pci/drm/apple/iomfb.h

277

u8 client_null;

sys/dev/pci/drm/apple/iomfb.h

278

u8 padding[2];

sys/dev/pci/drm/apple/iomfb.h

291

u8 value_null;

sys/dev/pci/drm/apple/iomfb.h

292

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

297

u8 ret;

sys/dev/pci/drm/apple/iomfb.h

298

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

305

u8 value_null;

sys/dev/pci/drm/apple/iomfb.h

306

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

317

u8 unkbool;

sys/dev/pci/drm/apple/iomfb.h

318

u8 unkint_null;

sys/dev/pci/drm/apple/iomfb.h

319

u8 padding[2];

sys/dev/pci/drm/apple/iomfb.h

345

u8 unkBool;

sys/dev/pci/drm/apple/iomfb.h

359

u8 ret;

sys/dev/pci/drm/apple/iomfb.h

369

u8 mode_null;

sys/dev/pci/drm/apple/iomfb.h

370

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

379

u8 unkint_null;

sys/dev/pci/drm/apple/iomfb.h

380

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

390

u8 flag1;

sys/dev/pci/drm/apple/iomfb.h

391

u8 flag2;

sys/dev/pci/drm/apple/iomfb.h

392

u8 pad[2];

sys/dev/pci/drm/apple/iomfb.h

397

u8 client_null;

sys/dev/pci/drm/apple/iomfb.h

398

u8 pad[3];

sys/dev/pci/drm/apple/iomfb.h

411

u8 matrix_null;

sys/dev/pci/drm/apple/iomfb.h

412

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

423

u8 value_null;

sys/dev/pci/drm/apple/iomfb.h

424

u8 padding[3];

sys/dev/pci/drm/apple/iomfb.h

97

u8 flag1;

sys/dev/pci/drm/apple/iomfb.h

98

u8 flag2;

sys/dev/pci/drm/apple/iomfb.h

99

u8 padding[2];

sys/dev/pci/drm/apple/iomfb_template.c

105

static u8 dcpep_cb_true(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

1052

static u8 dcpep_cb_create_backlight_service(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

1058

TRAMPOLINE_OUT(trampoline_true, dcpep_cb_true, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1059

TRAMPOLINE_OUT(trampoline_false, dcpep_cb_false, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1072

struct iomfb_sr_set_property_int_req, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1079

u8);

sys/dev/pci/drm/apple/iomfb_template.c

1085

TRAMPOLINE_INOUT(trampoline_prop_start, dcpep_cb_prop_start, u32, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1087

struct dcp_set_dcpav_prop_chunk_req, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1089

struct dcp_set_dcpav_prop_end_req, u8);

sys/dev/pci/drm/apple/iomfb_template.c

110

static u8 dcpep_cb_false(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

1105

iomfbep_cb_enable_backlight_message_ap_gated, u8);

sys/dev/pci/drm/apple/iomfb_template.c

1110

TRAMPOLINE_OUT(trampoline_create_backlight_service, dcpep_cb_create_backlight_service, u8);

sys/dev/pci/drm/apple/iomfb_template.c

150

u8 *succ = ch->output[ch->depth - 1];

sys/dev/pci/drm/apple/iomfb_template.c

172

u8 *succ = ch->output[ch->depth - 1];

sys/dev/pci/drm/apple/iomfb_template.c

185

u8 *succ = out;

sys/dev/pci/drm/apple/iomfb_template.c

237

static u8 iomfbep_cb_sr_set_property_int(struct apple_dcp *dcp,

sys/dev/pci/drm/apple/iomfb_template.c

369

static u8 dcpep_cb_release_mem_desc(struct apple_dcp *dcp, u32 *mem_desc_id)

sys/dev/pci/drm/apple/iomfb_template.c

492

u8 *enabled)

sys/dev/pci/drm/apple/iomfb_template.c

504

static u8 dcpep_cb_prop_start(struct apple_dcp *dcp, u32 *length)

sys/dev/pci/drm/apple/iomfb_template.c

522

static u8 dcpep_cb_prop_chunk(struct apple_dcp *dcp,

sys/dev/pci/drm/apple/iomfb_template.c

588

static u8 dcpep_cb_prop_end(struct apple_dcp *dcp,

sys/dev/pci/drm/apple/iomfb_template.c

591

u8 resp = dcpep_process_chunks(dcp, req);

sys/dev/pci/drm/apple/iomfb_template.c

604

u8 *succ = ch->output[ch->depth - 1];

sys/dev/pci/drm/apple/iomfb_template.h

102

u8 unkbool;

sys/dev/pci/drm/apple/iomfb_template.h

106

u8 unkbool2;

sys/dev/pci/drm/apple/iomfb_template.h

112

u8 swap_null;

sys/dev/pci/drm/apple/iomfb_template.h

113

u8 surf_null[SWAP_SURFACES];

sys/dev/pci/drm/apple/iomfb_template.h

115

u8 surf2_null[5];

sys/dev/pci/drm/apple/iomfb_template.h

117

u8 unkoutbool_null;

sys/dev/pci/drm/apple/iomfb_template.h

119

u8 unkU32Ptr_null;

sys/dev/pci/drm/apple/iomfb_template.h

120

u8 unkU32out_null;

sys/dev/pci/drm/apple/iomfb_template.h

122

u8 padding[1];

sys/dev/pci/drm/apple/iomfb_template.h

126

u8 unkoutbool;

sys/dev/pci/drm/apple/iomfb_template.h

131

u8 padding[3];

sys/dev/pci/drm/apple/iomfb_template.h

136

u8 unkbool;

sys/dev/pci/drm/apple/iomfb_template.h

139

u8 swap_info[0x6c4];

sys/dev/pci/drm/apple/iomfb_template.h

141

u8 swap_info[0x6c5];

sys/dev/pci/drm/apple/iomfb_template.h

144

u8 swap_info_null;

sys/dev/pci/drm/apple/iomfb_template.h

152

u8 unk_u64_null;

sys/dev/pci/drm/apple/iomfb_template.h

154

u8 addr_null;

sys/dev/pci/drm/apple/iomfb_template.h

155

u8 length_null;

sys/dev/pci/drm/apple/iomfb_template.h

157

u8 padding[1];

sys/dev/pci/drm/apple/iomfb_template.h

159

u8 padding[2];

sys/dev/pci/drm/apple/iomfb_template.h

36

u8 unk_110[0x1b8];

sys/dev/pci/drm/apple/iomfb_template.h

38

u8 unk_2cc[0x14];

sys/dev/pci/drm/apple/iomfb_template.h

43

u8 unk_2e2[3];

sys/dev/pci/drm/apple/iomfb_template.h

47

u8 bl_power; // constant 0x40 for on

sys/dev/pci/drm/apple/iomfb_template.h

48

u8 unk_2f3[0x2d];

sys/dev/pci/drm/apple/iomfb_template.h

50

u8 unk_320[0x13f];

sys/dev/pci/drm/apple/iomfb_template.h

57

u8 is_tiled;

sys/dev/pci/drm/apple/iomfb_template.h

58

u8 is_tearing_allowed;

sys/dev/pci/drm/apple/iomfb_template.h

59

u8 is_premultiplied;

sys/dev/pci/drm/apple/iomfb_template.h

64

u8 xfer_func;

sys/dev/pci/drm/apple/iomfb_template.h

65

u8 colorspace;

sys/dev/pci/drm/apple/iomfb_template.h

68

u8 pel_w;

sys/dev/pci/drm/apple/iomfb_template.h

69

u8 pel_h;

sys/dev/pci/drm/apple/iomfb_template.h

85

u8 padding[7];

sys/dev/pci/drm/apple/iomfb_template.h

87

u8 padding[47];

sys/dev/pci/drm/apple/parser.c

204

static int parse_blob(struct dcp_parse_ctx *handle, size_t size, u8 const **blob)

sys/dev/pci/drm/apple/parser.c

207

const u8 *out;

sys/dev/pci/drm/apple/parser.c

749

u8 type;

sys/dev/pci/drm/apple/parser.c

770

static void append_chmap(struct snd_pcm_chmap_elem *chmap, u8 type)

sys/dev/pci/drm/apple/parser.c

929

const u8 *blob;

sys/dev/pci/drm/apple/parser.h

117

u8 data[24];

sys/dev/pci/drm/apple/parser.h

79

u8 depth;

sys/dev/pci/drm/apple/systemep.c

19

static const u8 setprop_gAFKConfigLogMask_ffff[] = {

sys/dev/pci/drm/apple/trace.h

100

__field(u8, endpoint)

sys/dev/pci/drm/apple/trace.h

116

__field(u8, endpoint) __field(u16, size)

sys/dev/pci/drm/apple/trace.h

134

__field(u8, endpoint) __field(u32, rptr)

sys/dev/pci/drm/apple/trace.h

165

__field(u8, endpoint) __field(u32, rptr)

sys/dev/pci/drm/apple/trace.h

186

u8, endpoint) __field(u32, channel) __field(u32, type)

sys/dev/pci/drm/apple/trace.h

187

__field(u32, data_size) __field(u8, category)

sys/dev/pci/drm/apple/trace.h

383

TP_PROTO(struct dptx_port *dptx, u8 core, u8 atc, u8 die),

sys/dev/pci/drm/apple/trace.h

387

__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),

sys/dev/pci/drm/apple/trace.h

397

TP_PROTO(struct dptx_port *dptx, u8 core, u8 atc, u8 die),

sys/dev/pci/drm/apple/trace.h

401

__field(u32, unit) __field(u8, core) __field(u8, atc) __field(u8, die)),

sys/dev/pci/drm/apple/trace.h

80

TP_PROTO(struct apple_dcp *dcp, u8 endpoint, u64 message),

sys/dev/pci/drm/apple/trace.h

84

__field(u8, endpoint)

sys/dev/pci/drm/apple/trace.h

96

TP_PROTO(struct apple_dcp *dcp, u8 endpoint, u64 message),

sys/dev/pci/drm/clients/drm_log.c

113

const u8 *src;

sys/dev/pci/drm/clients/drm_log.c

74

const u8 *src, unsigned int src_pitch,

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

128

u8 offset, const void *buffer, size_t size)

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

449

u8 data;

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

497

u8 data = 0;

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

64

u8 offset, void *buffer, size_t size)

sys/dev/pci/drm/display/drm_dp_dual_mode_helper.c

66

u8 zero = 0;

sys/dev/pci/drm/display/drm_dp_helper.c

1065

bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1066

const u8 port_cap[4], u8 type)

sys/dev/pci/drm/display/drm_dp_helper.c

1082

bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1083

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

111

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1118

u8 real_edid_checksum)

sys/dev/pci/drm/display/drm_dp_helper.c

1120

u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;

sys/dev/pci/drm/display/drm_dp_helper.c

115

u8 lane_status;

sys/dev/pci/drm/display/drm_dp_helper.c

1169

static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

1171

u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;

sys/dev/pci/drm/display/drm_dp_helper.c

1180

u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

1182

u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/display/drm_dp_helper.c

1232

u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

126

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1266

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1267

u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])

sys/dev/pci/drm/display/drm_dp_helper.c

1270

u8 len;

sys/dev/pci/drm/display/drm_dp_helper.c

1307

int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1308

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

133

u8 l = dp_link_status(link_status, i);

sys/dev/pci/drm/display/drm_dp_helper.c

1336

int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1337

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

139

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1401

int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1402

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

1444

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1445

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

146

u8 l = dp_link_status(link_status, i);

sys/dev/pci/drm/display/drm_dp_helper.c

1500

bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1501

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

153

u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1531

bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1532

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

1562

bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1563

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

1564

u8 color_spc)

sys/dev/pci/drm/display/drm_dp_helper.c

1596

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1597

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

160

u8 l = dp_link_status(link_status, i);

sys/dev/pci/drm/display/drm_dp_helper.c

1600

u8 vic;

sys/dev/pci/drm/display/drm_dp_helper.c

1662

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1663

const u8 port_cap[4],

sys/dev/pci/drm/display/drm_dp_helper.c

167

bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

170

u8 lane_align, lane_status;

sys/dev/pci/drm/display/drm_dp_helper.c

1749

drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1750

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

1806

const u8 *dpcd,

sys/dev/pci/drm/display/drm_dp_helper.c

1807

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

1832

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

1854

u8 count;

sys/dev/pci/drm/display/drm_dp_helper.c

187

bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

190

u8 lane_status;

sys/dev/pci/drm/display/drm_dp_helper.c

203

bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

205

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

sys/dev/pci/drm/display/drm_dp_helper.c

212

bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

214

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

sys/dev/pci/drm/display/drm_dp_helper.c

221

bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

223

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

sys/dev/pci/drm/display/drm_dp_helper.c

2250

static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)

sys/dev/pci/drm/display/drm_dp_helper.c

2252

u8 buf, count;

sys/dev/pci/drm/display/drm_dp_helper.c

2283

u8 crc_bytes[6];

sys/dev/pci/drm/display/drm_dp_helper.c

229

static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)

sys/dev/pci/drm/display/drm_dp_helper.c

241

static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)

sys/dev/pci/drm/display/drm_dp_helper.c

2445

int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2477

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

2504

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

2523

u8 oui[3];

sys/dev/pci/drm/display/drm_dp_helper.c

2524

u8 device_id[6];

sys/dev/pci/drm/display/drm_dp_helper.c

253

static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)

sys/dev/pci/drm/display/drm_dp_helper.c

2570

u8 any_device[] = DEVICE_ID_ANY;

sys/dev/pci/drm/display/drm_dp_helper.c

2679

u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2681

u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];

sys/dev/pci/drm/display/drm_dp_helper.c

2716

u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

2719

u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];

sys/dev/pci/drm/display/drm_dp_helper.c

2731

u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];

sys/dev/pci/drm/display/drm_dp_helper.c

2774

u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2776

u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];

sys/dev/pci/drm/display/drm_dp_helper.c

2820

int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

2821

u8 dsc_bpc[3])

sys/dev/pci/drm/display/drm_dp_helper.c

2824

u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];

sys/dev/pci/drm/display/drm_dp_helper.c

2842

const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,

sys/dev/pci/drm/display/drm_dp_helper.c

2843

u8 *buf, int buf_size)

sys/dev/pci/drm/display/drm_dp_helper.c

287

static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

2876

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

2877

u8 caps[DP_LTTPR_COMMON_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2897

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

2899

u8 caps[DP_LTTPR_PHY_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

290

int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);

sys/dev/pci/drm/display/drm_dp_helper.c

2907

static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)

sys/dev/pci/drm/display/drm_dp_helper.c

292

u8 rd_interval, mask;

sys/dev/pci/drm/display/drm_dp_helper.c

2923

int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2925

u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);

sys/dev/pci/drm/display/drm_dp_helper.c

2946

int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

2948

u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);

sys/dev/pci/drm/display/drm_dp_helper.c

2963

u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :

sys/dev/pci/drm/display/drm_dp_helper.c

3021

int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3023

u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);

sys/dev/pci/drm/display/drm_dp_helper.c

3037

drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3039

u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);

sys/dev/pci/drm/display/drm_dp_helper.c

3053

drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3055

u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);

sys/dev/pci/drm/display/drm_dp_helper.c

3072

u8 rate, lanes;

sys/dev/pci/drm/display/drm_dp_helper.c

3120

struct drm_dp_phy_test_params *data, u8 dp_rev)

sys/dev/pci/drm/display/drm_dp_helper.c

3123

u8 test_pattern;

sys/dev/pci/drm/display/drm_dp_helper.c

3337

bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3339

u8 rx_feature;

sys/dev/pci/drm/display/drm_dp_helper.c

3362

bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3364

u8 rx_feature;

sys/dev/pci/drm/display/drm_dp_helper.c

342

int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

3460

int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

3461

const u8 port_cap[4])

sys/dev/pci/drm/display/drm_dp_helper.c

3464

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

349

int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

3500

u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |

sys/dev/pci/drm/display/drm_dp_helper.c

3519

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3545

u8 frl_mode)

sys/dev/pci/drm/display/drm_dp_helper.c

3548

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

360

u8 val;

sys/dev/pci/drm/display/drm_dp_helper.c

3601

u8 frl_type)

sys/dev/pci/drm/display/drm_dp_helper.c

3604

u8 buf = max_frl_mask;

sys/dev/pci/drm/display/drm_dp_helper.c

3640

u8 buf = 0;

sys/dev/pci/drm/display/drm_dp_helper.c

3663

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3685

int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)

sys/dev/pci/drm/display/drm_dp_helper.c

3687

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3715

u8 buf, error_count;

sys/dev/pci/drm/display/drm_dp_helper.c

3750

bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3752

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3753

u8 major_v, minor_v;

sys/dev/pci/drm/display/drm_dp_helper.c

377

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3772

int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3774

u8 slice_cap1, slice_cap2;

sys/dev/pci/drm/display/drm_dp_helper.c

379

u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &

sys/dev/pci/drm/display/drm_dp_helper.c

3810

int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3812

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3826

int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

3828

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3850

int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)

sys/dev/pci/drm/display/drm_dp_helper.c

3852

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3890

int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])

sys/dev/pci/drm/display/drm_dp_helper.c

3911

int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])

sys/dev/pci/drm/display/drm_dp_helper.c

393

u8 rd_interval)

sys/dev/pci/drm/display/drm_dp_helper.c

3936

int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)

sys/dev/pci/drm/display/drm_dp_helper.c

3939

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

3970

u8 buf[3] = { 0 };

sys/dev/pci/drm/display/drm_dp_helper.c

4009

u8 buf;

sys/dev/pci/drm/display/drm_dp_helper.c

401

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

4058

u8 dpcd_buf;

sys/dev/pci/drm/display/drm_dp_helper.c

4133

u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

4137

u8 pn, pn_min, pn_max;

sys/dev/pci/drm/display/drm_dp_helper.c

4228

u8 *current_mode)

sys/dev/pci/drm/display/drm_dp_helper.c

4231

u8 buf[3];

sys/dev/pci/drm/display/drm_dp_helper.c

4232

u8 mode_reg;

sys/dev/pci/drm/display/drm_dp_helper.c

4311

u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

4312

u32 *current_level, u8 *current_mode, bool need_luminance)

sys/dev/pci/drm/display/drm_dp_helper.c

4425

u8 current_mode;

sys/dev/pci/drm/display/drm_dp_helper.c

4426

u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];

sys/dev/pci/drm/display/drm_dp_helper.c

447

static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)

sys/dev/pci/drm/display/drm_dp_helper.c

453

const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

455

u8 interval = dp_lttpr_phy_cap(phy_cap,

sys/dev/pci/drm/display/drm_dp_helper.c

476

u8 val = 1;

sys/dev/pci/drm/display/drm_dp_helper.c

480

static const u8 timeout_mapping[] = {

sys/dev/pci/drm/display/drm_dp_helper.c

521

u8 drm_dp_link_rate_to_bw_code(int link_rate)

sys/dev/pci/drm/display/drm_dp_helper.c

537

int drm_dp_bw_code_to_link_rate(u8 link_bw)

sys/dev/pci/drm/display/drm_dp_helper.c

557

u8 request, uint offset, void *buffer, int ret)

sys/dev/pci/drm/display/drm_dp_helper.c

581

static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,

sys/dev/pci/drm/display/drm_dp_helper.c

660

u8 buffer;

sys/dev/pci/drm/display/drm_dp_helper.c

76

static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)

sys/dev/pci/drm/display/drm_dp_helper.c

801

u8 status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

81

static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

823

u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/display/drm_dp_helper.c

86

u8 l = dp_link_status(link_status, i);

sys/dev/pci/drm/display/drm_dp_helper.c

860

u8 value;

sys/dev/pci/drm/display/drm_dp_helper.c

898

u8 value;

sys/dev/pci/drm/display/drm_dp_helper.c

91

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/display/drm_dp_helper.c

923

u8 status;

sys/dev/pci/drm/display/drm_dp_helper.c

94

u8 lane_align;

sys/dev/pci/drm/display/drm_dp_helper.c

946

int vcpid, u8 start_time_slot, u8 time_slot_count)

sys/dev/pci/drm/display/drm_dp_helper.c

948

u8 payload_alloc[3], status;

sys/dev/pci/drm/display/drm_dp_helper.c

95

u8 lane_status;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

102

static const char *drm_dp_mst_req_type_str(u8 req_type)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1155

u8 port_num, u32 offset, u8 num_bytes, u8 *bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1198

u8 vcpi, uint16_t pbn,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1199

u8 number_sdp_streams,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1200

u8 *sdp_stream_sink)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1232

build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1233

u8 *q_id)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

133

static const char *drm_dp_mst_nak_reason_str(u8 nak_reason)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1332

static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

175

static inline u8

sys/dev/pci/drm/display/drm_dp_mst_topology.c

176

drm_dp_mst_get_ufp_num_at_lct_from_rad(u8 lct, const u8 *rad)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

180

u8 ufp_num;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

192

drm_dp_mst_rad_to_str(const u8 rad[8], u8 lct, char *out, size_t len)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

195

u8 unpacked_rad[16] = {};

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2015

static struct drm_dp_mst_port *drm_dp_get_port(struct drm_dp_mst_branch *mstb, u8 port_num)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2035

static u8 drm_dp_calculate_rad(struct drm_dp_mst_port *port,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2036

u8 *rad)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2052

static bool drm_dp_mst_is_end_device(u8 pdt, bool mcs)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2069

drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

207

static u8 drm_dp_msg_header_crc4(const uint8_t *data, size_t num_nibbles)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2074

u8 rad[8], lct;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

209

u8 bitmask = 0x80;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

210

u8 bitshift = 7;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

211

u8 array_index = 0;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

213

u8 remainder = 0;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2197

u8 buf[UUID_SIZE];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2328

struct drm_dp_mst_branch *mstb, u8 port_number)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2365

u8 new_pdt = DP_PEER_DEVICE_NONE;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

241

static u8 drm_dp_msg_data_crc4(const uint8_t *data, u8 number_of_bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

243

u8 bitmask = 0x80;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

244

u8 bitshift = 7;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

245

u8 array_index = 0;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2490

u8 new_pdt;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2553

u8 lct, u8 *rad)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2729

u8 port_num, u32 offset, u8 num_bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

274

static inline u8 drm_dp_calc_sb_hdr_size(struct drm_dp_sideband_msg_hdr *hdr)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2741

bool up, u8 *msg, int len)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

276

u8 size = 3;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2775

u8 req_type;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

2804

u8 chunk[48];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

283

u8 *buf, int *len)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

287

u8 crc4;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

304

u8 *buf, int buflen, u8 *hdrlen)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

306

u8 crc4;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

307

u8 len;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

309

u8 idx;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3137

u8 sinks[DRM_DP_MAX_SDP_STREAMS];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3229

u8 nonce[7];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3473

int offset, int size, u8 *bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

350

u8 *buf = raw->msg;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3524

int offset, int size, u8 *bytes)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3559

static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3626

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3628

u8 mstm_cap;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3809

u8 buf[UUID_SIZE];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3878

u8 replyblock[32];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3881

u8 hdrlen;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3920

replylen = min(msg->curchunk_len, (u8)(len - hdrlen));

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3951

static int get_msg_request_type(u8 data)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4242

int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr *mgr, const u8 *esi,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4243

u8 *ack, bool *handled)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

471

const u8 *buf = raw->msg;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4834

static const char *pdt_to_string(u8 pdt)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4973

u8 buf[DP_PAYLOAD_TABLE_SIZE];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6100

u8 upstream_dsc;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6101

u8 endpoint_fec;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6102

u8 endpoint_dsc;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

6170

u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/display/drm_dp_mst_topology.c

73

int offset, int size, u8 *bytes);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

736

static void drm_dp_crc_sideband_chunk_req(u8 *msg, u8 len)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

738

u8 crc4;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

748

u8 *buf = raw->msg;

sys/dev/pci/drm/display/drm_dp_mst_topology.c

757

u8 hdrlen)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

76

int offset, int size, u8 *bytes);

sys/dev/pci/drm/display/drm_dp_mst_topology.c

788

u8 *replybuf, u8 replybuflen)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

790

u8 crc4;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1041

u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1051

u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1052

u8 status_change_mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1053

u8 val;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1197

u8 mask = DP_BW_ALLOCATION_CAPABILITY_CHANGED | DP_ESTIMATED_BW_CHANGED;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1198

u8 val;

sys/dev/pci/drm/display/drm_dp_tunnel.c

124

u8 buf[HWEIGHT64(DPTUN_INFO_REG_MASK)];

sys/dev/pci/drm/display/drm_dp_tunnel.c

1302

u8 val;

sys/dev/pci/drm/display/drm_dp_tunnel.c

144

u8 max_dprx_lane_count;

sys/dev/pci/drm/display/drm_dp_tunnel.c

146

u8 adapter_id;

sys/dev/pci/drm/display/drm_dp_tunnel.c

1630

static int stream_id_to_idx(u32 stream_mask, u8 stream_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1663

u8 stream_id, int bw)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1679

u8 stream_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

1704

u8 stream_id, int bw)

sys/dev/pci/drm/display/drm_dp_tunnel.c

182

u8 drv_group_id;

sys/dev/pci/drm/display/drm_dp_tunnel.c

235

static u8 tunnel_reg(const struct drm_dp_tunnel_regs *regs, int address)

sys/dev/pci/drm/display/drm_dp_tunnel.c

240

static u8 tunnel_reg_drv_group_id(const struct drm_dp_tunnel_regs *regs)

sys/dev/pci/drm/display/drm_dp_tunnel.c

242

u8 drv_id = tunnel_reg(regs, DP_USB4_DRIVER_ID) & DP_USB4_DRIVER_ID_MASK;

sys/dev/pci/drm/display/drm_dp_tunnel.c

243

u8 group_id = tunnel_reg(regs, DP_IN_ADAPTER_TUNNEL_INFORMATION) & DP_GROUP_ID_MASK;

sys/dev/pci/drm/display/drm_dp_tunnel.c

264

u8 bw_code = tunnel_reg(regs, DP_TUNNELING_MAX_LINK_RATE);

sys/dev/pci/drm/display/drm_dp_tunnel.c

277

u8 cap_mask = DP_TUNNELING_SUPPORT | DP_IN_BW_ALLOCATION_MODE_SUPPORT;

sys/dev/pci/drm/display/drm_dp_tunnel.c

292

static u8 tunnel_group_drv_id(u8 drv_group_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

297

static u8 tunnel_group_id(u8 drv_group_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

314

lookup_or_alloc_group(struct drm_dp_tunnel_mgr *mgr, u8 drv_group_id)

sys/dev/pci/drm/display/drm_dp_tunnel.c

456

u8 drv_group_id,

sys/dev/pci/drm/display/drm_dp_tunnel.c

476

u8 drv_group_id = tunnel_reg_drv_group_id(regs);

sys/dev/pci/drm/display/drm_dp_tunnel.c

554

u8 drv_group_id = tunnel_reg_drv_group_id(regs);

sys/dev/pci/drm/display/drm_dp_tunnel.c

625

u8 new_drv_group_id = tunnel_reg_drv_group_id(regs);

sys/dev/pci/drm/display/drm_dp_tunnel.c

719

static int dev_id_len(const u8 *dev_id, int max_len)

sys/dev/pci/drm/display/drm_dp_tunnel.c

914

u8 mask = DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE | DP_UNMASK_BW_ALLOCATION_IRQ;

sys/dev/pci/drm/display/drm_dp_tunnel.c

915

u8 val;

sys/dev/pci/drm/display/drm_dsc_helper.c

1221

u8 bits_per_component)

sys/dev/pci/drm/display/drm_dsc_helper.c

1460

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)

sys/dev/pci/drm/display/drm_dsc_helper.c

334

u8 first_line_bpg_offset;

sys/dev/pci/drm/display/drm_dsc_helper.c

336

u8 flatness_min_qp;

sys/dev/pci/drm/display/drm_dsc_helper.c

337

u8 flatness_max_qp;

sys/dev/pci/drm/display/drm_dsc_helper.c

338

u8 rc_quant_incr_limit0;

sys/dev/pci/drm/display/drm_dsc_helper.c

339

u8 rc_quant_incr_limit1;

sys/dev/pci/drm/display/drm_dsc_helper.c

344

u8 bpp;

sys/dev/pci/drm/display/drm_dsc_helper.c

345

u8 bpc;

sys/dev/pci/drm/display/drm_dsc_helper.c

63

int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)

sys/dev/pci/drm/display/drm_hdcp_helper.c

14

drm_hdcp_check_ksvs_revoked(struct drm_device *drm_dev, u8 *ksvs, u32 ksv_count)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

175

u8 status)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

184

u8 status,

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

185

u8 arb_lost_cnt, u8 nack_cnt,

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

186

u8 low_drive_cnt, u8 error_cnt)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

29

static int drm_connector_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

37

static int drm_connector_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,

sys/dev/pci/drm/display/drm_hdmi_cec_helper.c

89

u8 available_las,

sys/dev/pci/drm/display/drm_hdmi_helper.c

13

static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

385

u8 vic = drm_match_cea_mode(mode);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

934

u8 buffer[HDMI_INFOFRAME_SIZE(MAX)];

sys/dev/pci/drm/display/drm_scdc_helper.c

110

ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,

sys/dev/pci/drm/display/drm_scdc_helper.c

156

u8 status;

sys/dev/pci/drm/display/drm_scdc_helper.c

186

u8 config;

sys/dev/pci/drm/display/drm_scdc_helper.c

246

u8 config;

sys/dev/pci/drm/display/drm_scdc_helper.c

70

ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,

sys/dev/pci/drm/drm_crtc_internal.h

300

const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,

sys/dev/pci/drm/drm_crtc_internal.h

302

void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad);

sys/dev/pci/drm/drm_crtc_internal.h

303

void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);

sys/dev/pci/drm/drm_debugfs.c

642

u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];

sys/dev/pci/drm/drm_debugfs.c

693

u8 buf[HDMI_INFOFRAME_SIZE(MAX)]; \

sys/dev/pci/drm/drm_displayid.c

18

u8 quirks;

sys/dev/pci/drm/drm_displayid.c

192

u8 displayid_version(const struct displayid_iter *iter)

sys/dev/pci/drm/drm_displayid.c

201

u8 displayid_primary_use(const struct displayid_iter *iter)

sys/dev/pci/drm/drm_displayid.c

28

static u8 get_quirks(const struct drm_edid *drm_edid)

sys/dev/pci/drm/drm_displayid.c

41

displayid_get_header(const u8 *displayid, int length, int index)

sys/dev/pci/drm/drm_displayid.c

54

validate_displayid(const u8 *displayid, int length, int idx, bool ignore_checksum)

sys/dev/pci/drm/drm_displayid.c

57

u8 csum = 0;

sys/dev/pci/drm/drm_displayid.c

82

static const u8 *find_next_displayid_extension(struct displayid_iter *iter)

sys/dev/pci/drm/drm_displayid.c

85

const u8 *displayid;

sys/dev/pci/drm/drm_displayid_internal.h

101

u8 tag;

sys/dev/pci/drm/drm_displayid_internal.h

102

u8 rev;

sys/dev/pci/drm/drm_displayid_internal.h

103

u8 num_bytes;

sys/dev/pci/drm/drm_displayid_internal.h

108

u8 tile_cap;

sys/dev/pci/drm/drm_displayid_internal.h

109

u8 topo[3];

sys/dev/pci/drm/drm_displayid_internal.h

110

u8 tile_size[4];

sys/dev/pci/drm/drm_displayid_internal.h

111

u8 tile_pixel_bezel[5];

sys/dev/pci/drm/drm_displayid_internal.h

112

u8 topology_id[8];

sys/dev/pci/drm/drm_displayid_internal.h

116

u8 pixel_clock[3];

sys/dev/pci/drm/drm_displayid_internal.h

117

u8 flags;

sys/dev/pci/drm/drm_displayid_internal.h

134

u8 flags;

sys/dev/pci/drm/drm_displayid_internal.h

137

u8 vrefresh;

sys/dev/pci/drm/drm_displayid_internal.h

150

u8 oui[3];

sys/dev/pci/drm/drm_displayid_internal.h

151

u8 data_structure_type;

sys/dev/pci/drm/drm_displayid_internal.h

152

u8 mso;

sys/dev/pci/drm/drm_displayid_internal.h

163

const u8 *section;

sys/dev/pci/drm/drm_displayid_internal.h

168

u8 version;

sys/dev/pci/drm/drm_displayid_internal.h

169

u8 primary_use;

sys/dev/pci/drm/drm_displayid_internal.h

171

u8 quirks;

sys/dev/pci/drm/drm_displayid_internal.h

182

u8 displayid_version(const struct displayid_iter *iter);

sys/dev/pci/drm/drm_displayid_internal.h

183

u8 displayid_primary_use(const struct displayid_iter *iter);

sys/dev/pci/drm/drm_displayid_internal.h

94

u8 rev;

sys/dev/pci/drm/drm_displayid_internal.h

95

u8 bytes;

sys/dev/pci/drm/drm_displayid_internal.h

96

u8 prod_id;

sys/dev/pci/drm/drm_displayid_internal.h

97

u8 ext_count;

sys/dev/pci/drm/drm_draw.c

100

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_draw.c

139

iosys_map_wr(dmap, off, u8, (color & 0x000000FF) >> 0);

sys/dev/pci/drm/drm_draw.c

140

iosys_map_wr(dmap, off + 1, u8, (color & 0x0000FF00) >> 8);

sys/dev/pci/drm/drm_draw.c

141

iosys_map_wr(dmap, off + 2, u8, (color & 0x00FF0000) >> 16);

sys/dev/pci/drm/drm_draw.c

64

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_draw.c

78

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_draw.c

90

iosys_map_wr(dmap, off, u8, (fg32 & 0x000000FF) >> 0);

sys/dev/pci/drm/drm_draw.c

91

iosys_map_wr(dmap, off + 1, u8, (fg32 & 0x0000FF00) >> 8);

sys/dev/pci/drm/drm_draw.c

92

iosys_map_wr(dmap, off + 2, u8, (fg32 & 0x00FF0000) >> 16);

sys/dev/pci/drm/drm_draw_internal.h

16

static inline bool drm_draw_is_pixel_fg(const u8 *sbuf8, unsigned int spitch, int x, int y)

sys/dev/pci/drm/drm_draw_internal.h

21

static inline const u8 *drm_draw_get_char_bitmap(const struct font_desc *font,

sys/dev/pci/drm/drm_draw_internal.h

30

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_draw_internal.h

35

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_draw_internal.h

40

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_edid.c

1765

static const u8 edid_header[] = {

sys/dev/pci/drm/drm_edid.c

1803

const u8 *block = _block;

sys/dev/pci/drm/drm_edid.c

1805

u8 csum = 0, crc = 0;

sys/dev/pci/drm/drm_edid.c

1824

const u8 *block = _block;

sys/dev/pci/drm/drm_edid.c

2150

drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)

sys/dev/pci/drm/drm_edid.c

2205

u8 last_block;

sys/dev/pci/drm/drm_edid.c

2338

typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);

sys/dev/pci/drm/drm_edid.c

3104

static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)

sys/dev/pci/drm/drm_edid.c

3125

cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)

sys/dev/pci/drm/drm_edid.c

3128

u8 d = ext[0x02];

sys/dev/pci/drm/drm_edid.c

3129

const u8 *det_base = ext + d;

sys/dev/pci/drm/drm_edid.c

3140

vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)

sys/dev/pci/drm/drm_edid.c

3143

const u8 *det_base = ext + 5;

sys/dev/pci/drm/drm_edid.c

3156

const u8 *ext;

sys/dev/pci/drm/drm_edid.c

3340

bad_std_timing(u8 a, u8 b)

sys/dev/pci/drm/drm_edid.c

3640

const struct edid *edid, const u8 *t)

sys/dev/pci/drm/drm_edid.c

3657

const struct edid *edid, const u8 *t)

sys/dev/pci/drm/drm_edid.c

3673

range_pixel_clock(const struct edid *edid, const u8 *t)

sys/dev/pci/drm/drm_edid.c

3693

const u8 *t = (const u8 *)timing;

sys/dev/pci/drm/drm_edid.c

3919

const u8 *est = ((const u8 *)timing) + 6;

sys/dev/pci/drm/drm_edid.c

4057

const u8 empty[3] = { 0, 0, 0 };

sys/dev/pci/drm/drm_edid.c

4210

const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid,

sys/dev/pci/drm/drm_edid.c

4213

const u8 *edid_ext = NULL;

sys/dev/pci/drm/drm_edid.c

4241

const u8 *ext;

sys/dev/pci/drm/drm_edid.c

4270

static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)

sys/dev/pci/drm/drm_edid.c

4282

static u8 cea_num_vics(void)

sys/dev/pci/drm/drm_edid.c

4287

static u8 cea_next_vic(u8 vic)

sys/dev/pci/drm/drm_edid.c

4320

cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)

sys/dev/pci/drm/drm_edid.c

4356

static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,

sys/dev/pci/drm/drm_edid.c

4360

u8 vic;

sys/dev/pci/drm/drm_edid.c

4398

u8 drm_match_cea_mode(const struct drm_display_mode *to_match)

sys/dev/pci/drm/drm_edid.c

4401

u8 vic;

sys/dev/pci/drm/drm_edid.c

4433

static bool drm_valid_cea_vic(u8 vic)

sys/dev/pci/drm/drm_edid.c

4438

static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)

sys/dev/pci/drm/drm_edid.c

4448

static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)

sys/dev/pci/drm/drm_edid.c

4463

static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,

sys/dev/pci/drm/drm_edid.c

4467

u8 vic;

sys/dev/pci/drm/drm_edid.c

4502

static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)

sys/dev/pci/drm/drm_edid.c

4505

u8 vic;

sys/dev/pci/drm/drm_edid.c

4529

static bool drm_valid_hdmi_vic(u8 vic)

sys/dev/pci/drm/drm_edid.c

4553

u8 vic = drm_match_cea_mode(mode);

sys/dev/pci/drm/drm_edid.c

4606

static u8 svd_to_vic(u8 svd)

sys/dev/pci/drm/drm_edid.c

4642

const u8 *svds, u8 svds_len)

sys/dev/pci/drm/drm_edid.c

4648

u8 vic = svd_to_vic(svds[i]);

sys/dev/pci/drm/drm_edid.c

4675

u8 video_code)

sys/dev/pci/drm/drm_edid.c

4778

static int add_hdmi_mode(struct drm_connector *connector, u8 vic)

sys/dev/pci/drm/drm_edid.c

4832

static bool hdmi_vsdb_latency_present(const u8 *db)

sys/dev/pci/drm/drm_edid.c

4837

static bool hdmi_vsdb_i_latency_present(const u8 *db)

sys/dev/pci/drm/drm_edid.c

4842

static int hdmi_vsdb_latency_length(const u8 *db)

sys/dev/pci/drm/drm_edid.c

4862

do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)

sys/dev/pci/drm/drm_edid.c

4865

u8 vic_len, hdmi_3d_len = 0;

sys/dev/pci/drm/drm_edid.c

4897

u8 vic;

sys/dev/pci/drm/drm_edid.c

4985

cea_revision(const u8 *cea)

sys/dev/pci/drm/drm_edid.c

5017

const u8 *collection;

sys/dev/pci/drm/drm_edid.c

5028

u8 tag_length;

sys/dev/pci/drm/drm_edid.c

5029

u8 data[];

sys/dev/pci/drm/drm_edid.c

5059

const u8 *data = cea_db_data(db);

sys/dev/pci/drm/drm_edid.c

5096

static int cea_db_collection_size(const u8 *cta)

sys/dev/pci/drm/drm_edid.c

5098

u8 d = cta[2];

sys/dev/pci/drm/drm_edid.c

5113

const u8 *ext;

sys/dev/pci/drm/drm_edid.c

5284

const u8 *cta;

sys/dev/pci/drm/drm_edid.c

5323

const u8 *data = cea_db_data(db) + 1;

sys/dev/pci/drm/drm_edid.c

5370

modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,

sys/dev/pci/drm/drm_edid.c

5373

const u8 *vdb420 = cea_db_data(db) + 1;

sys/dev/pci/drm/drm_edid.c

5390

u8 vic;

sys/dev/pci/drm/drm_edid.c

54

static int oui(u8 first, u8 second, u8 third)

sys/dev/pci/drm/drm_edid.c

5437

static const u8 pre_computed_values[] = {

sys/dev/pci/drm/drm_edid.c

5477

static uint8_t eotf_supported(const u8 *edid_ext)

sys/dev/pci/drm/drm_edid.c

5486

static uint8_t hdr_metadata_type(const u8 *edid_ext)

sys/dev/pci/drm/drm_edid.c

5493

drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)

sys/dev/pci/drm/drm_edid.c

5518

drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)

sys/dev/pci/drm/drm_edid.c

5520

u8 len = cea_db_payload_len(db);

sys/dev/pci/drm/drm_edid.c

5681

void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)

sys/dev/pci/drm/drm_edid.c

5691

void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)

sys/dev/pci/drm/drm_edid.c

5739

const u8 *data = cea_db_data(db);

sys/dev/pci/drm/drm_edid.c

5760

drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);

sys/dev/pci/drm/drm_edid.c

5836

u8 **sadb)

sys/dev/pci/drm/drm_edid.c

5873

int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)

sys/dev/pci/drm/drm_edid.c

5969

const u8 *edid_ext;

sys/dev/pci/drm/drm_edid.c

5990

const u8 *data = cea_db_data(db);

sys/dev/pci/drm/drm_edid.c

6051

const u8 *svds = cea_db_data(db);

sys/dev/pci/drm/drm_edid.c

6052

u8 *vics;

sys/dev/pci/drm/drm_edid.c

6075

u8 vic = svd_to_vic(svds[i]);

sys/dev/pci/drm/drm_edid.c

6097

u8 vic = info->vics[i];

sys/dev/pci/drm/drm_edid.c

6104

static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)

sys/dev/pci/drm/drm_edid.c

6126

const u8 *svds = cea_db_data(db) + 1;

sys/dev/pci/drm/drm_edid.c

6130

u8 vic = svd_to_vic(svds[i]);

sys/dev/pci/drm/drm_edid.c

6140

static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)

sys/dev/pci/drm/drm_edid.c

6152

void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)

sys/dev/pci/drm/drm_edid.c

6187

const u8 *db)

sys/dev/pci/drm/drm_edid.c

6189

u8 dc_mask;

sys/dev/pci/drm/drm_edid.c

6197

const u8 *hf_scds)

sys/dev/pci/drm/drm_edid.c

6218

u8 dsc_max_slices;

sys/dev/pci/drm/drm_edid.c

6219

u8 dsc_max_frl_rate;

sys/dev/pci/drm/drm_edid.c

6269

const u8 *hf_scds)

sys/dev/pci/drm/drm_edid.c

6275

u8 max_frl_rate = 0;

sys/dev/pci/drm/drm_edid.c

6334

const u8 *hdmi)

sys/dev/pci/drm/drm_edid.c

6395

drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)

sys/dev/pci/drm/drm_edid.c

6398

u8 len = cea_db_payload_len(db);

sys/dev/pci/drm/drm_edid.c

6430

const u8 *db)

sys/dev/pci/drm/drm_edid.c

6433

u8 version = db[4];

sys/dev/pci/drm/drm_edid.c

6452

const u8 *edid_ext;

sys/dev/pci/drm/drm_edid.c

6484

const u8 *data = (const u8 *)db;

sys/dev/pci/drm/drm_edid.c

6910

u8 timing_formula = timings->flags & 0x7;

sys/dev/pci/drm/drm_edid.c

7276

static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,

sys/dev/pci/drm/drm_edid.c

7292

static u8 drm_mode_cea_vic(const struct drm_connector *connector,

sys/dev/pci/drm/drm_edid.c

7317

static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)

sys/dev/pci/drm/drm_edid.c

7341

u8 vic, hdmi_vic;

sys/dev/pci/drm/drm_edid.c

7543

u8 tile_v_loc, tile_h_loc;

sys/dev/pci/drm/drm_edid.c

7544

u8 num_v_tile, num_h_tile;

sys/dev/pci/drm/drm_eld.c

21

int drm_eld_sad_get(const u8 *eld, int sad_index, struct cea_sad *cta_sad)

sys/dev/pci/drm/drm_eld.c

23

const u8 *sad;

sys/dev/pci/drm/drm_eld.c

44

int drm_eld_sad_set(u8 *eld, int sad_index, const struct cea_sad *cta_sad)

sys/dev/pci/drm/drm_eld.c

46

u8 *sad;

sys/dev/pci/drm/drm_fb_helper.c

1164

u8 depth = format->depth;

sys/dev/pci/drm/drm_fb_helper.c

298

static void drm_fb_helper_sysrq(u8 dummy1)

sys/dev/pci/drm/drm_format_helper.c

1001

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

1042

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

1083

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

1127

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

1167

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

1269

u8 *dbuf8 = dbuf;

sys/dev/pci/drm/drm_format_helper.c

1270

const u8 *sbuf8 = sbuf;

sys/dev/pci/drm/drm_format_helper.c

1271

u8 px;

sys/dev/pci/drm/drm_format_helper.c

1275

u8 byte = 0;

sys/dev/pci/drm/drm_format_helper.c

1288

u8 *dbuf8 = dbuf;

sys/dev/pci/drm/drm_format_helper.c

1289

const u8 *sbuf8 = sbuf;

sys/dev/pci/drm/drm_format_helper.c

1293

u8 byte = 0;

sys/dev/pci/drm/drm_format_helper.c

1349

u8 *mono = dst[0].vaddr, *gray8;

sys/dev/pci/drm/drm_format_helper.c

1380

gray8 = (u8 *)src32 + len_src32;

sys/dev/pci/drm/drm_format_helper.c

1437

u8 *gray2 = dst[0].vaddr, *gray8;

sys/dev/pci/drm/drm_format_helper.c

1468

gray8 = (u8 *)src32 + len_src32;

sys/dev/pci/drm/drm_format_helper.c

234

const unsigned int *dst_pitch, const u8 *dst_pixsize,

sys/dev/pci/drm/drm_format_helper.c

266

u8 *dbuf8;

sys/dev/pci/drm/drm_format_helper.c

288

dbuf8 = (u8 __force *)dbuf32;

sys/dev/pci/drm/drm_format_helper.c

347

u8 *dbuf8;

sys/dev/pci/drm/drm_format_helper.c

382

dbuf8 = (u8 __force *)dbuf32;

sys/dev/pci/drm/drm_format_helper.c

506

u8 cpp = DIV_ROUND_UP(drm_format_info_bpp(format, 0), 8);

sys/dev/pci/drm/drm_format_helper.c

556

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

595

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

635

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

675

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

715

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

755

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

795

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

835

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

875

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

917

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_format_helper.c

959

static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {

sys/dev/pci/drm/drm_mipi_dsi.c

1059

ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,

sys/dev/pci/drm/drm_mipi_dsi.c

1064

u8 stack_tx[8];

sys/dev/pci/drm/drm_mipi_dsi.c

1065

u8 *tx;

sys/dev/pci/drm/drm_mipi_dsi.c

1099

ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,

sys/dev/pci/drm/drm_mipi_dsi.c

1125

void mipi_dsi_dcs_read_multi(struct mipi_dsi_multi_context *ctx, u8 cmd,

sys/dev/pci/drm/drm_mipi_dsi.c

1200

int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode)

sys/dev/pci/drm/drm_mipi_dsi.c

1225

int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format)

sys/dev/pci/drm/drm_mipi_dsi.c

1341

u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };

sys/dev/pci/drm/drm_mipi_dsi.c

1368

u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };

sys/dev/pci/drm/drm_mipi_dsi.c

1393

u8 value = mode;

sys/dev/pci/drm/drm_mipi_dsi.c

1416

int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format)

sys/dev/pci/drm/drm_mipi_dsi.c

1444

u8 payload[2] = { scanline >> 8, scanline & 0xff };

sys/dev/pci/drm/drm_mipi_dsi.c

1470

u8 payload[2] = { brightness & 0xff, brightness >> 8 };

sys/dev/pci/drm/drm_mipi_dsi.c

1519

u8 payload[2] = { brightness >> 8, brightness & 0xff };

sys/dev/pci/drm/drm_mipi_dsi.c

1542

u8 brightness_be[2];

sys/dev/pci/drm/drm_mipi_dsi.c

1897

u8 format)

sys/dev/pci/drm/drm_mipi_dsi.c

481

bool mipi_dsi_packet_format_is_short(u8 type)

sys/dev/pci/drm/drm_mipi_dsi.c

519

bool mipi_dsi_packet_format_is_long(u8 type)

sys/dev/pci/drm/drm_mipi_dsi.c

586

const u8 *tx = msg->tx_buf;

sys/dev/pci/drm/drm_mipi_dsi.c

609

.tx_buf = (u8 [2]) { 0, 0 },

sys/dev/pci/drm/drm_mipi_dsi.c

631

.tx_buf = (u8 [2]) { 0, 0 },

sys/dev/pci/drm/drm_mipi_dsi.c

652

u8 tx[2] = { value & 0xff, value >> 8 };

sys/dev/pci/drm/drm_mipi_dsi.c

681

u8 tx[2] = { };

sys/dev/pci/drm/drm_modes.c

2726

u8 vic = drm_match_cea_mode(mode);

sys/dev/pci/drm/drm_modes.c

2746

u8 vic = drm_match_cea_mode(mode);

sys/dev/pci/drm/drm_panic.c

148

const u8 *sbuf8, unsigned int spitch, unsigned int scale,

sys/dev/pci/drm/drm_panic.c

168

u8 *p = vaddr + offset;

sys/dev/pci/drm/drm_panic.c

183

u8 *vaddr2;

sys/dev/pci/drm/drm_panic.c

184

u8 *p = vaddr + offset;

sys/dev/pci/drm/drm_panic.c

234

unsigned int cpp, const u8 *sbuf8,

sys/dev/pci/drm/drm_panic.c

291

const u8 *sbuf8, unsigned int spitch,

sys/dev/pci/drm/drm_panic.c

436

const u8 *src;

sys/dev/pci/drm/drm_panic.c

657

static int drm_panic_get_qr_code_url(u8 **qr_image)

sys/dev/pci/drm/drm_panic.c

714

static int drm_panic_get_qr_code_raw(u8 **qr_image)

sys/dev/pci/drm/drm_panic.c

731

static int drm_panic_get_qr_code(u8 **qr_image)

sys/dev/pci/drm/drm_panic.c

753

u8 *qr_image;

sys/dev/pci/drm/drm_print.c

491

const u8 *buf, size_t len)

sys/dev/pci/drm/hdmi.c

113

u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1565

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1629

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1671

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1722

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1725

u8 hdmi_video_format;

sys/dev/pci/drm/hdmi.c

1802

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1803

const u8 *temp;

sys/dev/pci/drm/hdmi.c

1804

u8 x_lsb, x_msb;

sys/dev/pci/drm/hdmi.c

1805

u8 y_lsb, y_msb;

sys/dev/pci/drm/hdmi.c

1857

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

1893

const u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

284

u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

35

static u8 hdmi_infoframe_checksum(const u8 *ptr, size_t size)

sys/dev/pci/drm/hdmi.c

37

u8 csum = 0;

sys/dev/pci/drm/hdmi.c

393

u8 *buffer)

sys/dev/pci/drm/hdmi.c

395

u8 channels;

sys/dev/pci/drm/hdmi.c

430

u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

49

u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

503

struct dp_sdp *sdp, u8 dp_version)

sys/dev/pci/drm/hdmi.c

614

u8 *ptr = buffer;

sys/dev/pci/drm/hdmi.c

758

u8 *ptr = buffer;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

165

u8 dummy;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

171

static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)

sys/dev/pci/drm/i915/display/dvo_ch7017.c

190

static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)

sys/dev/pci/drm/i915/display/dvo_ch7017.c

192

u8 buf[2] = { addr, val };

sys/dev/pci/drm/i915/display/dvo_ch7017.c

208

u8 val;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

264

u8 lvds_pll_feedback_div, lvds_pll_vco_control;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

265

u8 outputs_enable, lvds_control_2, lvds_power_down;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

266

u8 horizontal_active_pixel_input;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

267

u8 horizontal_active_pixel_output, vertical_active_line_output;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

268

u8 active_input_line_output;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

339

u8 val;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

367

u8 val;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

379

u8 val;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

102

u8 vid;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

113

u8 did;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

124

static char *ch7xxx_get_id(u8 vid)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

136

static char *ch7xxx_get_did(u8 did)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

149

static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

153

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

154

u8 in_buf[2];

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

187

static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

191

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

218

u8 vendor, device;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

261

u8 cdet, orig_pm, pm;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

293

u8 tvco, tpcp, tpd, tlpf, idf;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

345

u8 val;

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

360

u8 val;

sys/dev/pci/drm/i915/display/dvo_ivch.c

198

u8 out_buf[1];

sys/dev/pci/drm/i915/display/dvo_ivch.c

199

u8 in_buf[2];

sys/dev/pci/drm/i915/display/dvo_ivch.c

241

u8 out_buf[3];

sys/dev/pci/drm/i915/display/dvo_ns2501.c

195

u8 offset;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

196

u8 value;

sys/dev/pci/drm/i915/display/dvo_ns2501.c

206

u8 sync; /* configuration of the C0 register */

sys/dev/pci/drm/i915/display/dvo_ns2501.c

207

u8 conf; /* configuration register 8 */

sys/dev/pci/drm/i915/display/dvo_ns2501.c

208

u8 syncb; /* configuration register 41 */

sys/dev/pci/drm/i915/display/dvo_ns2501.c

209

u8 dither; /* configuration of the dithering */

sys/dev/pci/drm/i915/display/dvo_ns2501.c

210

u8 pll_a; /* PLL configuration, register A, 1B */

sys/dev/pci/drm/i915/display/dvo_ns2501.c

393

static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/pci/drm/i915/display/dvo_ns2501.c

397

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_ns2501.c

398

u8 in_buf[2];

sys/dev/pci/drm/i915/display/dvo_ns2501.c

438

static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/pci/drm/i915/display/dvo_ns2501.c

442

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_sil164.c

112

static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/pci/drm/i915/display/dvo_sil164.c

116

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_sil164.c

183

u8 reg9;

sys/dev/pci/drm/i915/display/dvo_sil164.c

258

u8 val;

sys/dev/pci/drm/i915/display/dvo_sil164.c

75

static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/pci/drm/i915/display/dvo_sil164.c

79

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_sil164.c

80

u8 in_buf[2];

sys/dev/pci/drm/i915/display/dvo_tfp410.c

100

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_tfp410.c

101

u8 in_buf[2];

sys/dev/pci/drm/i915/display/dvo_tfp410.c

133

static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/pci/drm/i915/display/dvo_tfp410.c

137

u8 out_buf[2];

sys/dev/pci/drm/i915/display/dvo_tfp410.c

161

u8 ch1, ch2;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

209

u8 ctl2;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

242

u8 ctl1;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

257

u8 ctl1;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

270

u8 val, val2;

sys/dev/pci/drm/i915/display/dvo_tfp410.c

96

static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/pci/drm/i915/display/g4x_dp.c

1037

u8 train_set = intel_dp->train_set[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

1053

static u32 snb_cpu_edp_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/g4x_dp.c

1055

u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |

sys/dev/pci/drm/i915/display/g4x_dp.c

1085

u8 train_set = intel_dp->train_set[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

1101

static u32 ivb_cpu_edp_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/g4x_dp.c

1103

u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |

sys/dev/pci/drm/i915/display/g4x_dp.c

1137

u8 train_set = intel_dp->train_set[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

578

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/g4x_dp.c

619

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/g4x_dp.c

803

static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/g4x_dp.c

809

static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/g4x_dp.c

815

static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/g4x_dp.c

820

static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/g4x_dp.c

831

u8 train_set = intel_dp->train_set[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

917

u8 train_set = intel_dp->train_set[0];

sys/dev/pci/drm/i915/display/g4x_dp.c

994

static u32 g4x_signal_levels(u8 train_set)

sys/dev/pci/drm/i915/display/i9xx_wm.c

1203

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1560

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

1748

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/i9xx_wm.c

2420

static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)

sys/dev/pci/drm/i915/display/i9xx_wm.c

29

u8 default_wm;

sys/dev/pci/drm/i915/display/i9xx_wm.c

30

u8 guard_size;

sys/dev/pci/drm/i915/display/i9xx_wm.c

31

u8 cacheline_size;

sys/dev/pci/drm/i915/display/icl_dsi.c

165

const u8 *data = packet->payload;

sys/dev/pci/drm/i915/display/intel_alpm.c

228

u8 max_wake_lines;

sys/dev/pci/drm/i915/display/intel_alpm.c

447

u8 val;

sys/dev/pci/drm/i915/display/intel_alpm.c

46

u8 dpcd;

sys/dev/pci/drm/i915/display/intel_alpm.c

590

u8 val;

sys/dev/pci/drm/i915/display/intel_audio.c

1236

const u8 *eld = audio_state->eld;

sys/dev/pci/drm/i915/display/intel_audio.c

907

u8 m;

sys/dev/pci/drm/i915/display/intel_backlight.c

176

u8 lbpc;

sys/dev/pci/drm/i915/display/intel_backlight.c

248

u8 lbpc;

sys/dev/pci/drm/i915/display/intel_bios.c

103

const u8 *base = _bdb;

sys/dev/pci/drm/i915/display/intel_bios.c

1370

u8 panel_type = panel->vbt.panel_type;

sys/dev/pci/drm/i915/display/intel_bios.c

148

u8 data[];

sys/dev/pci/drm/i915/display/intel_bios.c

1528

u8 vswing;

sys/dev/pci/drm/i915/display/intel_bios.c

1768

static const u8 *

sys/dev/pci/drm/i915/display/intel_bios.c

1774

const u8 *data = &sequence->data[0];

sys/dev/pci/drm/i915/display/intel_bios.c

1775

u8 current_id;

sys/dev/pci/drm/i915/display/intel_bios.c

1820

const u8 *data, int index, int total)

sys/dev/pci/drm/i915/display/intel_bios.c

1826

u8 operation_byte = *(data + index);

sys/dev/pci/drm/i915/display/intel_bios.c

1859

const u8 *data, int index, int total)

sys/dev/pci/drm/i915/display/intel_bios.c

1892

u8 operation_byte = *(data + index);

sys/dev/pci/drm/i915/display/intel_bios.c

1936

const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];

sys/dev/pci/drm/i915/display/intel_bios.c

1971

u8 *init_otp;

sys/dev/pci/drm/i915/display/intel_bios.c

1994

init_otp = (u8 *)panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];

sys/dev/pci/drm/i915/display/intel_bios.c

2051

const u8 *seq_data;

sys/dev/pci/drm/i915/display/intel_bios.c

2053

u8 *data;

sys/dev/pci/drm/i915/display/intel_bios.c

2088

u8 seq_id = *(data + index);

sys/dev/pci/drm/i915/display/intel_bios.c

2183

static u8 translate_iboost(struct intel_display *display, u8 val)

sys/dev/pci/drm/i915/display/intel_bios.c

2185

static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */

sys/dev/pci/drm/i915/display/intel_bios.c

2195

static const u8 cnp_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2203

static const u8 icp_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2215

static const u8 rkl_pch_tgp_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2222

static const u8 adls_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2230

static const u8 gen9bc_tgp_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2236

static const u8 adlp_ddc_pin_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

2245

static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin)

sys/dev/pci/drm/i915/display/intel_bios.c

2247

const u8 *ddc_pin_map;

sys/dev/pci/drm/i915/display/intel_bios.c

2286

static u8 dvo_port_type(u8 dvo_port)

sys/dev/pci/drm/i915/display/intel_bios.c

2320

const int port_mapping[][3], u8 dvo_port)

sys/dev/pci/drm/i915/display/intel_bios.c

2339

u8 dvo_port)

sys/dev/pci/drm/i915/display/intel_bios.c

2415

dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port)

sys/dev/pci/drm/i915/display/intel_bios.c

3373

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)

sys/dev/pci/drm/i915/display/intel_bios.c

3476

u8 dvo_port = child->dvo_port;

sys/dev/pci/drm/i915/display/intel_bios.c

3590

static const u8 adlp_aux_ch_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

3606

static const u8 adls_aux_ch_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

3618

static const u8 rkl_aux_ch_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

3625

static const u8 direct_aux_ch_map[] = {

sys/dev/pci/drm/i915/display/intel_bios.c

3637

static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)

sys/dev/pci/drm/i915/display/intel_bios.c

3639

const u8 *aux_ch_map;

sys/dev/pci/drm/i915/display/intel_bios.c

3679

u8 aux_channel;

sys/dev/pci/drm/i915/display/intel_bios.c

403

*(u8 *)(ptrs_block + 0) = BDB_LFP_DATA_PTRS;

sys/dev/pci/drm/i915/display/intel_bios.c

487

if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)

sys/dev/pci/drm/i915/display/intel_bios.c

84

static u32 _get_blocksize(const u8 *block_base)

sys/dev/pci/drm/i915/display/intel_bios.h

66

bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin);

sys/dev/pci/drm/i915/display/intel_bw.c

26

u8 active_planes[I915_MAX_DBUF_SLICES];

sys/dev/pci/drm/i915/display/intel_bw.c

37

u8 pipe_sagv_reject;

sys/dev/pci/drm/i915/display/intel_bw.c

392

u8 deburst, deprogbwlimit, derating;

sys/dev/pci/drm/i915/display/intel_bw.c

40

u8 active_pipes;

sys/dev/pci/drm/i915/display/intel_bw.c

469

int num_channels = max_t(u8, 1, dram_info->num_channels);

sys/dev/pci/drm/i915/display/intel_bw.c

540

int num_channels = max_t(u8, 1, dram_info->num_channels);

sys/dev/pci/drm/i915/display/intel_bw.c

56

u8 num_active_planes[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_bw.c

567

num_channels = min_t(u8, num_channels, qi.max_numchannels);

sys/dev/pci/drm/i915/display/intel_bw.c

67

u8 clk; /* clock in multiples of 16.6666 MHz */

sys/dev/pci/drm/i915/display/intel_bw.c

73

u8 num_points;

sys/dev/pci/drm/i915/display/intel_bw.c

74

u8 num_psf_points;

sys/dev/pci/drm/i915/display/intel_bw.c

75

u8 t_bl;

sys/dev/pci/drm/i915/display/intel_bw.c

76

u8 max_numchannels;

sys/dev/pci/drm/i915/display/intel_bw.c

77

u8 channel_width;

sys/dev/pci/drm/i915/display/intel_bw.c

78

u8 deinterleave;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1323

u8 ratio;

sys/dev/pci/drm/i915/display/intel_cdclk.c

140

u8 min_voltage_level[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_cdclk.c

149

u8 active_pipes;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1591

static u8 bxt_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1596

static u8 calc_voltage_level(int cdclk, int num_voltage_levels,

sys/dev/pci/drm/i915/display/intel_cdclk.c

1610

static u8 icl_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

162

u8 (*calc_voltage_level)(int cdclk);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1623

static u8 ehl_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1641

static u8 tgl_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1655

static u8 rplu_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1669

static u8 xe3lpd_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

185

static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2512

u8 voltage_level,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2513

u8 active_pipe_count,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2610

unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2655

unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2933

u8 min_voltage_level;

sys/dev/pci/drm/i915/display/intel_cdclk.c

358

u8 tmp = 0;

sys/dev/pci/drm/i915/display/intel_cdclk.c

391

static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

392

static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

393

static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

394

static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

395

const u8 *div_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

474

static const u8 div_3200[] = { 16, 10, 8 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

475

static const u8 div_4000[] = { 20, 12, 10 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

476

static const u8 div_5333[] = { 24, 16, 14 };

sys/dev/pci/drm/i915/display/intel_cdclk.c

477

const u8 *div_table;

sys/dev/pci/drm/i915/display/intel_cdclk.c

585

static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

821

static u8 bdw_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.c

960

static u8 skl_calc_voltage_level(int cdclk)

sys/dev/pci/drm/i915/display/intel_cdclk.h

20

u8 voltage_level;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

264

u8 lane_mask;

sys/dev/pci/drm/i915/display/intel_crt.c

1011

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_crt.c

705

u8 st00;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2109

u8 lane = INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2258

u8 mpllb_ana_freq_vco;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2259

u8 mpll_div_multiplier;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2274

mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)),

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

250

static u8 __intel_cx0_read(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2534

static u8 intel_c20_get_dp_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2569

static u8 intel_c20_get_hdmi_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2636

u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

274

static u8 intel_cx0_read(struct intel_encoder *encoder,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

275

u8 lane_mask, u16 addr)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2797

static u32 intel_cx0_get_powerdown_update(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2808

static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2820

u8 lane_mask, u8 state)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

283

int lane, u16 addr, u8 data, bool committed)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2871

static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2882

static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2899

u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2900

u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2957

u8 disables;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2959

u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2979

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2997

static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3008

static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3027

u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3252

u8 owned_lane_mask;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3268

u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3281

static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3350

u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

342

int lane, u16 addr, u8 data, bool committed)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3436

u8 expected = mpllb_sw_state->pll[i];

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

363

u8 lane_mask, u16 addr, u8 data, bool committed)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

404

int lane, u16 addr, u8 clear, u8 set, bool committed)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

406

u8 old, val;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

416

u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

418

u8 lane;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

424

static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

438

static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

457

u8 owned_lane_mask;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

492

u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

55

static int lane_mask_to_lane(u8 lane_mask)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

64

static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_ddi.c

1076

enum port port, u8 iboost)

sys/dev/pci/drm/i915/display/intel_ddi.c

1095

u8 iboost;

sys/dev/pci/drm/i915/display/intel_ddi.c

1125

static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_ddi.c

1149

static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_ddi.c

1466

u8 signal_levels)

sys/dev/pci/drm/i915/display/intel_ddi.c

1487

u8 train_set = intel_dp->train_set[lane];

sys/dev/pci/drm/i915/display/intel_ddi.c

1492

u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |

sys/dev/pci/drm/i915/display/intel_ddi.c

2106

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_ddi.c

2173

u8 width;

sys/dev/pci/drm/i915/display/intel_ddi.c

2349

u8 status = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

2478

static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_ddi.c

3815

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/intel_ddi.c

4511

static u8

sys/dev/pci/drm/i915/display/intel_ddi.c

4520

u8 transcoders = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

4561

u8 port_sync_transcoders = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

4684

u8 config;

sys/dev/pci/drm/i915/display/intel_ddi.c

612

u8 master_select =

sys/dev/pci/drm/i915/display/intel_ddi.c

633

u8 master_select =

sys/dev/pci/drm/i915/display/intel_ddi.c

801

u8 *pipe_mask, bool *is_dp_mst)

sys/dev/pci/drm/i915/display/intel_ddi.c

808

u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;

sys/dev/pci/drm/i915/display/intel_ddi.c

91

static const u8 index_to_dp_signal_levels[] = {

sys/dev/pci/drm/i915/display/intel_ddi.c

937

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

17

u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

21

u8 margin; /* swing value */

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

22

u8 scale; /* scale value */

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

23

u8 enable; /* scale enable */

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

24

u8 deemphasis;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

28

u8 dw2_swing_sel;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

29

u8 dw7_n_scalar;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

30

u8 dw4_cursor_coeff;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

31

u8 dw4_post_cursor_2;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

32

u8 dw4_post_cursor_1;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

36

u8 cri_txdeemph_override_11_6;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

37

u8 cri_txdeemph_override_5_0;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

38

u8 cri_txdeemph_override_17_12;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

42

u8 vswing;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

43

u8 preshoot;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

44

u8 de_emphasis;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

48

u8 vswing;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

49

u8 pre_cursor;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

50

u8 post_cursor;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

64

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.h

65

u8 hdmi_default_entry;

sys/dev/pci/drm/i915/display/intel_de.h

34

static inline u8

sys/dev/pci/drm/i915/display/intel_de.h

37

u8 val;

sys/dev/pci/drm/i915/display/intel_display.c

1116

u8 update_planes = crtc_state->update_planes;

sys/dev/pci/drm/i915/display/intel_display.c

1133

u8 update_planes = crtc_state->update_planes;

sys/dev/pci/drm/i915/display/intel_display.c

1152

u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &

sys/dev/pci/drm/i915/display/intel_display.c

271

static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

307

u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

317

u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

327

static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

3438

static u8 joiner_pipes(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

3440

u8 pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3469

u8 *primary_pipes, u8 *secondary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

348

static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

3498

u8 *primary_pipes, u8 *secondary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3529

static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3531

u8 secondary_pipes = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3539

static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3544

static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3549

static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3556

static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3561

static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,

sys/dev/pci/drm/i915/display/intel_display.c

3562

u8 ultrajoiner_secondary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3568

u8 *primary_pipes, u8 *secondary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3601

u8 *primary_pipe, u8 *secondary_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

3603

u8 primary_ultrajoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3604

u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3605

u8 secondary_ultrajoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3606

u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3607

u8 ultrajoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3608

u8 uncompressed_joiner_pipes, bigjoiner_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

364

u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

3718

static u8 hsw_panel_transcoders(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_display.c

3720

u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);

sys/dev/pci/drm/i915/display/intel_display.c

3728

static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)

sys/dev/pci/drm/i915/display/intel_display.c

3731

u8 panel_transcoder_mask = hsw_panel_transcoders(display);

sys/dev/pci/drm/i915/display/intel_display.c

3733

u8 primary_pipe, secondary_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

3734

u8 enabled_transcoders = 0;

sys/dev/pci/drm/i915/display/intel_display.c

3796

static bool has_edp_transcoders(u8 enabled_transcoders)

sys/dev/pci/drm/i915/display/intel_display.c

3801

static bool has_dsi_transcoders(u8 enabled_transcoders)

sys/dev/pci/drm/i915/display/intel_display.c

3807

static bool has_pipe_transcoders(u8 enabled_transcoders)

sys/dev/pci/drm/i915/display/intel_display.c

3815

u8 enabled_transcoders)

sys/dev/pci/drm/i915/display/intel_display.c

3917

u8 primary_pipe, secondary_pipes;

sys/dev/pci/drm/i915/display/intel_display.c

393

u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)

sys/dev/pci/drm/i915/display/intel_display.c

4847

intel_compare_buffer(const u8 *a, const u8 *b, size_t len)

sys/dev/pci/drm/i915/display/intel_display.c

4933

memcmp_diff_len(const u8 *a, const u8 *b, size_t len)

sys/dev/pci/drm/i915/display/intel_display.c

4949

const u8 *a, const u8 *b, size_t len)

sys/dev/pci/drm/i915/display/intel_display.c

5523

const char *reason, u8 mask)

sys/dev/pci/drm/i915/display/intel_display.c

5602

u8 pipe_mask,

sys/dev/pci/drm/i915/display/intel_display.c

5696

u8 intel_calc_active_pipes(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/intel_display.c

5697

u8 active_pipes)

sys/dev/pci/drm/i915/display/intel_display.c

5789

u8 transcoders)

sys/dev/pci/drm/i915/display/intel_display.c

5806

u8 pipes)

sys/dev/pci/drm/i915/display/intel_display.c

6182

u8 affected_pipes = 0;

sys/dev/pci/drm/i915/display/intel_display.c

6183

u8 modeset_pipes = 0;

sys/dev/pci/drm/i915/display/intel_display.c

6445

u8 trans = new_crtc_state->sync_mode_slaves_mask;

sys/dev/pci/drm/i915/display/intel_display.c

6861

u8 disable_pipes = 0;

sys/dev/pci/drm/i915/display/intel_display.c

6956

u8 update_pipes = 0, modeset_pipes = 0;

sys/dev/pci/drm/i915/display/intel_display.h

397

u8 intel_calc_active_pipes(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/intel_display.h

398

u8 active_pipes);

sys/dev/pci/drm/i915/display/intel_display.h

415

u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);

sys/dev/pci/drm/i915/display/intel_display.h

423

u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);

sys/dev/pci/drm/i915/display/intel_display.h

424

u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);

sys/dev/pci/drm/i915/display/intel_display.h

425

u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);

sys/dev/pci/drm/i915/display/intel_display.h

515

const char *reason, u8 pipe_mask);

sys/dev/pci/drm/i915/display/intel_display.h

519

u8 pipe_mask,

sys/dev/pci/drm/i915/display/intel_display_core.h

140

u8 pch_ssc_use;

sys/dev/pci/drm/i915/display/intel_display_core.h

188

u8 hpd_short_storm_enabled;

sys/dev/pci/drm/i915/display/intel_display_core.h

229

u8 override_afc_startup_val;

sys/dev/pci/drm/i915/display/intel_display_core.h

237

u8 initialized;

sys/dev/pci/drm/i915/display/intel_display_core.h

238

u8 dvo_port;

sys/dev/pci/drm/i915/display/intel_display_core.h

239

u8 target_addr;

sys/dev/pci/drm/i915/display/intel_display_core.h

240

u8 dvo_wiring;

sys/dev/pci/drm/i915/display/intel_display_core.h

241

u8 i2c_pin;

sys/dev/pci/drm/i915/display/intel_display_core.h

242

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_display_core.h

272

u8 num_levels;

sys/dev/pci/drm/i915/display/intel_display_core.h

341

u8 num_qgv_points;

sys/dev/pci/drm/i915/display/intel_display_core.h

342

u8 num_psf_gv_points;

sys/dev/pci/drm/i915/display/intel_display_core.h

343

u8 num_planes;

sys/dev/pci/drm/i915/display/intel_display_core.h

367

u8 enabled_slices;

sys/dev/pci/drm/i915/display/intel_display_core.h

472

u8 vblank_enabled;

sys/dev/pci/drm/i915/display/intel_display_core.h

557

u8 phy_failed_calibration;

sys/dev/pci/drm/i915/display/intel_display_core.h

98

u8 eld[MAX_ELD_BYTES];

sys/dev/pci/drm/i915/display/intel_display_device.h

264

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_display_device.h

265

u8 cpu_transcoder_mask;

sys/dev/pci/drm/i915/display/intel_display_device.h

268

u8 num_sprites[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_device.h

269

u8 num_scalers[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_display_device.h

271

u8 fbc_mask;

sys/dev/pci/drm/i915/display/intel_display_device.h

284

u8 abox_mask;

sys/dev/pci/drm/i915/display/intel_display_device.h

288

u8 slice_mask;

sys/dev/pci/drm/i915/display/intel_display_device.h

291

#define DEFINE_FLAG(name) u8 name:1

sys/dev/pci/drm/i915/display/intel_display_irq.c

2075

u8 pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.c

2098

u8 pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_irq.h

36

void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_irq.h

37

void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask);

sys/dev/pci/drm/i915/display/intel_display_power.c

1088

u8 req_slices)

sys/dev/pci/drm/i915/display/intel_display_power.c

1091

u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1120

u8 slices_mask;

sys/dev/pci/drm/i915/display/intel_display_power.c

1590

u8 type;

sys/dev/pci/drm/i915/display/intel_display_power.c

1591

u8 num_channels;

sys/dev/pci/drm/i915/display/intel_display_power.h

298

u8 req_slices);

sys/dev/pci/drm/i915/display/intel_display_power_map.c

44

u8 count;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1778

u8 tries = 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

204

u8 irq_pipe_mask, bool has_vga)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

214

u8 irq_pipe_mask)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

993

u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

994

u8 enabled_dbuf_slices = display->dbuf.enabled_slices;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

126

u8 instance_idx;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

57

u8 count;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

72

u8 idx;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

82

u8 idx;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

85

u8 aux_ch;

sys/dev/pci/drm/i915/display/intel_display_power_well.h

94

u8 count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1129

u8 active_non_psr_pipes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1130

u8 entry_setup_frames;

sys/dev/pci/drm/i915/display/intel_display_types.h

1143

u8 mode_flags;

sys/dev/pci/drm/i915/display/intel_display_types.h

1145

u8 lane_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1151

u8 lane_lat_optim_mask;

sys/dev/pci/drm/i915/display/intel_display_types.h

1154

u8 min_voltage_level;

sys/dev/pci/drm/i915/display/intel_display_types.h

1210

u8 enabled_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1213

u8 active_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1214

u8 scaled_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1215

u8 nv12_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1216

u8 c8_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1219

u8 update_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1222

u8 async_flip_planes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1224

u8 framestart_delay; /* 1-4 */

sys/dev/pci/drm/i915/display/intel_display_types.h

1225

u8 msa_timing_delay; /* 0-3 */

sys/dev/pci/drm/i915/display/intel_display_types.h

1238

u8 eld[MAX_ELD_BYTES];

sys/dev/pci/drm/i915/display/intel_display_types.h

1268

u8 joiner_pipes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1276

u8 slice_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1303

u8 sync_mode_slaves_mask;

sys/dev/pci/drm/i915/display/intel_display_types.h

1322

u8 pipeline_full;

sys/dev/pci/drm/i915/display/intel_display_types.h

1336

u8 link_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1337

u8 pixel_overlap;

sys/dev/pci/drm/i915/display/intel_display_types.h

1390

u8 tail;

sys/dev/pci/drm/i915/display/intel_display_types.h

1402

u8 plane_ids_mask;

sys/dev/pci/drm/i915/display/intel_display_types.h

1405

u8 mode_flags;

sys/dev/pci/drm/i915/display/intel_display_types.h

1489

u8 vtd_guard;

sys/dev/pci/drm/i915/display/intel_display_types.h

1581

u8 video_pattern;

sys/dev/pci/drm/i915/display/intel_display_types.h

1583

u8 bpc;

sys/dev/pci/drm/i915/display/intel_display_types.h

1592

u8 test_lane_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1673

u8 sink_sync_latency;

sys/dev/pci/drm/i915/display/intel_display_types.h

168

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_display_types.h

1687

u8 entry_setup_frames;

sys/dev/pci/drm/i915/display/intel_display_types.h

1692

u8 active_non_psr_pipes;

sys/dev/pci/drm/i915/display/intel_display_types.h

1699

u8 lane_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1700

u8 sink_count;

sys/dev/pci/drm/i915/display/intel_display_types.h

1703

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1704

u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1705

u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1708

u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

sys/dev/pci/drm/i915/display/intel_display_types.h

1709

u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1710

u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1711

u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1712

u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

1738

#define INTEL_DP_LINK_RATE_IDX_BITS (BITS_PER_TYPE(u8) - INTEL_DP_LANE_COUNT_EXP_BITS)

sys/dev/pci/drm/i915/display/intel_display_types.h

1742

u8 link_rate_idx:INTEL_DP_LINK_RATE_IDX_BITS;

sys/dev/pci/drm/i915/display/intel_display_types.h

1743

u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;

sys/dev/pci/drm/i915/display/intel_display_types.h

1772

u8 train_set[4];

sys/dev/pci/drm/i915/display/intel_display_types.h

1808

u8 dp_train_pat);

sys/dev/pci/drm/i915/display/intel_display_types.h

1812

u8 (*preemph_max)(struct intel_dp *intel_dp);

sys/dev/pci/drm/i915/display/intel_display_types.h

1813

u8 (*voltage_max)(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_display_types.h

1824

u8 max_bpc;

sys/dev/pci/drm/i915/display/intel_display_types.h

1853

u8 io_wake_lines;

sys/dev/pci/drm/i915/display/intel_display_types.h

1854

u8 fast_wake_lines;

sys/dev/pci/drm/i915/display/intel_display_types.h

1859

u8 check_entry_lines;

sys/dev/pci/drm/i915/display/intel_display_types.h

1860

u8 aux_less_wake_lines;

sys/dev/pci/drm/i915/display/intel_display_types.h

1861

u8 silence_period_sym_clocks;

sys/dev/pci/drm/i915/display/intel_display_types.h

1862

u8 lfps_half_cycle_num_of_syms;

sys/dev/pci/drm/i915/display/intel_display_types.h

1867

u8 alpm_dpcd;

sys/dev/pci/drm/i915/display/intel_display_types.h

1896

u8 max_lanes;

sys/dev/pci/drm/i915/display/intel_display_types.h

338

u8 seamless_drrs_min_refresh_rate;

sys/dev/pci/drm/i915/display/intel_display_types.h

349

u8 drrs_msa_timing_delay;

sys/dev/pci/drm/i915/display/intel_display_types.h

371

u8 min_brightness; /* min_brightness/255 of max */

sys/dev/pci/drm/i915/display/intel_display_types.h

383

u8 seq_version;

sys/dev/pci/drm/i915/display/intel_display_types.h

385

u8 *data;

sys/dev/pci/drm/i915/display/intel_display_types.h

386

const u8 *sequence[MIPI_SEQ_MAX];

sys/dev/pci/drm/i915/display/intel_display_types.h

387

u8 *deassert_seq; /* Used by fixup_mipi_sequences() */

sys/dev/pci/drm/i915/display/intel_display_types.h

417

u8 controller; /* bxt+ only */

sys/dev/pci/drm/i915/display/intel_display_types.h

472

u8 content_type;

sys/dev/pci/drm/i915/display/intel_display_types.h

544

u8 polled;

sys/dev/pci/drm/i915/display/intel_display_types.h

550

u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_display_types.h

551

u8 fec_capability;

sys/dev/pci/drm/i915/display/intel_display_types.h

553

u8 dsc_hblank_expansion_quirk:1;

sys/dev/pci/drm/i915/display/intel_display_types.h

554

u8 dsc_decompression_enabled:1;

sys/dev/pci/drm/i915/display/intel_display_types.h

723

u8 rotation;

sys/dev/pci/drm/i915/display/intel_display_types.h

798

u8 lines;

sys/dev/pci/drm/i915/display/intel_display_types.h

831

u8 num_levels;

sys/dev/pci/drm/i915/display/intel_dmc.c

1031

u8 *payload;

sys/dev/pci/drm/i915/display/intel_dmc.c

1152

payload = (u8 *)(dmc_header) + header_len_bytes;

sys/dev/pci/drm/i915/display/intel_dmc.c

1205

((u8 *)package_header + sizeof(*package_header));

sys/dev/pci/drm/i915/display/intel_dmc.c

300

u8 reserved1;

sys/dev/pci/drm/i915/display/intel_dmc.c

303

u8 dmc_id;

sys/dev/pci/drm/i915/display/intel_dmc.c

317

u8 header_len;

sys/dev/pci/drm/i915/display/intel_dmc.c

320

u8 header_ver;

sys/dev/pci/drm/i915/display/intel_dmc.c

322

u8 reserved[10];

sys/dev/pci/drm/i915/display/intel_dmc.c

333

u8 header_len;

sys/dev/pci/drm/i915/display/intel_dmc.c

336

u8 header_ver;

sys/dev/pci/drm/i915/display/intel_dmc.c

961

u8 package_ver)

sys/dev/pci/drm/i915/display/intel_dp.c

1014

u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,

sys/dev/pci/drm/i915/display/intel_dp.c

1019

u8 min_slice_count, i;

sys/dev/pci/drm/i915/display/intel_dp.c

1034

min_slice_count = max_t(u8, min_slice_count, 2);

sys/dev/pci/drm/i915/display/intel_dp.c

1044

min_slice_count = max_t(u8, min_slice_count,

sys/dev/pci/drm/i915/display/intel_dp.c

1050

u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;

sys/dev/pci/drm/i915/display/intel_dp.c

111

static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

sys/dev/pci/drm/i915/display/intel_dp.c

125

static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};

sys/dev/pci/drm/i915/display/intel_dp.c

1424

u8 dsc_slice_count = 0;

sys/dev/pci/drm/i915/display/intel_dp.c

1609

u8 *link_bw, u8 *rate_select)

sys/dev/pci/drm/i915/display/intel_dp.c

1827

u8 max_req_bpc)

sys/dev/pci/drm/i915/display/intel_dp.c

1831

u8 dsc_bpc[3] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

1856

static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp.c

1936

u8 sink_dsc_format;

sys/dev/pci/drm/i915/display/intel_dp.c

2115

u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);

sys/dev/pci/drm/i915/display/intel_dp.c

2262

u8 dsc_bpc[3] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

2413

u8 dsc_dp_slice_count;

sys/dev/pci/drm/i915/display/intel_dp.c

249

u8 uhbr_rates = 0;

sys/dev/pci/drm/i915/display/intel_dp.c

3441

write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)

sys/dev/pci/drm/i915/display/intel_dp.c

3444

u8 val;

sys/dev/pci/drm/i915/display/intel_dp.c

3617

u8 oui[] = { 0x00, 0xaa, 0x01 };

sys/dev/pci/drm/i915/display/intel_dp.c

3618

u8 buf[3] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

3666

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)

sys/dev/pci/drm/i915/display/intel_dp.c

3813

static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)

sys/dev/pci/drm/i915/display/intel_dp.c

3869

u8 max_frl_bw_mask, u8 *frl_trained_mask)

sys/dev/pci/drm/i915/display/intel_dp.c

3885

u8 max_frl_bw_mask = 0, frl_trained_mask;

sys/dev/pci/drm/i915/display/intel_dp.c

3961

u8 buf = 0;

sys/dev/pci/drm/i915/display/intel_dp.c

4058

u8 pps_param[6];

sys/dev/pci/drm/i915/display/intel_dp.c

4114

u8 tmp;

sys/dev/pci/drm/i915/display/intel_dp.c

4176

u8 dprx = 0;

sys/dev/pci/drm/i915/display/intel_dp.c

4185

u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp.c

4200

void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_dp.c

4229

static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)

sys/dev/pci/drm/i915/display/intel_dp.c

4311

u8 mso;

sys/dev/pci/drm/i915/display/intel_dp.c

4627

intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)

sys/dev/pci/drm/i915/display/intel_dp.c

4649

static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])

sys/dev/pci/drm/i915/display/intel_dp.c

5116

u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/i915/display/intel_dp.c

5142

intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)

sys/dev/pci/drm/i915/display/intel_dp.c

5158

u8 link_status[DP_LINK_STATUS_SIZE] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

5196

u8 esi[4] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

5197

u8 ack[4] = {};

sys/dev/pci/drm/i915/display/intel_dp.c

5245

u8 buf = 0;

sys/dev/pci/drm/i915/display/intel_dp.c

5268

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp.c

5356

u8 *pipe_mask)

sys/dev/pci/drm/i915/display/intel_dp.c

5418

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp.c

5488

u8 val;

sys/dev/pci/drm/i915/display/intel_dp.c

5513

u8 val;

sys/dev/pci/drm/i915/display/intel_dp.c

5553

u8 old_sink_count = intel_dp->sink_count;

sys/dev/pci/drm/i915/display/intel_dp.c

5599

u8 *dpcd = intel_dp->dpcd;

sys/dev/pci/drm/i915/display/intel_dp.c

5600

u8 type;

sys/dev/pci/drm/i915/display/intel_dp.c

6239

static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)

sys/dev/pci/drm/i915/display/intel_dp.c

6287

u8 transcoders;

sys/dev/pci/drm/i915/display/intel_dp.c

6402

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_dp.c

798

u8 lane_count)

sys/dev/pci/drm/i915/display/intel_dp.h

113

u8 *link_bw, u8 *rate_select);

sys/dev/pci/drm/i915/display/intel_dp.h

138

u8 dsc_max_bpc);

sys/dev/pci/drm/i915/display/intel_dp.h

151

u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,

sys/dev/pci/drm/i915/display/intel_dp.h

202

void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);

sys/dev/pci/drm/i915/display/intel_dp.h

206

u8 lane_count);

sys/dev/pci/drm/i915/display/intel_dp.h

56

u8 *pipe_mask);

sys/dev/pci/drm/i915/display/intel_dp.h

60

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

238

const u8 *send, int send_bytes,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

239

u8 *recv, int recv_size,

sys/dev/pci/drm/i915/display/intel_dp_aux.c

34

u32 intel_dp_aux_pack(const u8 *src, int src_bytes)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

459

intel_dp_aux_header(u8 txbuf[HEADER_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_aux.c

46

static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes)

sys/dev/pci/drm/i915/display/intel_dp_aux.c

487

u8 txbuf[20], rxbuf[20];

sys/dev/pci/drm/i915/display/intel_dp_aux.h

22

u32 intel_dp_aux_pack(const u8 *src, int src_bytes);

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

106

static bool is_intel_tcon_cap(const u8 tcon_cap[4])

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

120

u8 tcon_cap[4];

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

180

u8 tmp;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

181

u8 buf[2] = {};

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

218

u8 buf[4] = {};

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

252

u8 buf[4];

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

272

intel_dp_aux_fill_hdr_tcon_params(const struct drm_connector_state *conn_state, u8 *ctrl)

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

313

u8 old_ctrl, ctrl;

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

379

u8 buf[4] = {};

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

445

u8 buf[3];

sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c

527

u8 current_mode;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

110

u8 *bstatus)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

133

u8 *bcaps)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

154

u8 bcaps;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

166

u8 *ri_prime)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

188

u8 bstatus;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

203

int num_downstream, u8 *ksv_fifo)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

262

u8 bstatus;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

281

u8 bcaps;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

292

u8 msg_id;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

293

u8 stream_type;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

297

u8 msg_id;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

344

u8 *rx_status)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

365

u8 msg_id, bool *msg_ready)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

367

u8 rx_status;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

405

u8 msg_id = hdcp2_msg_data->msg_id;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

441

static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

457

u8 *byte = buf;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

492

u32 *dev_cnt, u8 *byte)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

497

u8 *rx_info = byte;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

516

u8 msg_id, void *buf, size_t size)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

524

u8 *byte = buf;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

59

u8 *an)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

600

bool is_repeater, u8 content_type)

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

62

u8 aksv[DRM_HDCP_KSV_LEN] = {};

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

629

u8 rx_status;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

651

u8 rx_caps[3];

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

703

u8 bcaps;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

809

u8 stream_type;

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

94

u8 *bksv)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1030

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1097

u8 val = DP_TRAINING_PATTERN_DISABLE;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1106

u8 sink_status;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1190

u8 lane_count)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

123

u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1399

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

147

static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1532

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

197

static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

212

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

263

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

284

static u8 dp_voltage_max(u8 preemph)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

299

static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

302

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

310

static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

313

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

334

static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

339

u8 voltage_max;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

357

static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

361

u8 preemph_max;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

389

static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

392

const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

395

u8 tx_ffe = 0;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

409

static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

412

const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

415

u8 v = 0;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

416

u8 p = 0;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

417

u8 voltage_max;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

418

u8 preemph_max;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

445

static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

448

const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

486

const u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

508

u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

532

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

535

u8 buf[sizeof(intel_dp->train_set) + 1];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

549

static char dp_training_pattern_name(u8 train_pat)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

568

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

570

u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

634

u8 dp_train_pat)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

660

static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

676

static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

678

u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

680

u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

698

u8 train_set_lane = intel_dp->train_set[lane];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

714

u8 link_config[2];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

73

static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

751

u8 link_config[] = { link_bw, lane_count };

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

80

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

829

u8 link_bw, u8 rate_select)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

83

u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

843

u8 link_bw, rate_select;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

890

const u8 old_link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

891

const u8 new_link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

896

u8 old, new;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

917

const u8 link_status[DP_LINK_STATUS_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

934

u8 old_link_status[DP_LINK_STATUS_SIZE] = {};

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

936

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

96

const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/i915/display/intel_dp_link_training.h

16

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/i915/display/intel_dp_link_training.h

29

const u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/i915/display/intel_dp_link_training.h

33

u8 dp_train_pat);

sys/dev/pci/drm/i915/display/intel_dp_link_training.h

45

const u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/i915/display/intel_dp_link_training.h

48

static inline u8 intel_dp_training_pattern_symbol(u8 pattern)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1464

u8 dsc_slice_count = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1660

u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1676

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2084

u8 rate_select;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2085

u8 link_bw;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2121

u8 val;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

251

u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?

sys/dev/pci/drm/i915/display/intel_dp_mst.c

467

u8 dsc_bpc[3] = {};

sys/dev/pci/drm/i915/display/intel_dp_mst.c

761

u8 transcoders = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

786

static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

792

u8 mask = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

820

u8 mst_pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

821

u8 fec_pipe_mask = 0;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

855

u8 mst_port_pipes;

sys/dev/pci/drm/i915/display/intel_dp_test.c

113

static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_dp_test.c

116

u8 test_pattern;

sys/dev/pci/drm/i915/display/intel_dp_test.c

117

u8 test_misc;

sys/dev/pci/drm/i915/display/intel_dp_test.c

175

static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_dp_test.c

178

u8 test_result = DP_TEST_ACK;

sys/dev/pci/drm/i915/display/intel_dp_test.c

312

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_test.c

335

static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_dp_test.c

356

u8 response = DP_TEST_NAK;

sys/dev/pci/drm/i915/display/intel_dp_test.c

357

u8 request = 0;

sys/dev/pci/drm/i915/display/intel_dp_test.c

404

u8 *pipe_mask)

sys/dev/pci/drm/i915/display/intel_dp_test.c

456

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp_test.c

75

static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_dp_test.c

80

u8 test_lane_count, test_link_bw;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

122

static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pipe_mask)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

163

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

302

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

303

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

596

u8

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

597

bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

614

u8 lane_lat_optim_mask)

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

635

u8

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

643

u8 mask;

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

102

static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

107

u8 lane_lat_optim_mask)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

110

static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

40

u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

42

u8 lane_lat_optim_mask);

sys/dev/pci/drm/i915/display/intel_dpio_phy.h

43

u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1674

static const u8 even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1679

static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1681

const u8 *list;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2930

static const u8 div1_vals[] = { 7, 5, 3, 2 };

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3119

u8 val = display->vbt.override_afc_startup_val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4638

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4708

u8 pipe_mask = BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

252

u8 tx;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

253

u8 cmn;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

254

u8 pll[20];

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

303

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

368

u8 index;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

373

u8 active_mask;

sys/dev/pci/drm/i915/display/intel_dsi.h

83

u8 eotp_pkt;

sys/dev/pci/drm/i915/display/intel_dsi.h

84

u8 clock_stop;

sys/dev/pci/drm/i915/display/intel_dsi.h

86

u8 escape_clk_div;

sys/dev/pci/drm/i915/display/intel_dsi.h

87

u8 dual_link;

sys/dev/pci/drm/i915/display/intel_dsi.h

92

u8 pixel_overlap;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

104

u8 cabc = POWER_SAVE_OFF;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

112

u8 ctrl = 0;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

137

u8 ctrl = 0;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

153

u8 cabc = POWER_SAVE_MEDIUM;

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

53

u8 data[2] = {};

sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c

72

u8 data[2] = {};

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

105

static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

106

const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

110

u8 type, flags, seq_port;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

184

static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

197

static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

198

const char *con_id, u8 idx, bool value)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

225

u8 gpio_index, const char *chip,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

226

const char *con_id, u8 idx, bool value)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

250

u8 gpio_source, u8 gpio_index, bool value)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

272

u8 gpio_source, u8 gpio_index, bool value)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

315

u8 gpio_index, bool value)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

399

static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

403

u8 gpio_source = 0, gpio_index = 0, gpio_number;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

493

static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

502

u8 vbt_i2c_bus_num = *(data + 2);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

504

u8 reg_offset = *(data + 5);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

505

u8 payload_size = *(data + 6);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

506

u8 *payload_data;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

548

static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

557

static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

584

typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

585

const u8 *data);

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

629

const u8 *data;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

653

u8 operation_byte = *data++;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

654

u8 operation_size = 0;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

666

const u8 *next = data + operation_size;

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

85

u8 seq_port)

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

107

u8 rsvd5;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

117

u8 byte_clk_sel:2;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

118

u8 rsvd6:6;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

156

u8 tclk_miss;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

157

u8 tclk_post;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

158

u8 rsvd12;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

159

u8 tclk_pre;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

160

u8 tclk_prepare;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

161

u8 tclk_settle;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

162

u8 tclk_term_enable;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

163

u8 tclk_trail;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

165

u8 rsvd13;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

166

u8 td_term_enable;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

167

u8 teot;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

168

u8 ths_exit;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

169

u8 ths_prepare;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

171

u8 rsvd14;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

172

u8 ths_settle;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

173

u8 ths_skip;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

174

u8 ths_trail;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

175

u8 tinit;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

176

u8 tlpx;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

177

u8 rsvd15[3];

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

180

u8 panel_enable;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

181

u8 bl_enable;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

182

u8 pwm_enable;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

183

u8 reset_r_n;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

184

u8 pwr_down_r;

sys/dev/pci/drm/i915/display/intel_dsi_vbt_defs.h

185

u8 stdby_r_n;

sys/dev/pci/drm/i915/display/intel_fb.c

219

u8 from;

sys/dev/pci/drm/i915/display/intel_fb.c

220

u8 until;

sys/dev/pci/drm/i915/display/intel_fb.c

230

u8 plane_caps;

sys/dev/pci/drm/i915/display/intel_fb.c

233

u8 cc_planes:3;

sys/dev/pci/drm/i915/display/intel_fb.c

234

u8 packed_aux_planes:4;

sys/dev/pci/drm/i915/display/intel_fb.c

235

u8 planar_aux_planes:4;

sys/dev/pci/drm/i915/display/intel_fb.c

401

u8 tiling_caps;

sys/dev/pci/drm/i915/display/intel_fb.c

445

static bool plane_caps_contain_any(u8 caps, u8 mask)

sys/dev/pci/drm/i915/display/intel_fb.c

450

static bool plane_caps_contain_all(u8 caps, u8 mask)

sys/dev/pci/drm/i915/display/intel_fb.c

540

u8 display_ver_from, u8 display_ver_until)

sys/dev/pci/drm/i915/display/intel_fb.c

547

u8 plane_caps,

sys/dev/pci/drm/i915/display/intel_fb.c

587

u8 plane_caps)

sys/dev/pci/drm/i915/display/intel_fb.c

657

static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,

sys/dev/pci/drm/i915/display/intel_fb.h

46

u8 plane_caps);

sys/dev/pci/drm/i915/display/intel_fbc.c

109

u8 limit;

sys/dev/pci/drm/i915/display/intel_gmbus.c

575

unsigned short addr, u8 *buf, unsigned int len,

sys/dev/pci/drm/i915/display/intel_gmbus.c

639

u8 *buf = msg->buf;

sys/dev/pci/drm/i915/display/intel_gmbus.c

664

unsigned short addr, u8 *buf, unsigned int len,

sys/dev/pci/drm/i915/display/intel_gmbus.c

701

u8 *buf = msg->buf;

sys/dev/pci/drm/i915/display/intel_gmbus.c

927

u8 cmd = DRM_HDCP_DDC_AKSV;

sys/dev/pci/drm/i915/display/intel_gmbus.c

928

u8 buf[DRM_HDCP_KSV_LEN] = {};

sys/dev/pci/drm/i915/display/intel_hdcp.c

1757

u8 *rx_info;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1789

drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v);

sys/dev/pci/drm/i915/display/intel_hdcp.c

185

bool intel_hdcp_is_ksv_valid(u8 *ksv)

sys/dev/pci/drm/i915/display/intel_hdcp.c

199

const struct intel_hdcp_shim *shim, u8 *bksv)

sys/dev/pci/drm/i915/display/intel_hdcp.c

226

u8 bksv[5];

sys/dev/pci/drm/i915/display/intel_hdcp.c

2333

data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2334

data->protocol = (u8)shim->protocol;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2464

hdcp->content_type = (u8)conn_state->hdcp_content_type;

sys/dev/pci/drm/i915/display/intel_hdcp.c

483

u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)

sys/dev/pci/drm/i915/display/intel_hdcp.c

517

u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];

sys/dev/pci/drm/i915/display/intel_hdcp.c

522

u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8);

sys/dev/pci/drm/i915/display/intel_hdcp.c

730

u8 bstatus[2], num_downstream, *ksv_fifo;

sys/dev/pci/drm/i915/display/intel_hdcp.c

821

u8 shim[DRM_HDCP_AN_LEN];

sys/dev/pci/drm/i915/display/intel_hdcp.c

825

u8 shim[DRM_HDCP_KSV_LEN];

sys/dev/pci/drm/i915/display/intel_hdcp.c

829

u8 shim[DRM_HDCP_RI_LEN];

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

109

verify_rxcert_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

110

verify_rxcert_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

177

send_hprime_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

178

send_hprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

232

pairing_info_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

233

pairing_info_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

288

lc_init_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

289

lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

341

verify_lprime_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

342

verify_lprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

397

get_skey_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

398

get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

456

verify_repeater_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

457

verify_repeater_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

46

session_init_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

47

session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

531

verify_mprime_in->port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

532

verify_mprime_in->port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

590

enable_auth_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

591

enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

642

session_close_in.port.physical_port = (u8)data->hdcp_ddi;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c

643

session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder;

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

114

u8 msg_id, void *buf, size_t size);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

122

bool is_repeater, u8 type);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

51

int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

54

int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

63

u8 *bstatus);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

70

int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);

sys/dev/pci/drm/i915/display/intel_hdcp_shim.h

78

int num_downstream, u8 *ksv_fifo);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1305

u8 start = offset & 0xff;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1332

u8 *write_buf;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1359

u8 *an)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1383

u8 *bksv)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1398

u8 *bstatus)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1418

u8 val;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1432

u8 *ri_prime)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1451

u8 val;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1465

int num_downstream, u8 *ksv_fifo)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1577

u8 shim[DRM_HDCP_RI_LEN];

sys/dev/pci/drm/i915/display/intel_hdmi.c

1612

u8 msg_id;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1626

u8 *rx_status)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1634

static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1655

u8 msg_id, bool *msg_ready,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1659

u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];

sys/dev/pci/drm/i915/display/intel_hdmi.c

1683

u8 msg_id, bool paired)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1719

u8 msg_id, void *buf, size_t size)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1757

u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];

sys/dev/pci/drm/i915/display/intel_hdmi.c

1781

u8 hdcp2_version;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2724

static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2727

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2747

static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2750

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2767

static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2770

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2793

static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2807

static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2810

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2830

static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2849

static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2868

static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2873

static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2889

static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2892

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2912

static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2915

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2943

get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2966

static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2971

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

3054

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_hdmi.c

584

static const u8 infoframe_type_to_idx[] = {

sys/dev/pci/drm/i915/display/intel_hdmi.c

656

u8 buffer[VIDEO_DIP_DATA_SIZE];

sys/dev/pci/drm/i915/display/intel_hdmi.c

685

u8 buffer[VIDEO_DIP_DATA_SIZE];

sys/dev/pci/drm/i915/display/intel_link_bw.c

101

u8 pipe_mask,

sys/dev/pci/drm/i915/display/intel_link_bw.c

154

u8 pipe_mask,

sys/dev/pci/drm/i915/display/intel_link_bw.h

18

u8 force_fec_pipes;

sys/dev/pci/drm/i915/display/intel_link_bw.h

19

u8 bpp_limit_reached_pipes;

sys/dev/pci/drm/i915/display/intel_link_bw.h

28

u8 pipe_mask,

sys/dev/pci/drm/i915/display/intel_lspcon.c

137

u8 hdr_caps;

sys/dev/pci/drm/i915/display/intel_lspcon.c

247

u8 rev;

sys/dev/pci/drm/i915/display/intel_lspcon.c

332

u8 avi_if_ctrl;

sys/dev/pci/drm/i915/display/intel_lspcon.c

333

u8 retry;

sys/dev/pci/drm/i915/display/intel_lspcon.c

357

u8 *avi_buf)

sys/dev/pci/drm/i915/display/intel_lspcon.c

359

u8 avi_if_ctrl;

sys/dev/pci/drm/i915/display/intel_lspcon.c

360

u8 block_count = 0;

sys/dev/pci/drm/i915/display/intel_lspcon.c

361

u8 *data;

sys/dev/pci/drm/i915/display/intel_lspcon.c

404

const u8 *frame,

sys/dev/pci/drm/i915/display/intel_lspcon.c

407

u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };

sys/dev/pci/drm/i915/display/intel_lspcon.c

436

const u8 *buffer, ssize_t len)

sys/dev/pci/drm/i915/display/intel_lspcon.c

442

const u8 *data = buffer;

sys/dev/pci/drm/i915/display/intel_lspcon.c

549

u8 buf[VIDEO_DIP_DATA_SIZE];

sys/dev/pci/drm/i915/display/intel_lvds.c

851

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

188

static u8 get_transcoder_pipes(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

189

u8 transcoder_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

192

u8 pipes = 0;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

216

u8 *master_pipe_mask, u8 *slave_pipes_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

245

static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask)

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

248

u8 pipes = 0;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

265

u8 portsync_master_mask;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

266

u8 portsync_slaves_mask;

sys/dev/pci/drm/i915/display/intel_modeset_setup.c

267

u8 joiner_secondaries_mask;

sys/dev/pci/drm/i915/display/intel_opregion.c

104

u8 rsvd2[4];

sys/dev/pci/drm/i915/display/intel_opregion.c

112

u8 rsvd[244];

sys/dev/pci/drm/i915/display/intel_opregion.c

127

u8 plut[74]; /* panel LUT and identifier */

sys/dev/pci/drm/i915/display/intel_opregion.c

139

u8 rsvd[58];

sys/dev/pci/drm/i915/display/intel_opregion.c

145

u8 bddc[256]; /* Panel EDID */

sys/dev/pci/drm/i915/display/intel_opregion.c

146

u8 rsvd[764];

sys/dev/pci/drm/i915/display/intel_opregion.c

65

u8 signature[16];

sys/dev/pci/drm/i915/display/intel_opregion.c

68

u8 rsvd;

sys/dev/pci/drm/i915/display/intel_opregion.c

69

u8 revision;

sys/dev/pci/drm/i915/display/intel_opregion.c

70

u8 minor;

sys/dev/pci/drm/i915/display/intel_opregion.c

71

u8 major;

sys/dev/pci/drm/i915/display/intel_opregion.c

73

u8 bios_ver[32];

sys/dev/pci/drm/i915/display/intel_opregion.c

74

u8 vbios_ver[16];

sys/dev/pci/drm/i915/display/intel_opregion.c

75

u8 driver_ver[16];

sys/dev/pci/drm/i915/display/intel_opregion.c

79

u8 dver[32];

sys/dev/pci/drm/i915/display/intel_opregion.c

80

u8 rsvd[124];

sys/dev/pci/drm/i915/display/intel_opregion.c

88

u8 rsvd1[20];

sys/dev/pci/drm/i915/display/intel_opregion.c

959

u8 major = opregion->header->over.major;

sys/dev/pci/drm/i915/display/intel_overlay.c

216

u8 val;

sys/dev/pci/drm/i915/display/intel_plane.c

1592

u8 plane_ids_mask)

sys/dev/pci/drm/i915/display/intel_plane.c

1632

static u8 intel_joiner_affected_planes(struct intel_atomic_state *state,

sys/dev/pci/drm/i915/display/intel_plane.c

1633

u8 joined_pipes)

sys/dev/pci/drm/i915/display/intel_plane.c

1637

u8 affected_planes = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

1655

u8 joined_pipes)

sys/dev/pci/drm/i915/display/intel_plane.c

1657

u8 prev_affected_planes, affected_planes = 0;

sys/dev/pci/drm/i915/display/intel_plane.c

1731

u8 old_active_planes, new_active_planes;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

23

u8 voltage_index;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

24

u8 qclk_gv_index;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

25

u8 active_pipes;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

26

u8 active_dbufs; /* pre-Xe3 only */

sys/dev/pci/drm/i915/display/intel_pmdemand.c

28

u8 active_phys;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

29

u8 plls;

sys/dev/pci/drm/i915/display/intel_pmdemand.c

33

u8 scalers; /* pre-Xe3 only */

sys/dev/pci/drm/i915/display/intel_pmdemand.c

350

min_t(u8, intel_dbuf_num_enabled_slices(new_dbuf_state), 3);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

352

min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), 3);

sys/dev/pci/drm/i915/display/intel_pmdemand.c

355

min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

490

u8 dbuf_slices)

sys/dev/pci/drm/i915/display/intel_pmdemand.h

34

u8 dbuf_slices);

sys/dev/pci/drm/i915/display/intel_psr.c

1027

u8 idle_frames;

sys/dev/pci/drm/i915/display/intel_psr.c

1057

static const u8 map[] = {

sys/dev/pci/drm/i915/display/intel_psr.c

1672

u8 active_pipes = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

3589

u8 *status, u8 *error_status)

sys/dev/pci/drm/i915/display/intel_psr.c

3631

u8 val;

sys/dev/pci/drm/i915/display/intel_psr.c

3662

u8 status, error_status;

sys/dev/pci/drm/i915/display/intel_psr.c

3663

const u8 errors = DP_PSR_RFB_STORAGE_ERROR |

sys/dev/pci/drm/i915/display/intel_psr.c

3900

u8 active_non_psr_pipes;

sys/dev/pci/drm/i915/display/intel_psr.c

4285

u8 status, error_status;

sys/dev/pci/drm/i915/display/intel_psr.c

481

static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

484

u8 val = 8; /* assume the worst if we can't read the value */

sys/dev/pci/drm/i915/display/intel_psr.c

495

static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

497

u8 su_capability = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

536

u8 y;

sys/dev/pci/drm/i915/display/intel_psr.c

701

static const u8 aux_msg[] = {

sys/dev/pci/drm/i915/display/intel_psr.c

749

u8 val = DP_PANEL_REPLAY_ENABLE |

sys/dev/pci/drm/i915/display/intel_psr.c

754

u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;

sys/dev/pci/drm/i915/display/intel_psr.c

776

u8 val = 0;

sys/dev/pci/drm/i915/display/intel_psr.c

879

static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

981

static u8 frames_before_su_entry(struct intel_dp *intel_dp)

sys/dev/pci/drm/i915/display/intel_psr.c

983

u8 frames_before_su_entry;

sys/dev/pci/drm/i915/display/intel_psr.c

985

frames_before_su_entry = max_t(u8,

sys/dev/pci/drm/i915/display/intel_qp_tables.c

104

static const u8 rc_range_minqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

152

static const u8 rc_range_maxqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

200

static const u8 rc_range_minqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

248

static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

296

static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

314

static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

332

static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

352

static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

38

static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

382

static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

415

static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.c

457

u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)

sys/dev/pci/drm/i915/display/intel_qp_tables.c

467

u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)

sys/dev/pci/drm/i915/display/intel_qp_tables.c

71

static const u8 rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {

sys/dev/pci/drm/i915/display/intel_qp_tables.h

11

u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);

sys/dev/pci/drm/i915/display/intel_qp_tables.h

12

u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);

sys/dev/pci/drm/i915/display/intel_quirks.c

100

u8 sink_oui[3];

sys/dev/pci/drm/i915/display/intel_quirks.c

101

u8 sink_device_id[6];

sys/dev/pci/drm/i915/display/intel_sdvo.c

1008

unsigned int if_index, u8 tx_rate,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1009

const u8 *data, unsigned int length)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1012

u8 set_buf_index[2] = { if_index, 0 };

sys/dev/pci/drm/i915/display/intel_sdvo.c

1013

u8 hbuf_size, tmp[8];

sys/dev/pci/drm/i915/display/intel_sdvo.c

1049

u8 *data, unsigned int length)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1052

u8 set_buf_index[2] = { if_index, 0 };

sys/dev/pci/drm/i915/display/intel_sdvo.c

1053

u8 hbuf_size, tx_rate, av_split;

sys/dev/pci/drm/i915/display/intel_sdvo.c

112

u8 colorimetry_cap;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1138

u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];

sys/dev/pci/drm/i915/display/intel_sdvo.c

1163

u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];

sys/dev/pci/drm/i915/display/intel_sdvo.c

1200

u8 val;

sys/dev/pci/drm/i915/display/intel_sdvo.c

125

u8 dtd_sdvo_flags;

sys/dev/pci/drm/i915/display/intel_sdvo.c

135

u8 tv_format_supported[TV_FORMAT_NUM];

sys/dev/pci/drm/i915/display/intel_sdvo.c

1709

u8 val;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1819

const u8 *eld = crtc_state->eld;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2018

static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)

sys/dev/pci/drm/i915/display/intel_sdvo.c

2020

u8 cap;

sys/dev/pci/drm/i915/display/intel_sdvo.c

253

static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)

sys/dev/pci/drm/i915/display/intel_sdvo.c

2643

u8 pin;

sys/dev/pci/drm/i915/display/intel_sdvo.c

2683

static u8

sys/dev/pci/drm/i915/display/intel_sdvo.c

283

u8 cmd;

sys/dev/pci/drm/i915/display/intel_sdvo.c

3417

u8 byte;

sys/dev/pci/drm/i915/display/intel_sdvo.c

400

static const char *sdvo_cmd_name(u8 cmd)

sys/dev/pci/drm/i915/display/intel_sdvo.c

414

static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/pci/drm/i915/display/intel_sdvo.c

426

BUF_PRINT("%02X ", ((u8 *)args)[i]);

sys/dev/pci/drm/i915/display/intel_sdvo.c

455

static const char *sdvo_cmd_status(u8 status)

sys/dev/pci/drm/i915/display/intel_sdvo.c

463

static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/pci/drm/i915/display/intel_sdvo.c

468

u8 *buf, status;

sys/dev/pci/drm/i915/display/intel_sdvo.c

491

buf[2*i + 1] = ((u8*)args)[i];

sys/dev/pci/drm/i915/display/intel_sdvo.c

533

static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/pci/drm/i915/display/intel_sdvo.c

544

u8 retry = 15; /* 5 quick checks, followed by 10 long checks */

sys/dev/pci/drm/i915/display/intel_sdvo.c

545

u8 status;

sys/dev/pci/drm/i915/display/intel_sdvo.c

602

&((u8 *)response)[i]))

sys/dev/pci/drm/i915/display/intel_sdvo.c

604

BUF_PRINT(" %02X", ((u8 *)response)[i]);

sys/dev/pci/drm/i915/display/intel_sdvo.c

631

u8 ddc_bus)

sys/dev/pci/drm/i915/display/intel_sdvo.c

639

static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)

sys/dev/pci/drm/i915/display/intel_sdvo.c

648

intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)

sys/dev/pci/drm/i915/display/intel_sdvo.c

703

u8 state = SDVO_ENCODER_STATE_ON;

sys/dev/pci/drm/i915/display/intel_sdvo.c

750

static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/pci/drm/i915/display/intel_sdvo.c

757

static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/pci/drm/i915/display/intel_sdvo.c

823

static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)

sys/dev/pci/drm/i915/display/intel_sdvo.c

92

u8 ddc_bus;

sys/dev/pci/drm/i915/display/intel_sdvo.c

938

u8 mode)

sys/dev/pci/drm/i915/display/intel_sdvo.c

944

u8 mode)

sys/dev/pci/drm/i915/display/intel_sdvo.c

950

u8 pixel_repeat)

sys/dev/pci/drm/i915/display/intel_sdvo.c

957

u8 audio_state)

sys/dev/pci/drm/i915/display/intel_sdvo.c

964

u8 *hbuf_size)

sys/dev/pci/drm/i915/display/intel_sdvo.c

981

u8 set_buf_index[2];

sys/dev/pci/drm/i915/display/intel_sdvo.c

982

u8 av_split;

sys/dev/pci/drm/i915/display/intel_sdvo.c

983

u8 buf_size;

sys/dev/pci/drm/i915/display/intel_sdvo.c

984

u8 buf[48];

sys/dev/pci/drm/i915/display/intel_sdvo.c

985

u8 *pos;

sys/dev/pci/drm/i915/display/intel_sdvo.c

99

u8 target_addr;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

100

u8 v_sync_off_high;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

101

u8 reserved;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

114

u8 interlace:1;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

115

u8 scaled:1;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

116

u8 pad:6;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

55

u8 vendor_id;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

553

u8 t0;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

554

u8 t1;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

555

u8 t2;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

556

u8 t3;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

557

u8 t4;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

56

u8 device_id;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

57

u8 device_rev_id;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

570

u8 max_value;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

571

u8 default_value;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

58

u8 sdvo_version_major;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

59

u8 sdvo_version_minor;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

737

u8 dvi_rev;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

738

u8 hdmi_rev;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

79

u8 h_active; /* lower 8 bits (pixels) */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

80

u8 h_blank; /* lower 8 bits (pixels) */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

81

u8 h_high; /* upper 4 bits each h_active, h_blank */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

82

u8 v_active; /* lower 8 bits (lines) */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

83

u8 v_blank; /* lower 8 bits (lines) */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

84

u8 v_high; /* upper 4 bits each v_active, v_blank */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

88

u8 h_sync_off; /* lower 8 bits, from hblank start */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

89

u8 h_sync_width; /* lower 8 bits (pixels) */

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

91

u8 v_sync_off_width;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

96

u8 sync_off_width_high;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

97

u8 dtd_flags;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

98

u8 sdvo_flags;

sys/dev/pci/drm/i915/display/intel_sprite.c

183

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/intel_sprite.c

486

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/intel_sprite.c

60

static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 };

sys/dev/pci/drm/i915/display/intel_sprite.c

600

u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);

sys/dev/pci/drm/i915/display/intel_tc.c

1762

u8 pipe_mask;

sys/dev/pci/drm/i915/display/intel_tc.c

67

u8 phy_fia_idx;

sys/dev/pci/drm/i915/display/intel_tc.c

68

u8 max_lane_count;

sys/dev/pci/drm/i915/display/intel_tv.c

321

u8 oversample;

sys/dev/pci/drm/i915/display/intel_tv.c

322

u8 hsync_end;

sys/dev/pci/drm/i915/display/intel_tv.c

325

u8 vsync_start_f1, vsync_start_f2, vsync_len;

sys/dev/pci/drm/i915/display/intel_tv.c

327

u8 veq_start_f1, veq_start_f2, veq_len;

sys/dev/pci/drm/i915/display/intel_tv.c

328

u8 vi_end_f1, vi_end_f2;

sys/dev/pci/drm/i915/display/intel_tv.c

331

u8 hburst_start, hburst_len;

sys/dev/pci/drm/i915/display/intel_tv.c

332

u8 vburst_start_f1;

sys/dev/pci/drm/i915/display/intel_tv.c

334

u8 vburst_start_f2;

sys/dev/pci/drm/i915/display/intel_tv.c

336

u8 vburst_start_f3;

sys/dev/pci/drm/i915/display/intel_tv.c

338

u8 vburst_start_f4;

sys/dev/pci/drm/i915/display/intel_tv.c

344

u8 dda1_inc;

sys/dev/pci/drm/i915/display/intel_tv.c

65

u8 burst;

sys/dev/pci/drm/i915/display/intel_vblank.c

543

u8 mode_flags = crtc_state->mode_flags;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

102

u8 vbt_checksum;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

103

u8 reserved0;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1063

u8 rate:4; /* ???-223 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1064

u8 lanes:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1065

u8 preemphasis:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1066

u8 vswing:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1075

u8 preemphasis:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1076

u8 vswing:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1126

u8 display_select;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1131

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1145

u8 display_select;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1149

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1150

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

116

u8 signature[16];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1164

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1182

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1183

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1192

u8 panel_type;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1193

u8 panel_type2; /* 212+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1195

u8 pfit_mode:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1196

u8 pfit_text_mode_enhanced:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1197

u8 pfit_gfx_mode_enhanced:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1198

u8 pfit_ratio_auto:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1199

u8 pixel_dither:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1200

u8 lvds_edid:1; /* ???-240 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1201

u8 rsvd2:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1202

u8 rsvd4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1226

u8 table_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1237

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1279

u8 top; /* 227+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1280

u8 bottom; /* 227+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1281

u8 left; /* 238+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1282

u8 right; /* 238+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1288

u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1289

u8 pixel_overlap_count[16]; /* 208+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1303

u8 type:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1304

u8 active_low_pwm:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1305

u8 i2c_pin:3; /* obsolete since ? */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1306

u8 i2c_speed:2; /* obsolete since ? */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1308

u8 min_brightness; /* ???-233 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1309

u8 i2c_address; /* obsolete since ? */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1310

u8 i2c_command; /* obsolete since ? */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1314

u8 type:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1315

u8 controller:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1324

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1326

u8 level[16]; /* 162-233 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1330

u8 brightness_precision_bits[16]; /* 236+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1338

u8 dpst_support:1; /* ???-159 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1339

u8 power_conservation_pref:3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1340

u8 reserved2:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1341

u8 lace_enabled_status:1; /* 210+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1342

u8 lace_support:1; /* 210+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1343

u8 als_enable:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1352

u8 dpst_aggressiveness : 4; /* (228/252)-256 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1353

u8 lace_aggressiveness : 4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1357

u8 opst_aggressiveness : 4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1358

u8 elp_aggressiveness : 4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1362

u8 apd_aggressiveness:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1363

u8 pixoptix_aggressiveness:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1367

u8 xpst_aggressiveness:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1368

u8 tcon_aggressiveness:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1372

u8 panel_technology:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1373

u8 reserved:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1379

u8 lace_aggressiveness_profile:3; /* 210-227 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1380

u8 reserved1:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1410

u8 enable_bfi_in_driver:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1411

u8 enable_brightness_control_in_cui:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1412

u8 reserved:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1413

u8 brightness_percentage_when_bfi_disabled;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1417

u8 bfi_structure_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1426

u8 chromaticity_enable:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1427

u8 chromaticity_from_edid_base_block:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1428

u8 rsvd:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1430

u8 green_y_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1431

u8 green_x_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1432

u8 red_y_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1433

u8 red_x_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1434

u8 white_y_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1435

u8 white_x_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1436

u8 blue_y_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1437

u8 blue_x_lo:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1439

u8 red_x_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1440

u8 red_y_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1441

u8 green_x_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1442

u8 green_y_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1443

u8 blue_x_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1444

u8 blue_y_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1445

u8 white_x_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1446

u8 white_y_hi;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1450

u8 luminance_enable:1; /* 211+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1451

u8 gamma_enable:1; /* 211+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1452

u8 rsvd:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1457

u8 gamma; /* 211+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1516

u8 enable;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1531

u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1539

u8 version;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1540

u8 data[]; /* up to 6 variable length blocks */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1548

u8 is_enabled;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1549

u8 red[256];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1550

u8 blue[256];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1551

u8 green[256];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1567

u8 version_major:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1568

u8 version_minor:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1570

u8 rc_buffer_block_size:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1571

u8 reserved1:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1578

u8 rc_buffer_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1581

u8 line_buffer_depth:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1582

u8 reserved2:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1585

u8 block_prediction_enable:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1586

u8 reserved3:7;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1588

u8 max_bpp; /* mapping */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1591

u8 reserved4:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1592

u8 support_8bpc:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1593

u8 support_10bpc:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1594

u8 support_12bpc:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1595

u8 reserved5:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1610

u8 num_tables;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1611

u8 num_columns;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1633

u8 rsvd_flags:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1634

u8 vsync_positive_polarity:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1635

u8 hsync_positive_polarity:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1637

u8 rsvd[3];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1650

u8 displays_attached;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1651

u8 display_in_pipe_a;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1652

u8 display_in_pipe_b;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

202

u8 panel_fitting:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

203

u8 flexaim:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

204

u8 msg_enable:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

205

u8 clear_screen:3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

206

u8 color_flip:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

209

u8 download_ext_vbt:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

210

u8 enable_ssc:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

211

u8 ssc_freq:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

212

u8 enable_lfp_on_override:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

213

u8 disable_ssc_ddt:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

214

u8 underscan_vga_timings:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

215

u8 display_clock_mode:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

216

u8 vbios_hotplug_support:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

219

u8 disable_smooth_vision:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

220

u8 single_dvi:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

221

u8 rotate_180:1; /* 181+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

222

u8 fdi_rx_polarity_inverted:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

223

u8 vbios_extended_mode:1; /* 160+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

224

u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

225

u8 panel_best_fit_timing:1; /* 160+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

226

u8 ignore_strap_state:1; /* 160+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

229

u8 legacy_monitor_detect;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

232

u8 int_crt_support:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

233

u8 int_tv_support:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

234

u8 int_efp_support:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

235

u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

236

u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

237

u8 dp_ssc_dongle_supported:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

238

u8 rsvd11:2; /* finish byte */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

241

u8 tc_hpd_retry_timeout:7; /* 242+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

242

u8 rsvd12:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

245

u8 afc_startup_config:2; /* 249+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

246

u8 rsvd13:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

47

u8 mfg_week;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

479

u8 device_id[10]; /* ascii string */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

48

u8 mfg_year;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

481

u8 i2c_speed;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

482

u8 dp_onboard_redriver_preemph:3; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

483

u8 dp_onboard_redriver_vswing:3; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

484

u8 dp_onboard_redriver_present:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

485

u8 reserved0:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

486

u8 dp_ondock_redriver_preemph:3; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

487

u8 dp_ondock_redriver_vswing:3; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

488

u8 dp_ondock_redriver_present:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

489

u8 reserved1:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

490

u8 hdmi_level_shifter_value:5; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

491

u8 hdmi_max_data_rate:3; /* 204+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

493

u8 edidless_efp:1; /* 161+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

494

u8 compression_enable:1; /* 198+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

495

u8 compression_method_cps:1; /* 198+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

496

u8 ganged_edp:1; /* 202+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

497

u8 lttpr_non_transparent:1; /* 235+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

498

u8 disable_compression_for_ext_disp:1; /* 251+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

499

u8 reserved2:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

500

u8 compression_structure_index:4; /* 198+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

501

u8 reserved3:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

502

u8 hdmi_max_frl_rate:4; /* 237+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

503

u8 hdmi_max_frl_rate_valid:1; /* 237+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

504

u8 reserved4:3; /* 237+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

505

u8 reserved5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

510

u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

511

u8 i2c_pin;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

512

u8 target_addr;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

513

u8 ddc_pin;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

515

u8 dvo_cfg; /* See DEVICE_CFG_* above */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

519

u8 dvo2_port;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

520

u8 i2c2_pin;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

521

u8 target2_addr;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

522

u8 ddc2_pin;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

525

u8 efp_routed:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

526

u8 lane_reversal:1; /* 184+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

527

u8 lspcon:1; /* 192+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

528

u8 iboost:1; /* 196+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

529

u8 hpd_invert:1; /* 196+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

530

u8 use_vbt_vswing:1; /* 218+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

531

u8 dp_max_lane_count:2; /* 244+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

532

u8 hdmi_support:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

533

u8 dp_support:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

534

u8 tmds_support:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

535

u8 support_reserved:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

536

u8 aux_channel;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

537

u8 dongle_detect;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

541

u8 pipe_cap:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

542

u8 sdvo_stall:1; /* 158+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

543

u8 hpd_status:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

544

u8 integrated_encoder:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

545

u8 capabilities_reserved:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

546

u8 dvo_wiring; /* See DEVICE_WIRE_* above */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

549

u8 dvo2_wiring;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

550

u8 mipi_bridge_type; /* 171+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

554

u8 dvo_function;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

555

u8 dp_usb_type_c:1; /* 195+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

556

u8 tbt:1; /* 209+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

557

u8 flags2_reserved:2; /* 195+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

558

u8 dp_port_trace_length:4; /* 209+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

559

u8 dp_gpio_index; /* 195+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

561

u8 dp_iboost_level:4; /* 196+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

562

u8 hdmi_iboost_level:4; /* 196+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

563

u8 dp_max_link_rate:3; /* 216+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

564

u8 dp_max_link_rate_reserved:5; /* 216+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

565

u8 efp_index; /* 256+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

57

u8 hactive_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

572

u8 crt_ddc_gmbus_pin;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

575

u8 dpms_non_acpi:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

576

u8 skip_boot_crt_detect:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

577

u8 dpms_aim:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

578

u8 rsvd1:5; /* finish byte */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

58

u8 hblank_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

581

u8 boot_display[2];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

582

u8 child_dev_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

59

u8 hblank_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

595

u8 devices[];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

60

u8 hactive_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

603

u8 feature_bits;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

61

u8 vactive_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

613

u8 intel_mode_number[0];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

62

u8 vblank_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

624

u8 color_depths;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

625

u8 refresh_rate[3];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

626

u8 reserved;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

627

u8 text_cols;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

628

u8 text_rows;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

629

u8 font_height;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

63

u8 vblank_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

631

u8 misc;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

64

u8 vactive_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

65

u8 hsync_off_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

652

u8 wm_8bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

653

u8 burst_8bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

654

u8 wm_16bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

655

u8 burst_16bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

656

u8 wm_32bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

657

u8 burst_32bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

66

u8 hsync_pulse_width_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

67

u8 vsync_pulse_width_lo:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

678

u8 data_access_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

68

u8 vsync_off_lo:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

69

u8 vsync_pulse_width_hi:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

693

u8 n;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

694

u8 m1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

695

u8 m2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

696

u8 p1:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

697

u8 p1_div_by_2:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

698

u8 reserved:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

699

u8 p2_div_by_4:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

70

u8 vsync_off_hi:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

71

u8 hsync_pulse_width_hi:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

712

u8 full_link:1; /* 165+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

713

u8 require_aux_to_wakeup:1; /* 165+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

714

u8 feature_bits_rsvd:6;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

717

u8 idle_frames:4; /* 165+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

718

u8 lines_to_wait:3; /* 165+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

719

u8 wait_times_rsvd:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

72

u8 hsync_off_hi:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

73

u8 himage_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

74

u8 vimage_lo;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

740

u8 bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

742

u8 removal_flags;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

747

u8 row_size; /* 8 or 10 bytes */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

75

u8 vimage_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

76

u8 himage_hi:4;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

767

u8 boot_dev_algorithm:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

768

u8 allow_display_switch_dvd:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

769

u8 allow_display_switch_dos:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

77

u8 h_border;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

770

u8 hotplug_dvo:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

771

u8 dual_view_zoom:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

772

u8 int15h_hook:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

773

u8 sprite_in_clone:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

774

u8 primary_lfp_id:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

778

u8 boot_mode_bpp;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

779

u8 boot_mode_refresh;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

78

u8 v_border;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

79

u8 rsvd1:3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

798

u8 static_display:1; /* 163+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

799

u8 embedded_platform:1; /* 163+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

80

u8 digital:2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

800

u8 display_subsystem_enable:1; /* 163+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

801

u8 reserved0:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

805

u8 legacy_crt_max_refresh;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

808

u8 hdmi_termination:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

809

u8 cea861d_hdmi_support:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

81

u8 vsync_positive:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

810

u8 self_refresh_enable:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

811

u8 reserved1:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

813

u8 custom_vbt_version; /* 155+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

82

u8 hsync_positive:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

83

u8 non_interlaced:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

850

u8 persistent_max_config;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

859

u8 n;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

860

u8 m1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

861

u8 m2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

862

u8 p1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

863

u8 p2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

867

u8 row_size; /* 8 == gen2, 9 == gen3+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

868

u8 num_rows;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

877

u8 display_select_pipe_a;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

878

u8 display_select_pipe_b;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

879

u8 caps;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

884

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

898

u8 sv_bits[8];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

906

u8 rotation_enable;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

907

u8 rotation_flags_1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

918

u8 display_select_pipe_a;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

919

u8 display_select_pipe_b;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

923

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

924

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

933

u8 enable_in_vbios:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

934

u8 enable_in_os:1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

935

u8 enable_in_gop:1; /* 207+ */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

936

u8 reserved:5;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

937

u8 display_flags; /* ???-216 */

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

940

u8 color_depth;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

941

u8 refresh_rate;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

947

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

948

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

962

u8 num_entries;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

963

u8 entry_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

972

u8 panel_backlight;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

973

u8 h40_set_panel_type;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

974

u8 panel_type;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

975

u8 ssc_clk_freq;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

978

u8 sclalarcoeff_tab_row_num;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

979

u8 sclalarcoeff_tab_row_size;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

98

u8 signature[20];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

980

u8 coefficient[8];

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

981

u8 panel_misc_bits_1;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

982

u8 panel_misc_bits_2;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

983

u8 panel_misc_bits_3;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

984

u8 panel_misc_bits_4;

sys/dev/pci/drm/i915/display/intel_vdsc.c

167

u8 range_bpg_offset;

sys/dev/pci/drm/i915/display/intel_vdsc.c

215

u8 range_bpg_offset;

sys/dev/pci/drm/i915/display/intel_vga.c

51

u8 sr1;

sys/dev/pci/drm/i915/display/intel_wm_types.h

38

u8 plane[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_wm_types.h

45

u8 level;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1333

u8 alpha = plane_state->hw.alpha >> 8;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1341

u8 alpha = plane_state->hw.alpha >> 8;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

238

static u8 icl_nv12_y_plane_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

253

u8 icl_hdr_plane_mask(void)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2712

static u8 skl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2715

u8 caps = INTEL_PLANE_CAP_TILING_X |

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2731

static u8 glk_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2734

u8 caps = INTEL_PLANE_CAP_TILING_X |

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2744

static u8 icl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2764

static u8 tgl_plane_caps(struct intel_display *display,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2767

u8 caps = INTEL_PLANE_CAP_TILING_X |

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2824

u8 caps;

sys/dev/pci/drm/i915/display/skl_universal_plane.h

40

u8 icl_hdr_plane_mask(void);

sys/dev/pci/drm/i915/display/skl_watermark.c

1165

static bool check_mbus_joined(u8 active_pipes,

sys/dev/pci/drm/i915/display/skl_watermark.c

1177

static bool adlp_check_mbus_joined(u8 active_pipes)

sys/dev/pci/drm/i915/display/skl_watermark.c

1182

static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,

sys/dev/pci/drm/i915/display/skl_watermark.c

1200

static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1218

static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1224

static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1230

static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1236

static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)

sys/dev/pci/drm/i915/display/skl_watermark.c

1605

u8 cpp, u32 latency, u32 dbuf_block_size)

sys/dev/pci/drm/i915/display/skl_watermark.c

2495

static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)

sys/dev/pci/drm/i915/display/skl_watermark.c

2498

u8 enabled_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3075

u8 slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3342

static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)

sys/dev/pci/drm/i915/display/skl_watermark.c

3617

u8 old_slices, new_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3640

u8 old_slices, new_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3728

u8 slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

3844

u8 hw_enabled_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

41

u8 slices[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/skl_watermark.c

411

skl_ddb_entry_for_slices(struct intel_display *display, u8 slice_mask,

sys/dev/pci/drm/i915/display/skl_watermark.c

42

u8 enabled_slices;

sys/dev/pci/drm/i915/display/skl_watermark.c

429

static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)

sys/dev/pci/drm/i915/display/skl_watermark.c

43

u8 active_pipes;

sys/dev/pci/drm/i915/display/skl_watermark.c

44

u8 mdclk_cdclk_ratio;

sys/dev/pci/drm/i915/display/skl_watermark.c

448

u8 slice_mask = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

64

u8 cpp;

sys/dev/pci/drm/i915/display/skl_watermark.c

731

u8 active_pipes;

sys/dev/pci/drm/i915/display/skl_watermark.c

732

u8 dbuf_mask[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/skl_watermark.c

74

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display)

sys/dev/pci/drm/i915/display/skl_watermark.c

76

u8 enabled_slices = 0;

sys/dev/pci/drm/i915/display/skl_watermark.h

23

u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);

sys/dev/pci/drm/i915/display/vlv_dsi.c

104

const u8 *data, u32 len)

sys/dev/pci/drm/i915/display/vlv_dsi.c

120

u8 *data, u32 len)

sys/dev/pci/drm/i915/display/vlv_dsi.c

141

const u8 *header;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1853

static const u8 backlight_off_sequence[16] = {

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

491

u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;

sys/dev/pci/drm/i915/display/vlv_sideband.h

126

static inline u32 vlv_nc_read(struct drm_device *drm, u8 addr)

sys/dev/pci/drm/i915/gem/i915_gem_context_types.h

396

u8 remap_slice;

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

577

u8 x)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

43

static const u8 f_subtile_map[] = {

sys/dev/pci/drm/i915/gt/intel_context_types.h

189

u8 wa_bb_page; /* if set, page num reserved for context workarounds */

sys/dev/pci/drm/i915/gt/intel_context_types.h

212

u8 prio;

sys/dev/pci/drm/i915/gt/intel_context_types.h

285

u8 number_children;

sys/dev/pci/drm/i915/gt/intel_context_types.h

287

u8 child_index;

sys/dev/pci/drm/i915/gt/intel_context_types.h

305

u8 parent_page;

sys/dev/pci/drm/i915/gt/intel_engine.h

278

u32 intel_engine_context_size(struct intel_gt *gt, u8 class);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2153

const u8 num_entries = execlists->csb_size;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2155

u8 read, write;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

273

u32 intel_engine_context_size(struct intel_gt *gt, u8 class)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

396

static u32 get_reset_domain(u8 ver, enum intel_engine_id id)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

450

u8 logical_instance)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

455

u8 guc_class;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

54

u8 class;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

55

u8 instance;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

891

u8 first_ccs = __ffs(CCS_MASK(gt));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

908

static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

909

u8 class, const u8 *map, u8 num_instances)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

912

u8 current_logical_id = 0;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

929

static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

936

const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

942

u8 map[MAX_ENGINE_INSTANCE + 1];

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

963

u8 logical_ids[MAX_ENGINE_INSTANCE + 1];

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

977

u8 instance = intel_engines[i].instance;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

286

u8 csb_size;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

291

u8 csb_head;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

386

u8 class;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

387

u8 instance;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

142

u8 engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

143

u8 sched;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

17

intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

183

const char *intel_engine_class_repr(u8 class)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

202

u8 class;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

203

u8 instance;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

209

u8 base, max;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

98

u8 engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

99

u8 sched;

sys/dev/pci/drm/i915/gt/intel_engine_user.h

15

intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);

sys/dev/pci/drm/i915/gt/intel_engine_user.h

22

const char *intel_engine_class_repr(u8 class);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1705

u8 switch_detail)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1819

const u8 num_entries = execlists->csb_size;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1821

u8 head, tail;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3501

const u8 irq_shifts[] = {

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

122

const u8 class = GEN11_INTR_ENGINE_CLASS(identity);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

123

const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

65

gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

93

static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

208

i915_mcr_reg_t reg, u8 rw_flag,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

285

i915_mcr_reg_t reg, u8 rw_flag,

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

595

u8 *group, u8 *instance)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

664

u8 *group, u8 *instance)

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

697

u8 group, instance;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

728

u8 group, instance;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

748

u8 group, instance;

sys/dev/pci/drm/i915/gt/intel_gt_mcr.h

35

u8 *group, u8 *instance);

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

739

u8 val;

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

773

u8 val;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

242

u8 groupid;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

243

u8 instanceid;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

266

u8 num_engines;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

269

u8 sfc_mask;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

272

u8 vdbox_sfc_access;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

284

u8 uc_index;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

285

u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */

sys/dev/pci/drm/i915/gt/intel_gt_types.h

87

u8 rps_up_threshold;

sys/dev/pci/drm/i915/gt/intel_gt_types.h

88

u8 rps_down_threshold;

sys/dev/pci/drm/i915/gt/intel_gtt.c

349

u8 val;

sys/dev/pci/drm/i915/gt/intel_gtt.h

297

u8 top;

sys/dev/pci/drm/i915/gt/intel_gtt.h

298

u8 pd_shift;

sys/dev/pci/drm/i915/gt/intel_gtt.h

299

u8 scratch_order;

sys/dev/pci/drm/i915/gt/intel_lrc.c

106

static const u8 gen8_xcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

141

static const u8 gen9_xcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

225

static const u8 gen12_xcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

257

static const u8 dg2_xcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

291

static const u8 gen8_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

328

static const u8 gen9_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

412

static const u8 gen11_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

453

static const u8 gen12_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

48

const u8 *data,

sys/dev/pci/drm/i915/gt/intel_lrc.c

549

static const u8 dg2_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

592

static const u8 mtl_rcs_offsets[] = {

sys/dev/pci/drm/i915/gt/intel_lrc.c

63

u8 count, flags;

sys/dev/pci/drm/i915/gt/intel_lrc.c

641

static const u8 *reg_offsets(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

85

u8 v;

sys/dev/pci/drm/i915/gt/intel_migrate.c

531

u32 dst_offset, u8 dst_access,

sys/dev/pci/drm/i915/gt/intel_migrate.c

532

u32 src_offset, u8 src_access, int size)

sys/dev/pci/drm/i915/gt/intel_migrate.c

693

u8 src_access, dst_access;

sys/dev/pci/drm/i915/gt/intel_mocs.c

26

u8 uc_index;

sys/dev/pci/drm/i915/gt/intel_mocs.c

27

u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */

sys/dev/pci/drm/i915/gt/intel_mocs.c

28

u8 unused_entries_index;

sys/dev/pci/drm/i915/gt/intel_reset.c

149

u8 gdrst;

sys/dev/pci/drm/i915/gt/intel_reset.c

178

u8 gdrst;

sys/dev/pci/drm/i915/gt/intel_reset.c

413

u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;

sys/dev/pci/drm/i915/gt/intel_reset.c

503

u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;

sys/dev/pci/drm/i915/gt/intel_rps.c

1077

int intel_rps_set(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

174

static u32 rps_pm_mask(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

1964

u8 new_freq;

sys/dev/pci/drm/i915/gt/intel_rps.c

2605

u8 intel_rps_get_up_threshold(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2610

static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

2642

int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold)

sys/dev/pci/drm/i915/gt/intel_rps.c

2647

u8 intel_rps_get_down_threshold(struct intel_rps *rps)

sys/dev/pci/drm/i915/gt/intel_rps.c

2652

int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold)

sys/dev/pci/drm/i915/gt/intel_rps.c

285

u8 fmax, fmin, fstart;

sys/dev/pci/drm/i915/gt/intel_rps.c

375

static int _pxvid_to_vd(u8 pxvid)

sys/dev/pci/drm/i915/gt/intel_rps.c

386

static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid)

sys/dev/pci/drm/i915/gt/intel_rps.c

440

static int __gen5_rps_set(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

470

static int gen5_rps_set(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

495

u8 pxw[16];

sys/dev/pci/drm/i915/gt/intel_rps.c

564

u8 fstart, vstart;

sys/dev/pci/drm/i915/gt/intel_rps.c

656

static u32 rps_limits(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

747

static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

803

static int gen6_rps_set(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

827

static int vlv_rps_set(struct intel_rps *rps, u8 val)

sys/dev/pci/drm/i915/gt/intel_rps.c

842

static int rps_set(struct intel_rps *rps, u8 val, bool update)

sys/dev/pci/drm/i915/gt/intel_rps.h

35

int intel_rps_set(struct intel_rps *rps, u8 val);

sys/dev/pci/drm/i915/gt/intel_rps.h

40

u8 intel_rps_get_up_threshold(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

41

int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold);

sys/dev/pci/drm/i915/gt/intel_rps.h

42

u8 intel_rps_get_down_threshold(struct intel_rps *rps);

sys/dev/pci/drm/i915/gt/intel_rps.h

43

int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold);

sys/dev/pci/drm/i915/gt/intel_rps_types.h

105

u8 up_threshold; /* Current %busy required to uplock */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

106

u8 down_threshold; /* Current %busy required to downclock */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

22

u8 corr;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

50

u8 rp0_freq;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

51

u8 rp1_freq;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

52

u8 min_freq;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

84

u8 cur_freq; /* Current frequency (cached, may not == HW) */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

85

u8 last_freq; /* Last SWREQ frequency */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

86

u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

87

u8 max_freq_softlimit; /* Max frequency permitted by the driver */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

88

u8 max_freq; /* Maximum frequency, RP0 if not overclocking */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

89

u8 min_freq; /* AKA RPn. Minimum frequency */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

90

u8 boost_freq; /* Frequency to request when wait boosting */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

91

u8 idle_freq; /* Frequency to request when we are idle */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

92

u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

93

u8 rp1_freq; /* "less than" RP0 power/frequency */

sys/dev/pci/drm/i915/gt/intel_rps_types.h

94

u8 rp0_freq; /* Non-overclocked max frequency. */

sys/dev/pci/drm/i915/gt/intel_sseu.c

131

u8 ss_mask[GEN_SS_MASK_SIZE] = {};

sys/dev/pci/drm/i915/gt/intel_sseu.c

14

void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

sys/dev/pci/drm/i915/gt/intel_sseu.c

15

u8 max_subslices, u8 max_eus_per_subslice)

sys/dev/pci/drm/i915/gt/intel_sseu.c

213

u8 eu_en_fuse;

sys/dev/pci/drm/i915/gt/intel_sseu.c

258

u8 eu_en_fuse;

sys/dev/pci/drm/i915/gt/intel_sseu.c

259

u8 s_en;

sys/dev/pci/drm/i915/gt/intel_sseu.c

298

u8 eu_en;

sys/dev/pci/drm/i915/gt/intel_sseu.c

299

u8 s_en;

sys/dev/pci/drm/i915/gt/intel_sseu.c

338

u8 disabled_mask =

sys/dev/pci/drm/i915/gt/intel_sseu.c

347

u8 disabled_mask =

sys/dev/pci/drm/i915/gt/intel_sseu.c

38

intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)

sys/dev/pci/drm/i915/gt/intel_sseu.c

381

const u8 eu_mask = 0xff;

sys/dev/pci/drm/i915/gt/intel_sseu.c

412

u8 eu_disabled_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.c

522

u8 eu_disabled_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.c

570

u8 subslice_mask = 0;

sys/dev/pci/drm/i915/gt/intel_sseu.c

658

u8 slices, subslices;

sys/dev/pci/drm/i915/gt/intel_sseu.c

705

subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {

sys/dev/pci/drm/i915/gt/intel_sseu.c

787

u8 ss_mask = sseu->subslice_mask.hsw[s];

sys/dev/pci/drm/i915/gt/intel_sseu.c

810

u8 ss_mask = sseu->subslice_mask.hsw[s];

sys/dev/pci/drm/i915/gt/intel_sseu.c

97

u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};

sys/dev/pci/drm/i915/gt/intel_sseu.h

102

u8 slice_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.h

103

u8 subslice_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.h

104

u8 min_eus_per_subslice;

sys/dev/pci/drm/i915/gt/intel_sseu.h

105

u8 max_eus_per_subslice;

sys/dev/pci/drm/i915/gt/intel_sseu.h

149

void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

sys/dev/pci/drm/i915/gt/intel_sseu.h

150

u8 max_subslices, u8 max_eus_per_subslice);

sys/dev/pci/drm/i915/gt/intel_sseu.h

156

intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);

sys/dev/pci/drm/i915/gt/intel_sseu.h

60

u8 hsw[GEN_MAX_HSW_SLICES];

sys/dev/pci/drm/i915/gt/intel_sseu.h

69

u8 slice_mask;

sys/dev/pci/drm/i915/gt/intel_sseu.h

79

u8 eu_per_subslice;

sys/dev/pci/drm/i915/gt/intel_sseu.h

80

u8 min_eu_in_pool;

sys/dev/pci/drm/i915/gt/intel_sseu.h

82

u8 subslice_7eu[3];

sys/dev/pci/drm/i915/gt/intel_sseu.h

83

u8 has_slice_pg:1;

sys/dev/pci/drm/i915/gt/intel_sseu.h

84

u8 has_subslice_pg:1;

sys/dev/pci/drm/i915/gt/intel_sseu.h

85

u8 has_eu_pg:1;

sys/dev/pci/drm/i915/gt/intel_sseu.h

90

u8 has_xehp_dss:1;

sys/dev/pci/drm/i915/gt/intel_sseu.h

93

u8 max_slices;

sys/dev/pci/drm/i915/gt/intel_sseu.h

94

u8 max_subslices;

sys/dev/pci/drm/i915/gt/intel_sseu.h

95

u8 max_eus_per_subslice;

sys/dev/pci/drm/i915/gt/intel_sseu_debugfs.c

186

u8 subslice_7eu = info->sseu.subslice_7eu[s];

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2198

u8 mocs_w, mocs_r;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

550

u8 vals[3] = { 0, 0, 0 };

sys/dev/pci/drm/i915/gt/intel_workarounds.c

554

u8 ss;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

896

u8 mocs;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

144

u8 src_access = write_to_ccs ? DIRECT_ACCESS : INDIRECT_ACCESS;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

145

u8 dst_access = write_to_ccs ? INDIRECT_ACCESS : DIRECT_ACCESS;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1268

u8 freq;

sys/dev/pci/drm/i915/gt/selftest_rps.c

151

static u8 wait_for_freq(struct intel_rps *rps, u8 freq, int timeout_ms)

sys/dev/pci/drm/i915/gt/selftest_rps.c

153

u8 history[64], i;

sys/dev/pci/drm/i915/gt/selftest_rps.c

164

u8 act;

sys/dev/pci/drm/i915/gt/selftest_rps.c

188

static u8 rps_set_check(struct intel_rps *rps, u8 freq)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

953

u8 graphics_ver;

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

191

u8 shared_data_header_pad[SLPC_SHARED_DATA_SIZE_BYTE_HEADER -

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

194

u8 platform_info_pad[SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO];

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

197

u8 task_state_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE -

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

201

u8 override_params_pad[SLPC_OVERRIDE_PARAMS_TOTAL_BYTES -

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

204

u8 shared_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_OTHER];

sys/dev/pci/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

207

u8 reserved_mode_definition[4096];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

112

u8 reserved[4];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

129

u8 general_data[4];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

130

u8 reserved3[56];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

24

u8 rom_bypass_vector[16];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

33

u8 flags;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

35

u8 reserved;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

55

u8 version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

56

u8 configuration;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

85

u8 header_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

86

u8 entry_version;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

87

u8 header_length; /* in bytes */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

88

u8 flags;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_binary_headers.h

94

u8 name[12];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

363

u8 group_id;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

366

u8 command;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

369

u8 reserved;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

370

u8 result;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

109

u8 heci_client_id, u32 message_size,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

25

u8 heci_client_id;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

31

u8 reserved1;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

71

u8 heci_client_id, u32 message_size,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

85

u8 heci_client_id, u32 msg_size,

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

527

intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1072

u8 guc_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

242

u8 guc_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

365

u8 group, inst;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

492

u8 guc_class;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

546

u8 engine_class, guc_class;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

612

static struct intel_engine_cs *find_engine_state(struct intel_gt *gt, u8 engine_class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

636

u8 engine_class, guc_class;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

530

u8 *caplist, *tmp;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

165

static u8 engine_class_guc_class_map[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

174

static u8 guc_class_engine_class_map[] = {

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

183

static inline u8 engine_class_to_guc_class(u8 class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

191

static inline u8 guc_class_to_engine_class(u8 guc_class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

259

u8 engine_class;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

260

u8 reserved0[3];

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

392

u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

100

u8 enable_id, u8 disable_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

111

u8 enable_id, u8 disable_id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

133

static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

148

static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

157

static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

207

static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2661

u8 child_index)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2775

static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3644

u8 prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3662

static inline u8 map_i915_prio_to_guc_prio(int prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3675

u8 guc_prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3687

u8 guc_prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3716

static inline bool new_guc_prio_higher(u8 old_guc_prio, u8 new_guc_prio)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3725

u8 new_guc_prio = map_i915_prio_to_guc_prio(rq_prio(rq));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

431

u8 unused[CACHELINE_BYTES - sizeof(u32)];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4337

u8 new_guc_prio = map_i915_prio_to_guc_prio(prio);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

443

u8 unused[WQ_OFFSET - sizeof(union guc_descs) -

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5303

intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5306

u8 engine_class = guc_class_to_engine_class(guc_class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5351

u8 guc_class, instance;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5599

u8 i;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5625

u8 child_index)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5644

u8 i;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5734

u8 i;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

205

u8 major;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

206

u8 minor;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

207

u8 patch;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

249

u8 rev; /* first platform rev using this FW */

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

289

u8 rev = INTEL_REVID(i915);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

31

multi_lrc_create_parent(struct intel_gt *gt, u8 class,

sys/dev/pci/drm/i915/gvt/cfg_space.c

148

u8 old = vgpu_cfg_space(vgpu)[offset];

sys/dev/pci/drm/i915/gvt/cfg_space.c

149

u8 new = *(u8 *)p_data;

sys/dev/pci/drm/i915/gvt/cfg_space.c

150

u8 changed = old ^ new;

sys/dev/pci/drm/i915/gvt/cfg_space.c

326

u8 next;

sys/dev/pci/drm/i915/gvt/cfg_space.c

385

u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];

sys/dev/pci/drm/i915/gvt/cfg_space.c

49

static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {

sys/dev/pci/drm/i915/gvt/cfg_space.c

70

u8 *src, unsigned int bytes)

sys/dev/pci/drm/i915/gvt/cfg_space.c

72

u8 *cfg_base = vgpu_cfg_space(vgpu);

sys/dev/pci/drm/i915/gvt/cfg_space.c

73

u8 mask, new, old;

sys/dev/pci/drm/i915/gvt/display.c

181

static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {

sys/dev/pci/drm/i915/gvt/display.h

85

u8 data[DPCD_SIZE];

sys/dev/pci/drm/i915/gvt/fb_decoder.c

293

u8 bpp; /* Bits per pixel; 0 indicates invalid */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

107

u8 enabled; /* plane is enabled */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

109

u8 bpp; /* bits per pixel */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

122

u8 enabled; /* plane is enabled */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

123

u8 tiled; /* X-tiled */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

124

u8 bpp; /* bits per pixel */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

139

u8 enabled;

sys/dev/pci/drm/i915/gvt/fb_decoder.h

140

u8 mode; /* cursor mode select */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

141

u8 bpp; /* bits per pixel */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

147

u8 x_sign; /* X Position Sign */

sys/dev/pci/drm/i915/gvt/fb_decoder.h

148

u8 y_sign; /* Y Position Sign */

sys/dev/pci/drm/i915/gvt/firmware.c

166

id = *(u8 *)(mem + PCI_REVISION_ID);

sys/dev/pci/drm/i915/gvt/handlers.c

1141

u8 t)

sys/dev/pci/drm/i915/gvt/handlers.c

1229

u8 buf[16];

sys/dev/pci/drm/i915/gvt/kvmgt.c

109

static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,

sys/dev/pci/drm/i915/gvt/kvmgt.c

1355

u8 *data = NULL;

sys/dev/pci/drm/i915/gvt/kvmgt.c

1589

static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,

sys/dev/pci/drm/i915/gvt/kvmgt.c

914

u8 val;

sys/dev/pci/drm/i915/gvt/kvmgt.c

989

u8 val;

sys/dev/pci/drm/i915/gvt/opregion.c

100

u8 dp_compat:1;

sys/dev/pci/drm/i915/gvt/opregion.c

101

u8 tmds_compat:1;

sys/dev/pci/drm/i915/gvt/opregion.c

102

u8 skip4:5;

sys/dev/pci/drm/i915/gvt/opregion.c

103

u8 aux_channel;

sys/dev/pci/drm/i915/gvt/opregion.c

104

u8 dongle_detect;

sys/dev/pci/drm/i915/gvt/opregion.c

105

u8 pipe_cap:2;

sys/dev/pci/drm/i915/gvt/opregion.c

106

u8 sdvo_stall:1; /* 158 */

sys/dev/pci/drm/i915/gvt/opregion.c

107

u8 hpd_status:2;

sys/dev/pci/drm/i915/gvt/opregion.c

108

u8 integrated_encoder:1;

sys/dev/pci/drm/i915/gvt/opregion.c

109

u8 skip5:2;

sys/dev/pci/drm/i915/gvt/opregion.c

110

u8 dvo_wiring;

sys/dev/pci/drm/i915/gvt/opregion.c

111

u8 mipi_bridge_type; /* 171 */

sys/dev/pci/drm/i915/gvt/opregion.c

113

u8 dvo_function;

sys/dev/pci/drm/i915/gvt/opregion.c

222

u8 *buf;

sys/dev/pci/drm/i915/gvt/opregion.c

236

buf = (u8 *)vgpu_opregion(vgpu)->va;

sys/dev/pci/drm/i915/gvt/opregion.c

46

u8 signature[16];

sys/dev/pci/drm/i915/gvt/opregion.c

49

u8 bios_ver[32];

sys/dev/pci/drm/i915/gvt/opregion.c

50

u8 vbios_ver[16];

sys/dev/pci/drm/i915/gvt/opregion.c

51

u8 driver_ver[16];

sys/dev/pci/drm/i915/gvt/opregion.c

55

u8 dver[32];

sys/dev/pci/drm/i915/gvt/opregion.c

56

u8 rsvd[124];

sys/dev/pci/drm/i915/gvt/opregion.c

60

u8 id;

sys/dev/pci/drm/i915/gvt/opregion.c

72

u8 i2c_speed;

sys/dev/pci/drm/i915/gvt/opregion.c

73

u8 dp_onboard_redriver; /* 158 */

sys/dev/pci/drm/i915/gvt/opregion.c

74

u8 dp_ondock_redriver; /* 158 */

sys/dev/pci/drm/i915/gvt/opregion.c

75

u8 hdmi_level_shifter_value:4; /* 169 */

sys/dev/pci/drm/i915/gvt/opregion.c

76

u8 hdmi_max_data_rate:4; /* 204 */

sys/dev/pci/drm/i915/gvt/opregion.c

78

u8 edidless_efp:1; /* 161 */

sys/dev/pci/drm/i915/gvt/opregion.c

79

u8 compression_enable:1; /* 198 */

sys/dev/pci/drm/i915/gvt/opregion.c

80

u8 compression_method:1; /* 198 */

sys/dev/pci/drm/i915/gvt/opregion.c

81

u8 ganged_edp:1; /* 202 */

sys/dev/pci/drm/i915/gvt/opregion.c

82

u8 skip0:4;

sys/dev/pci/drm/i915/gvt/opregion.c

83

u8 compression_structure_index:4; /* 198 */

sys/dev/pci/drm/i915/gvt/opregion.c

84

u8 skip1:4;

sys/dev/pci/drm/i915/gvt/opregion.c

85

u8 slave_port; /* 202 */

sys/dev/pci/drm/i915/gvt/opregion.c

86

u8 skip2;

sys/dev/pci/drm/i915/gvt/opregion.c

87

u8 dvo_port;

sys/dev/pci/drm/i915/gvt/opregion.c

88

u8 i2c_pin; /* for add-in card */

sys/dev/pci/drm/i915/gvt/opregion.c

89

u8 target_addr; /* for add-in card */

sys/dev/pci/drm/i915/gvt/opregion.c

90

u8 ddc_pin;

sys/dev/pci/drm/i915/gvt/opregion.c

92

u8 dvo_config;

sys/dev/pci/drm/i915/gvt/opregion.c

93

u8 efp_docked_port:1; /* 158 */

sys/dev/pci/drm/i915/gvt/opregion.c

94

u8 lane_reversal:1; /* 184 */

sys/dev/pci/drm/i915/gvt/opregion.c

95

u8 onboard_lspcon:1; /* 192 */

sys/dev/pci/drm/i915/gvt/opregion.c

96

u8 iboost_enable:1; /* 196 */

sys/dev/pci/drm/i915/gvt/opregion.c

97

u8 hpd_invert:1; /* BXT 196 */

sys/dev/pci/drm/i915/gvt/opregion.c

98

u8 slip3:3;

sys/dev/pci/drm/i915/gvt/opregion.c

99

u8 hdmi_compat:1;

sys/dev/pci/drm/i915/gvt/trace.h

229

TP_PROTO(u8 vgpu_id, u8 ring_id, u32 ip_gma, u32 *cmd_va,

sys/dev/pci/drm/i915/gvt/trace.h

237

__field(u8, vgpu_id)

sys/dev/pci/drm/i915/gvt/trace.h

238

__field(u8, ring_id)

sys/dev/pci/drm/i915/i915_drv.h

180

u8 *initial_cfg_space;

sys/dev/pci/drm/i915/i915_ioctl.c

25

u8 min_graphics_ver;

sys/dev/pci/drm/i915/i915_ioctl.c

26

u8 max_graphics_ver;

sys/dev/pci/drm/i915/i915_ioctl.c

27

u8 size;

sys/dev/pci/drm/i915/i915_irq.c

164

u8 slice = 0;

sys/dev/pci/drm/i915/i915_perf.c

1054

u8 *oa_buf_base = stream->oa_buffer.vaddr;

sys/dev/pci/drm/i915/i915_perf.c

1089

u8 *report = oa_buf_base + head;

sys/dev/pci/drm/i915/i915_perf.c

4017

u8 class, instance;

sys/dev/pci/drm/i915/i915_perf.c

4161

class = (u8)value;

sys/dev/pci/drm/i915/i915_perf.c

4165

instance = (u8)value;

sys/dev/pci/drm/i915/i915_perf.c

677

const u8 *report)

sys/dev/pci/drm/i915/i915_perf.c

682

u8 *oa_buf_end;

sys/dev/pci/drm/i915/i915_perf.c

744

u8 *oa_buf_base = stream->oa_buffer.vaddr;

sys/dev/pci/drm/i915/i915_perf.c

779

u8 *report = oa_buf_base + head;

sys/dev/pci/drm/i915/i915_perf.c

899

u8 *oa_buf_end = stream->oa_buffer.vaddr +

sys/dev/pci/drm/i915/i915_perf.c

901

u32 part = oa_buf_end - (u8 *)report32;

sys/dev/pci/drm/i915/i915_perf_types.h

291

u8 *vaddr;

sys/dev/pci/drm/i915/i915_pmu.c

41

static u8 engine_config_sample(u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

46

static u8 engine_event_sample(struct perf_event *event)

sys/dev/pci/drm/i915/i915_pmu.c

51

static u8 engine_event_class(struct perf_event *event)

sys/dev/pci/drm/i915/i915_pmu.c

56

static u8 engine_event_instance(struct perf_event *event)

sys/dev/pci/drm/i915/i915_pmu.c

664

u8 sample = engine_event_sample(event);

sys/dev/pci/drm/i915/i915_pmu.c

766

u8 sample = engine_event_sample(event);

sys/dev/pci/drm/i915/i915_pmu.c

809

u8 sample = engine_event_sample(event);

sys/dev/pci/drm/i915/i915_query.c

113

engine = intel_engine_lookup_user(i915, (u8)classinstance.engine_class,

sys/dev/pci/drm/i915/i915_query.c

114

(u8)classinstance.engine_instance);

sys/dev/pci/drm/i915/i915_query.c

42

BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));

sys/dev/pci/drm/i915/i915_reg_defs.h

175

#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))

sys/dev/pci/drm/i915/i915_reg_defs.h

59

((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \

sys/dev/pci/drm/i915/i915_request.c

239

static void __i915_request_fill(struct i915_request *rq, u8 val)

sys/dev/pci/drm/i915/i915_request.h

350

u8 guc_prio;

sys/dev/pci/drm/i915/intel_device_info.c

304

u8 expected_ver = ip->ver;

sys/dev/pci/drm/i915/intel_device_info.c

305

u8 expected_rel = ip->rel;

sys/dev/pci/drm/i915/intel_device_info.h

185

u8 ver;

sys/dev/pci/drm/i915/intel_device_info.h

186

u8 rel;

sys/dev/pci/drm/i915/intel_device_info.h

187

u8 step;

sys/dev/pci/drm/i915/intel_device_info.h

231

u8 gt; /* GT number, 0 if undefined */

sys/dev/pci/drm/i915/intel_device_info.h

236

#define DEFINE_FLAG(name) u8 name:1

sys/dev/pci/drm/i915/intel_memory_region.c

37

u8 __iomem *va, int pagesize,

sys/dev/pci/drm/i915/intel_memory_region.c

38

u8 value, resource_size_t offset,

sys/dev/pci/drm/i915/intel_memory_region.c

42

u8 result[3];

sys/dev/pci/drm/i915/intel_memory_region.c

68

const u8 val[] = { 0x0, 0xa5, 0xc3, 0xf0 };

sys/dev/pci/drm/i915/intel_step.c

135

static u8 gmd_to_intel_step(struct drm_i915_private *i915,

sys/dev/pci/drm/i915/intel_step.c

138

u8 step = gmd->step + STEP_A0;

sys/dev/pci/drm/i915/intel_step.h

18

u8 graphics_step; /* Represents the compute tile on Xe_HPC */

sys/dev/pci/drm/i915/intel_step.h

19

u8 media_step;

sys/dev/pci/drm/i915/intel_uncore.h

102

u8 (*mmio_readb)(struct intel_uncore *uncore,

sys/dev/pci/drm/i915/intel_uncore.h

112

i915_reg_t r, u8 val, bool trace);

sys/dev/pci/drm/i915/pxp/intel_pxp_huc.c

24

u8 client_id = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_huc.c

25

u8 fence_id = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.c

109

u8 client_id, u32 fence_id,

sys/dev/pci/drm/i915/pxp/intel_pxp_tee.h

18

u8 client_id, u32 fence_id,

sys/dev/pci/drm/i915/selftests/intel_uncore.c

145

u8 min_graphics_ver;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

146

u8 max_graphics_ver;

sys/dev/pci/drm/i915/soc/intel_dram.c

23

u8 width, ranks;

sys/dev/pci/drm/i915/soc/intel_dram.c

28

u8 ranks;

sys/dev/pci/drm/i915/soc/intel_dram.c

565

u8 valid_ranks = 0;

sys/dev/pci/drm/i915/soc/intel_dram.c

786

static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };

sys/dev/pci/drm/i915/soc/intel_dram.c

787

static const u8 sets[4] = { 1, 1, 2, 2 };

sys/dev/pci/drm/i915/soc/intel_dram.h

30

u8 num_channels;

sys/dev/pci/drm/i915/soc/intel_dram.h

31

u8 num_qgv_points;

sys/dev/pci/drm/i915/soc/intel_dram.h

32

u8 num_psf_gv_points;

sys/dev/pci/drm/i915/soc/intel_rom.c

109

rom->oprom = (u8 *)ISA_HOLE_VADDR(VGA_BIOS_ADDR);

sys/dev/pci/drm/include/drm/amd_asic_type.h

76

u8 revision; /* revision ID */

sys/dev/pci/drm/include/drm/display/drm_dp.h

1715

u8 HB0;

sys/dev/pci/drm/include/drm/display/drm_dp.h

1716

u8 HB1;

sys/dev/pci/drm/include/drm/display/drm_dp.h

1717

u8 HB2;

sys/dev/pci/drm/include/drm/display/drm_dp.h

1718

u8 HB3;

sys/dev/pci/drm/include/drm/display/drm_dp.h

1748

u8 db[32];

sys/dev/pci/drm/include/drm/display/drm_dp_dual_mode_helper.h

69

u8 offset, void *buffer, size_t size);

sys/dev/pci/drm/include/drm/display/drm_dp_dual_mode_helper.h

71

u8 offset, const void *buffer, size_t size);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

134

bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

135

bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

137

int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

140

drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

145

static inline u8

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

146

drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

152

drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

159

drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

166

drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

173

drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

180

drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

186

static inline u8

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

187

drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

194

drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

200

u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

201

u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

203

u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

204

int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

205

u8 dsc_bpc[3]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

208

drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

215

drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

223

drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

238

drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

245

drm_dp_sink_supports_fec(const u8 fec_capable)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

251

drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

257

drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

263

drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

271

drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

289

drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

321

u8 request;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

322

u8 reply;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

36

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

38

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

40

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

416

u8 crc_count;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

42

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

44

u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

47

int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

49

int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

53

const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

56

const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

58

const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

61

bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

610

unsigned int offset, u8 *valuep)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

626

unsigned int offset, u8 value)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

63

bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

640

unsigned int offset, u8 *valuep)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

65

bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

654

unsigned int offset, u8 value)

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

66

bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

660

u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

663

u8 status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

667

u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

67

bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

672

int vcpid, u8 start_time_slot, u8 time_slot_count);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

677

u8 real_edid_checksum);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

680

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

681

u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

682

bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

683

const u8 port_cap[4], u8 type);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

684

bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

685

const u8 port_cap[4],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

687

int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

688

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

689

int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

69

u8 drm_dp_link_rate_to_bw_code(int link_rate);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

690

const u8 port_cap[4],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

692

int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

693

const u8 port_cap[4],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

695

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

696

const u8 port_cap[4],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

698

bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

699

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

70

int drm_dp_bw_code_to_link_rate(u8 link_bw);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

700

bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

701

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

703

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

704

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

707

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

708

const u8 port_cap[4],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

712

drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

713

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

716

const u8 *dpcd,

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

717

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

721

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

726

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

727

u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

729

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

731

u8 caps[DP_LTTPR_PHY_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

732

int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

733

int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

736

int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

737

bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

738

bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

750

u8 oui[3];

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

751

u8 device_id[6];

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

752

u8 hw_rev;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

753

u8 sw_major_rev;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

754

u8 sw_minor_rev;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

852

u8 pwmgen_bit_count;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

853

u8 pwm_freq_pre_divider;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

865

u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

866

u32 *current_level, u8 *current_mode, bool need_luminance);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

938

u8 num_lanes;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

939

u8 phy_pattern;

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

940

u8 hbr2_reset[2];

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

941

u8 custom80[10];

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

948

struct drm_dp_phy_test_params *data, u8 dp_rev);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

949

int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

950

const u8 port_cap[4]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

954

u8 frl_mode);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

956

u8 frl_type);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

961

int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

964

bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

965

int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

966

int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

967

int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

969

int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

970

int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

971

bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

972

const u8 port_cap[4], u8 color_spc);

sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

973

int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

115

u8 port_num;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

119

u8 pdt;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

121

u8 dpcd_rev;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

122

u8 num_sdp_streams;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

123

u8 num_sdp_stream_sinks;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

159

u8 lct;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

160

u8 lcr;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

161

u8 rad[8];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

164

u8 msg_len;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

171

u8 chunk[48];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

172

u8 msg[256];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

173

u8 curchunk_len;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

174

u8 curchunk_idx; /* chunk we are parsing now */

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

175

u8 curchunk_hdrlen;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

176

u8 curlen; /* total length of the msg */

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

232

u8 rad[8];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

233

u8 lct;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

260

u8 reason;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

261

u8 nak_data;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

266

u8 nports;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

269

u8 peer_device_type;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

270

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

274

u8 dpcd_revision;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

276

u8 num_sdp_streams;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

277

u8 num_sdp_stream_sinks;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

282

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

283

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

284

u8 bytes[255];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

288

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

292

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

293

u8 reason;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

294

u8 bytes_written_before_failure;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

298

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

299

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

300

u8 bytes[255];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

304

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

305

u8 nak_reason;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

306

u8 i2c_nak_transaction;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

310

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

315

u8 stream_id;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

339

u8 state;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

344

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

345

u8 number_sdp_streams;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

346

u8 vcpi;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

348

u8 sdp_stream_sink[DRM_DP_MAX_SDP_STREAMS];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

352

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

353

u8 vcpi;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

359

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

364

u8 peer_device_type;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

368

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

370

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

374

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

376

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

377

u8 *bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

382

u8 num_transactions;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

383

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

385

u8 i2c_dev_id;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

386

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

387

u8 *bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

388

u8 no_stop_bit;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

389

u8 i2c_transaction_delay;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

391

u8 read_i2c_device_id;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

392

u8 num_bytes_read;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

396

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

397

u8 write_i2c_device_id;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

398

u8 num_bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

399

u8 *bytes;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

403

u8 stream_id;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

404

u8 client_id[7]; /* 56-bit nonce */

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

405

u8 stream_event;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

407

u8 stream_behavior;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

408

u8 valid_stream_behavior;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

413

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

417

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

425

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

429

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

430

u8 vcpi;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

434

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

440

u8 port_number;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

445

u8 req_type;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

465

u8 reply_type;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

466

u8 req_type;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

499

u8 msg[256];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

500

u8 chunk[48];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

501

u8 cur_offset;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

502

u8 cur_len;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

566

u8 vcpi;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

619

u8 total_avail_slots;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

621

u8 start_slot;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

721

u8 payload_count;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

728

u8 next_start_slot;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

738

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

742

u8 sink_count;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

855

enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

859

const u8 *esi,

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

860

u8 *ack,

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

211

u8 stream_id, int bw)

sys/dev/pci/drm/include/drm/display/drm_dp_tunnel.h

85

u8 stream_id, int bw);

sys/dev/pci/drm/include/drm/display/drm_dsc.h

116

u8 rc_tgt_offset_high;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

121

u8 rc_tgt_offset_low;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

131

u8 rc_edge_factor;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

136

u8 rc_quant_incr_limit1;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

141

u8 rc_quant_incr_limit0;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

165

u8 first_line_bpg_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

187

u8 flatness_min_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

191

u8 flatness_max_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

195

u8 initial_scale_value;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

227

u8 mux_word_size;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

241

u8 dsc_version_minor;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

245

u8 dsc_version_major;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

258

u8 second_line_bpg_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

289

u8 dsc_version;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

295

u8 pps_identifier;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

300

u8 pps_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

313

u8 pps_3;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

327

u8 pps_4;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

333

u8 bits_per_pixel_low;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

369

u8 initial_xmit_delay_high;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

374

u8 initial_xmit_delay_low;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

388

u8 pps20_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

395

u8 initial_scale_value;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

408

u8 scale_decrement_interval_high;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

413

u8 scale_decrement_interval_low;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

418

u8 pps26_reserved;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

425

u8 first_line_bpg_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

454

u8 flatness_min_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

461

u8 flatness_max_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

473

u8 rc_edge_factor;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

479

u8 rc_quant_incr_limit0;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

485

u8 rc_quant_incr_limit1;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

493

u8 rc_tgt_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

499

u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];

sys/dev/pci/drm/include/drm/display/drm_dsc.h

514

u8 native_422_420;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

522

u8 second_line_bpg_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

54

u8 range_min_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

58

u8 range_max_qp;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

63

u8 range_bpg_offset;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

77

u8 line_buf_depth;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

81

u8 bits_per_component;

sys/dev/pci/drm/include/drm/display/drm_dsc.h

91

u8 slice_count;

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

23

int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

30

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

127

u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

128

u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

129

u8 reserved[2];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

130

u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

134

u8 stream_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

135

u8 stream_type;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

144

u8 version;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

147

u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

152

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

153

u8 r_tx[HDCP_2_2_RTX_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

158

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

160

u8 r_rx[HDCP_2_2_RRX_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

161

u8 rx_caps[HDCP_2_2_RXCAPS_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

165

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

166

u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

170

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

171

u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

175

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

176

u8 h_prime[HDCP_2_2_H_PRIME_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

180

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

181

u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

185

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

186

u8 r_n[HDCP_2_2_RN_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

190

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

191

u8 l_prime[HDCP_2_2_L_PRIME_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

195

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

196

u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

197

u8 riv[HDCP_2_2_RIV_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

201

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

202

u8 rx_info[HDCP_2_2_RXINFO_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

203

u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

204

u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

205

u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

209

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

210

u8 v[HDCP_2_2_V_PRIME_HALF_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

214

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

215

u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

221

u8 msg_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

222

u8 m_prime[HDCP_2_2_MPRIME_LEN];

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

261

u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

267

void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

288

u8 srm_id;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

289

u8 reserved;

sys/dev/pci/drm/include/drm/display/drm_hdcp.h

291

u8 srm_gen_no;

sys/dev/pci/drm/include/drm/display/drm_hdcp_helper.h

17

int drm_hdcp_check_ksvs_revoked(struct drm_device *dev, u8 *ksvs, u32 ksv_count);

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

33

int (*log_addr)(struct drm_connector *connector, u8 logical_addr);

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

38

int (*transmit)(struct drm_connector *connector, u8 attempts,

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

45

u8 available_las,

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

52

u8 status,

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

53

u8 arb_lost_cnt, u8 nack_cnt,

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

54

u8 low_drive_cnt, u8 error_cnt);

sys/dev/pci/drm/include/drm/display/drm_hdmi_cec_helper.h

57

u8 status);

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

34

ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

36

ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

51

static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

52

u8 *value)

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

69

static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,

sys/dev/pci/drm/include/drm/display/drm_scdc_helper.h

70

u8 value)

sys/dev/pci/drm/include/drm/drm_bridge.h

1139

u8 hdmi_cec_available_las;

sys/dev/pci/drm/include/drm/drm_bridge.h

692

const u8 *buffer, size_t len);

sys/dev/pci/drm/include/drm/drm_bridge.h

794

int (*hdmi_cec_log_addr)(struct drm_bridge *bridge, u8 logical_addr);

sys/dev/pci/drm/include/drm/drm_bridge.h

808

int (*hdmi_cec_transmit)(struct drm_bridge *bridge, u8 attempts,

sys/dev/pci/drm/include/drm/drm_connector.h

1127

u8 max_requested_bpc;

sys/dev/pci/drm/include/drm/drm_connector.h

1133

u8 max_bpc;

sys/dev/pci/drm/include/drm/drm_connector.h

1280

const u8 *buffer, size_t len);

sys/dev/pci/drm/include/drm/drm_connector.h

2232

u8 real_edid_checksum;

sys/dev/pci/drm/include/drm/drm_connector.h

2512

u8 group_data[8];

sys/dev/pci/drm/include/drm/drm_connector.h

280

u8 bpc_supported;

sys/dev/pci/drm/include/drm/drm_connector.h

283

u8 max_slices;

sys/dev/pci/drm/include/drm/drm_connector.h

289

u8 max_lanes;

sys/dev/pci/drm/include/drm/drm_connector.h

292

u8 max_frl_rate_per_lane;

sys/dev/pci/drm/include/drm/drm_connector.h

295

u8 total_chunk_kbytes;

sys/dev/pci/drm/include/drm/drm_connector.h

325

u8 y420_dc_modes;

sys/dev/pci/drm/include/drm/drm_connector.h

328

u8 max_frl_rate_per_lane;

sys/dev/pci/drm/include/drm/drm_connector.h

331

u8 max_lanes;

sys/dev/pci/drm/include/drm/drm_connector.h

784

u8 edid_hdmi_rgb444_dc_modes;

sys/dev/pci/drm/include/drm/drm_connector.h

790

u8 edid_hdmi_ycbcr444_dc_modes;

sys/dev/pci/drm/include/drm/drm_connector.h

795

u8 cea_rev;

sys/dev/pci/drm/include/drm/drm_connector.h

827

u8 mso_stream_count;

sys/dev/pci/drm/include/drm/drm_connector.h

832

u8 mso_pixel_overlap;

sys/dev/pci/drm/include/drm/drm_connector.h

843

u8 *vics;

sys/dev/pci/drm/include/drm/drm_edid.h

120

u8 min_vfreq;

sys/dev/pci/drm/include/drm/drm_edid.h

121

u8 max_vfreq;

sys/dev/pci/drm/include/drm/drm_edid.h

122

u8 min_hfreq_khz;

sys/dev/pci/drm/include/drm/drm_edid.h

123

u8 max_hfreq_khz;

sys/dev/pci/drm/include/drm/drm_edid.h

124

u8 pixel_clock_mhz; /* need to multiply by 10 */

sys/dev/pci/drm/include/drm/drm_edid.h

125

u8 flags;

sys/dev/pci/drm/include/drm/drm_edid.h

128

u8 reserved;

sys/dev/pci/drm/include/drm/drm_edid.h

129

u8 hfreq_start_khz; /* need to multiply by 2 */

sys/dev/pci/drm/include/drm/drm_edid.h

130

u8 c; /* need to divide by 2 */

sys/dev/pci/drm/include/drm/drm_edid.h

132

u8 k;

sys/dev/pci/drm/include/drm/drm_edid.h

133

u8 j; /* need to divide by 2 */

sys/dev/pci/drm/include/drm/drm_edid.h

136

u8 version;

sys/dev/pci/drm/include/drm/drm_edid.h

137

u8 data1; /* high 6 bits: extra clock resolution */

sys/dev/pci/drm/include/drm/drm_edid.h

138

u8 data2; /* plus low 2 of above: max hactive */

sys/dev/pci/drm/include/drm/drm_edid.h

139

u8 supported_aspects;

sys/dev/pci/drm/include/drm/drm_edid.h

140

u8 flags; /* preferred aspect and blanking support */

sys/dev/pci/drm/include/drm/drm_edid.h

141

u8 supported_scalings;

sys/dev/pci/drm/include/drm/drm_edid.h

142

u8 preferred_refresh;

sys/dev/pci/drm/include/drm/drm_edid.h

148

u8 white_yx_lo; /* Lower 2 bits each */

sys/dev/pci/drm/include/drm/drm_edid.h

149

u8 white_x_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

150

u8 white_y_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

151

u8 gamma; /* need to divide by 100 then add 1 */

sys/dev/pci/drm/include/drm/drm_edid.h

155

u8 windex1;

sys/dev/pci/drm/include/drm/drm_edid.h

156

u8 wpindex1[3];

sys/dev/pci/drm/include/drm/drm_edid.h

157

u8 windex2;

sys/dev/pci/drm/include/drm/drm_edid.h

158

u8 wpindex2[3];

sys/dev/pci/drm/include/drm/drm_edid.h

162

u8 code[3];

sys/dev/pci/drm/include/drm/drm_edid.h

166

u8 pad1;

sys/dev/pci/drm/include/drm/drm_edid.h

167

u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name

sys/dev/pci/drm/include/drm/drm_edid.h

170

u8 pad2;

sys/dev/pci/drm/include/drm/drm_edid.h

287

u8 week_of_manufacture;

sys/dev/pci/drm/include/drm/drm_edid.h

288

u8 year_of_manufacture;

sys/dev/pci/drm/include/drm/drm_edid.h

292

u8 header[8];

sys/dev/pci/drm/include/drm/drm_edid.h

297

u8 mfg_id[2];

sys/dev/pci/drm/include/drm/drm_edid.h

298

u8 prod_code[2];

sys/dev/pci/drm/include/drm/drm_edid.h

300

u8 mfg_week;

sys/dev/pci/drm/include/drm/drm_edid.h

301

u8 mfg_year;

sys/dev/pci/drm/include/drm/drm_edid.h

305

u8 version;

sys/dev/pci/drm/include/drm/drm_edid.h

306

u8 revision;

sys/dev/pci/drm/include/drm/drm_edid.h

308

u8 input;

sys/dev/pci/drm/include/drm/drm_edid.h

309

u8 width_cm;

sys/dev/pci/drm/include/drm/drm_edid.h

310

u8 height_cm;

sys/dev/pci/drm/include/drm/drm_edid.h

311

u8 gamma;

sys/dev/pci/drm/include/drm/drm_edid.h

312

u8 features;

sys/dev/pci/drm/include/drm/drm_edid.h

314

u8 red_green_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

315

u8 blue_white_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

316

u8 red_x;

sys/dev/pci/drm/include/drm/drm_edid.h

317

u8 red_y;

sys/dev/pci/drm/include/drm/drm_edid.h

318

u8 green_x;

sys/dev/pci/drm/include/drm/drm_edid.h

319

u8 green_y;

sys/dev/pci/drm/include/drm/drm_edid.h

320

u8 blue_x;

sys/dev/pci/drm/include/drm/drm_edid.h

321

u8 blue_y;

sys/dev/pci/drm/include/drm/drm_edid.h

322

u8 white_x;

sys/dev/pci/drm/include/drm/drm_edid.h

323

u8 white_y;

sys/dev/pci/drm/include/drm/drm_edid.h

331

u8 extensions;

sys/dev/pci/drm/include/drm/drm_edid.h

333

u8 checksum;

sys/dev/pci/drm/include/drm/drm_edid.h

353

u8 format;

sys/dev/pci/drm/include/drm/drm_edid.h

354

u8 channels; /* max number of channels - 1 */

sys/dev/pci/drm/include/drm/drm_edid.h

355

u8 freq;

sys/dev/pci/drm/include/drm/drm_edid.h

356

u8 byte2; /* meaning depends on format */

sys/dev/pci/drm/include/drm/drm_edid.h

360

int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);

sys/dev/pci/drm/include/drm/drm_edid.h

447

u8 drm_match_cea_mode(const struct drm_display_mode *to_match);

sys/dev/pci/drm/include/drm/drm_edid.h

464

u8 video_code);

sys/dev/pci/drm/include/drm/drm_edid.h

476

int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),

sys/dev/pci/drm/include/drm/drm_edid.h

50

u8 t1;

sys/dev/pci/drm/include/drm/drm_edid.h

51

u8 t2;

sys/dev/pci/drm/include/drm/drm_edid.h

52

u8 mfg_rsvd;

sys/dev/pci/drm/include/drm/drm_edid.h

64

u8 hsize; /* need to multiply by 8 then add 248 */

sys/dev/pci/drm/include/drm/drm_edid.h

65

u8 vfreq_aspect;

sys/dev/pci/drm/include/drm/drm_edid.h

76

u8 hactive_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

77

u8 hblank_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

78

u8 hactive_hblank_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

79

u8 vactive_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

80

u8 vblank_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

81

u8 vactive_vblank_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

82

u8 hsync_offset_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

83

u8 hsync_pulse_width_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

84

u8 vsync_offset_pulse_width_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

85

u8 hsync_vsync_offset_pulse_width_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

86

u8 width_mm_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

87

u8 height_mm_lo;

sys/dev/pci/drm/include/drm/drm_edid.h

88

u8 width_height_mm_hi;

sys/dev/pci/drm/include/drm/drm_edid.h

89

u8 hborder;

sys/dev/pci/drm/include/drm/drm_edid.h

90

u8 vborder;

sys/dev/pci/drm/include/drm/drm_edid.h

91

u8 misc;

sys/dev/pci/drm/include/drm/drm_edid.h

96

u8 str[13];

sys/dev/pci/drm/include/drm/drm_eld.h

106

static inline int drm_eld_sad_count(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

119

static inline int drm_eld_calc_baseline_block_size(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

135

static inline int drm_eld_size(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

147

static inline u8 drm_eld_get_spk_alloc(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

159

static inline u8 drm_eld_get_conn_type(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

75

static inline int drm_eld_mnl(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_eld.h

80

int drm_eld_sad_get(const u8 *eld, int sad_index, struct cea_sad *cta_sad);

sys/dev/pci/drm/include/drm/drm_eld.h

81

int drm_eld_sad_set(u8 *eld, int sad_index, const struct cea_sad *cta_sad);

sys/dev/pci/drm/include/drm/drm_eld.h

87

static inline const u8 *drm_eld_sad(const u8 *eld)

sys/dev/pci/drm/include/drm/drm_fourcc.h

112

u8 char_per_block[DRM_FORMAT_MAX_PLANES];

sys/dev/pci/drm/include/drm/drm_fourcc.h

121

u8 block_w[DRM_FORMAT_MAX_PLANES];

sys/dev/pci/drm/include/drm/drm_fourcc.h

129

u8 block_h[DRM_FORMAT_MAX_PLANES];

sys/dev/pci/drm/include/drm/drm_fourcc.h

132

u8 hsub;

sys/dev/pci/drm/include/drm/drm_fourcc.h

134

u8 vsub;

sys/dev/pci/drm/include/drm/drm_fourcc.h

72

u8 depth;

sys/dev/pci/drm/include/drm/drm_fourcc.h

75

u8 num_planes;

sys/dev/pci/drm/include/drm/drm_fourcc.h

86

u8 cpp[DRM_FORMAT_MAX_PLANES];

sys/dev/pci/drm/include/drm/drm_mipi_dsi.h

78

ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *, u8, void *, size_t);

sys/dev/pci/drm/include/drm/drm_mipi_dsi.h

79

ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *, u8, const void *, size_t);

sys/dev/pci/drm/include/drm/drm_mipi_dsi.h

82

bool mipi_dsi_packet_format_is_long(u8);

sys/dev/pci/drm/include/drm/drm_modes.h

378

u8 type;

sys/dev/pci/drm/include/drm/drm_panic.h

183

size_t drm_panic_qr_max_data_size(u8 version, size_t url_len);

sys/dev/pci/drm/include/drm/drm_panic.h

185

u8 drm_panic_qr_generate(const char *url, u8 *data, size_t data_len, size_t data_size,

sys/dev/pci/drm/include/drm/drm_panic.h

186

u8 *tmp, size_t tmp_size);

sys/dev/pci/drm/include/drm/drm_print.h

204

const u8 *buf, size_t len);

sys/dev/pci/drm/include/drm/intel/i915_pxp_tee_interface.h

35

ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,

sys/dev/pci/drm/include/drm/intel/intel_lpe_audio.h

35

u8 eld[HDMI_MAX_ELD_BYTES];

sys/dev/pci/drm/include/linux/bits.h

32

((u8)(BIT(__n) + \

sys/dev/pci/drm/include/linux/bits.h

76

((u8)(GENMASK(__high, __low) + \

sys/dev/pci/drm/include/linux/firmware.h

18

const u8 *data;

sys/dev/pci/drm/include/linux/hdmi.h

353

struct dp_sdp *sdp, u8 dp_version);

sys/dev/pci/drm/include/linux/hdmi.h

373

u8 vic;

sys/dev/pci/drm/include/linux/io.h

25

static inline u8

sys/dev/pci/drm/include/linux/io.h

37

iowrite8(u8 val, volatile void __iomem *addr)

sys/dev/pci/drm/include/linux/pci.h

160

pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)

sys/dev/pci/drm/include/linux/pci.h

189

pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)

sys/dev/pci/drm/include/linux/pci.h

215

int reg, u8 *val)

sys/dev/pci/drm/include/linux/pci.h

228

int reg, u8 val)

sys/dev/pci/drm/radeon/atombios_crtc.c

672

u8 frev, crev;

sys/dev/pci/drm/radeon/atombios_crtc.c

769

u8 frev, crev;

sys/dev/pci/drm/radeon/atombios_crtc.c

831

u8 frev, crev;

sys/dev/pci/drm/radeon/atombios_dp.c

164

u8 tx_buf[20];

sys/dev/pci/drm/radeon/atombios_dp.c

166

u8 ack, delay = 0;

sys/dev/pci/drm/radeon/atombios_dp.c

252

static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/pci/drm/radeon/atombios_dp.c

254

u8 train_set[4])

sys/dev/pci/drm/radeon/atombios_dp.c

256

u8 v = 0;

sys/dev/pci/drm/radeon/atombios_dp.c

257

u8 p = 0;

sys/dev/pci/drm/radeon/atombios_dp.c

261

u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);

sys/dev/pci/drm/radeon/atombios_dp.c

262

u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

sys/dev/pci/drm/radeon/atombios_dp.c

302

const u8 dpcd[DP_DPCD_SIZE],

sys/dev/pci/drm/radeon/atombios_dp.c

338

static u8 radeon_dp_encoder_service(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/atombios_dp.c

340

u8 ucconfig, u8 lane_num)

sys/dev/pci/drm/radeon/atombios_dp.c

356

u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)

sys/dev/pci/drm/radeon/atombios_dp.c

368

u8 buf[3];

sys/dev/pci/drm/radeon/atombios_dp.c

385

u8 msg[DP_DPCD_SIZE];

sys/dev/pci/drm/radeon/atombios_dp.c

413

u8 tmp;

sys/dev/pci/drm/radeon/atombios_dp.c

501

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/radeon/atombios_dp.c

513

u8 power_state)

sys/dev/pci/drm/radeon/atombios_dp.c

540

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/radeon/atombios_dp.c

541

u8 train_set[4];

sys/dev/pci/drm/radeon/atombios_dp.c

542

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/pci/drm/radeon/atombios_dp.c

543

u8 tries;

sys/dev/pci/drm/radeon/atombios_dp.c

57

void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)

sys/dev/pci/drm/radeon/atombios_dp.c

599

u8 tmp;

sys/dev/pci/drm/radeon/atombios_dp.c

62

u8 align_num_bytes = ALIGN(num_bytes, 4);

sys/dev/pci/drm/radeon/atombios_dp.c

664

u8 voltage;

sys/dev/pci/drm/radeon/atombios_dp.c

790

u8 tmp, frev, crev;

sys/dev/pci/drm/radeon/atombios_dp.c

86

u8 *send, int send_bytes,

sys/dev/pci/drm/radeon/atombios_dp.c

87

u8 *recv, int recv_size,

sys/dev/pci/drm/radeon/atombios_dp.c

88

u8 delay, u8 *ack)

sys/dev/pci/drm/radeon/atombios_encoders.c

1434

u8 frev, crev;

sys/dev/pci/drm/radeon/atombios_encoders.c

148

static u8 radeon_atom_bl_level(struct backlight_device *bd)

sys/dev/pci/drm/radeon/atombios_encoders.c

150

u8 level;

sys/dev/pci/drm/radeon/atombios_encoders.c

452

static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)

sys/dev/pci/drm/radeon/atombios_encoders.c

47

static u8

sys/dev/pci/drm/radeon/atombios_encoders.c

50

u8 backlight_level;

sys/dev/pci/drm/radeon/atombios_encoders.c

66

u8 backlight_level)

sys/dev/pci/drm/radeon/atombios_encoders.c

85

u8

sys/dev/pci/drm/radeon/atombios_encoders.c

98

atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)

sys/dev/pci/drm/radeon/atombios_i2c.c

106

u8 flags;

sys/dev/pci/drm/radeon/atombios_i2c.c

37

u8 slave_addr, u8 flags,

sys/dev/pci/drm/radeon/atombios_i2c.c

38

u8 *buf, int num)

sys/dev/pci/drm/radeon/btc_dpm.c

1656

(u8 *)table,

sys/dev/pci/drm/radeon/btc_dpm.c

1873

u8 i, j;

sys/dev/pci/drm/radeon/btc_dpm.c

1890

u8 i, j, k;

sys/dev/pci/drm/radeon/btc_dpm.c

1963

u8 i, j;

sys/dev/pci/drm/radeon/btc_dpm.c

1993

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

1300

(u8 *)&low_sclk_interrupt_t,

sys/dev/pci/drm/radeon/ci_dpm.c

149

extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

2408

static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ci_dpm.c

241

static u8 ci_convert_to_vid(u16 vddc)

sys/dev/pci/drm/radeon/ci_dpm.c

2425

return (u8)i;

sys/dev/pci/drm/radeon/ci_dpm.c

249

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/pci/drm/radeon/ci_dpm.c

2497

arb_regs->McArbBurstTime = (u8)burst_time;

sys/dev/pci/drm/radeon/ci_dpm.c

250

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/pci/drm/radeon/ci_dpm.c

251

u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;

sys/dev/pci/drm/radeon/ci_dpm.c

2525

(u8 *)&arb_regs,

sys/dev/pci/drm/radeon/ci_dpm.c

2591

(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;

sys/dev/pci/drm/radeon/ci_dpm.c

2599

pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;

sys/dev/pci/drm/radeon/ci_dpm.c

2629

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

2637

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

2670

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

2687

table->AcpLevelCount = (u8)

sys/dev/pci/drm/radeon/ci_dpm.c

2703

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

2735

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

278

u8 *vid = pi->smc_powertune_table.VddCVid;

sys/dev/pci/drm/radeon/ci_dpm.c

2974

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

3102

state->VddcOffsetVid = (u8)

sys/dev/pci/drm/radeon/ci_dpm.c

3166

sclk->SclkDid = (u8)dividers.post_divider;

sys/dev/pci/drm/radeon/ci_dpm.c

3261

pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/pci/drm/radeon/ci_dpm.c

3266

(u8 *)levels, level_array_size,

sys/dev/pci/drm/radeon/ci_dpm.c

3316

pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;

sys/dev/pci/drm/radeon/ci_dpm.c

3324

(u8 *)levels, level_array_size,

sys/dev/pci/drm/radeon/ci_dpm.c

356

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/pci/drm/radeon/ci_dpm.c

357

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/pci/drm/radeon/ci_dpm.c

3644

(u8 *)&table->SystemFlags,

sys/dev/pci/drm/radeon/ci_dpm.c

379

pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/pci/drm/radeon/ci_dpm.c

380

pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;

sys/dev/pci/drm/radeon/ci_dpm.c

4049

static u8 ci_get_vce_boot_level(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/ci_dpm.c

4051

u8 i;

sys/dev/pci/drm/radeon/ci_dpm.c

416

dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;

sys/dev/pci/drm/radeon/ci_dpm.c

418

(u8)(pi->thermal_temp_setting.temperature_high / 1000);

sys/dev/pci/drm/radeon/ci_dpm.c

4290

u8 i, j, k;

sys/dev/pci/drm/radeon/ci_dpm.c

4432

u8 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

4460

u8 i, j;

sys/dev/pci/drm/radeon/ci_dpm.c

4487

u8 i, k;

sys/dev/pci/drm/radeon/ci_dpm.c

4579

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/pci/drm/radeon/ci_dpm.c

4649

mc_reg_table->last = (u8)i;

sys/dev/pci/drm/radeon/ci_dpm.c

4714

(u8 *)&pi->smc_mc_reg_table,

sys/dev/pci/drm/radeon/ci_dpm.c

4733

(u8 *)&pi->smc_mc_reg_table.data[0],

sys/dev/pci/drm/radeon/ci_dpm.c

4847

u8 request;

sys/dev/pci/drm/radeon/ci_dpm.c

487

(u8 *)&pi->smc_powertune_table,

sys/dev/pci/drm/radeon/ci_dpm.c

5398

u8 table_rev)

sys/dev/pci/drm/radeon/ci_dpm.c

5500

u8 frev, crev;

sys/dev/pci/drm/radeon/ci_dpm.c

5501

u8 *power_state_offset;

sys/dev/pci/drm/radeon/ci_dpm.c

5525

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/ci_dpm.c

5528

u8 *idx;

sys/dev/pci/drm/radeon/ci_dpm.c

5547

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/radeon/ci_dpm.c

5555

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/radeon/ci_dpm.c

5595

u8 frev, crev;

sys/dev/pci/drm/radeon/ci_dpm.c

5635

u8 frev, crev;

sys/dev/pci/drm/radeon/ci_dpm.c

992

(u8 *)(&fan_table),

sys/dev/pci/drm/radeon/ci_dpm.h

175

u8 svi_load_line_en;

sys/dev/pci/drm/radeon/ci_dpm.h

176

u8 svi_load_line_vddc;

sys/dev/pci/drm/radeon/ci_dpm.h

177

u8 tdc_vddc_throttle_release_limit_perc;

sys/dev/pci/drm/radeon/ci_dpm.h

178

u8 tdc_mawt;

sys/dev/pci/drm/radeon/ci_dpm.h

179

u8 tdc_waterfall_ctl;

sys/dev/pci/drm/radeon/ci_dpm.h

180

u8 dte_ambient_temp_base;

sys/dev/pci/drm/radeon/ci_dpm.h

325

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/ci_dpm.h

83

u8 last;

sys/dev/pci/drm/radeon/ci_dpm.h

84

u8 num_entries;

sys/dev/pci/drm/radeon/ci_smc.c

132

static const u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };

sys/dev/pci/drm/radeon/ci_smc.c

191

const u8 *src;

sys/dev/pci/drm/radeon/ci_smc.c

205

src = (const u8 *)

sys/dev/pci/drm/radeon/ci_smc.c

222

src = (const u8 *)rdev->smc_fw->data;

sys/dev/pci/drm/radeon/ci_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/cik.c

7545

u8 me_id, pipe_id, queue_id;

sys/dev/pci/drm/radeon/cypress_dpm.c

1030

eg_pi->mc_reg_table.last = (u8)i;

sys/dev/pci/drm/radeon/cypress_dpm.c

1076

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/pci/drm/radeon/cypress_dpm.c

1091

static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)

sys/dev/pci/drm/radeon/cypress_dpm.c

1577

u8 module_index;

sys/dev/pci/drm/radeon/cypress_dpm.c

1662

(u8 *)table, sizeof(RV770_SMC_STATETABLE),

sys/dev/pci/drm/radeon/cypress_dpm.c

1690

(u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),

sys/dev/pci/drm/radeon/cypress_dpm.c

300

u8 perf_req, bool advertise)

sys/dev/pci/drm/radeon/cypress_dpm.c

366

u8 request;

sys/dev/pci/drm/radeon/cypress_dpm.c

388

u8 request;

sys/dev/pci/drm/radeon/cypress_dpm.c

410

voltage->index = (u8)i;

sys/dev/pci/drm/radeon/cypress_dpm.c

422

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/pci/drm/radeon/cypress_dpm.c

425

u8 result = 0;

sys/dev/pci/drm/radeon/cypress_dpm.c

613

u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cypress_dpm.c

616

u8 mc_para_index;

sys/dev/pci/drm/radeon/cypress_dpm.c

625

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/pci/drm/radeon/cypress_dpm.c

632

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/pci/drm/radeon/cypress_dpm.c

641

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/pci/drm/radeon/cypress_dpm.c

648

mc_para_index = (u8)((memory_clock - 40000) / 5000);

sys/dev/pci/drm/radeon/cypress_dpm.c

681

u8 watermark_level)

sys/dev/pci/drm/radeon/cypress_dpm.c

882

return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,

sys/dev/pci/drm/radeon/cypress_dpm.c

901

(u8 *)&mc_reg_table.data[2],

sys/dev/pci/drm/radeon/cypress_dpm.c

966

mc_reg_table->last = (u8)i;

sys/dev/pci/drm/radeon/cypress_dpm.h

116

u8 watermark_level);

sys/dev/pci/drm/radeon/cypress_dpm.h

156

u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cypress_dpm.h

158

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);

sys/dev/pci/drm/radeon/cypress_dpm.h

35

u8 last;

sys/dev/pci/drm/radeon/cypress_dpm.h

36

u8 num_entries;

sys/dev/pci/drm/radeon/cypress_dpm.h

80

u8 mvdd_high_index;

sys/dev/pci/drm/radeon/cypress_dpm.h

81

u8 mvdd_low_index;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

32

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/dce3_1_afmt.c

50

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/dce3_1_afmt.c

89

u8 stereo_freqs = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

155

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/dce6_afmt.c

180

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/dce6_afmt.c

231

u8 stereo_freqs = 0;

sys/dev/pci/drm/radeon/dce6_afmt.c

261

u8 enable_mask)

sys/dev/pci/drm/radeon/dce6_afmt.h

40

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/dce6_afmt.h

42

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

122

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

140

u8 *sadb, int sad_count)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

179

u8 stereo_freqs = 0;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

41

u8 enable_mask)

sys/dev/pci/drm/radeon/evergreen_hdmi.h

51

u8 enable_mask);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

53

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

55

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/kv_dpm.c

1192

(u8 *)&pi->fps_high_t,

sys/dev/pci/drm/radeon/kv_dpm.c

1201

(u8 *)&pi->fps_low_t,

sys/dev/pci/drm/radeon/kv_dpm.c

1267

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

1279

static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)

sys/dev/pci/drm/radeon/kv_dpm.c

1281

u8 i;

sys/dev/pci/drm/radeon/kv_dpm.c

1314

(u8 *)&pi->vce_boot_level,

sys/dev/pci/drm/radeon/kv_dpm.c

1315

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

1352

(u8 *)&pi->samu_boot_level,

sys/dev/pci/drm/radeon/kv_dpm.c

1353

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

1367

static u8 kv_get_acp_boot_level(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/kv_dpm.c

1369

u8 i;

sys/dev/pci/drm/radeon/kv_dpm.c

1387

u8 acp_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.c

1416

(u8 *)&pi->acp_boot_level,

sys/dev/pci/drm/radeon/kv_dpm.c

1417

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

1593

u8 clk_bypass_cntl;

sys/dev/pci/drm/radeon/kv_dpm.c

1604

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

1876

static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/kv_dpm.c

1897

return (u8)i;

sys/dev/pci/drm/radeon/kv_dpm.c

2291

u8 frev, crev;

sys/dev/pci/drm/radeon/kv_dpm.c

2382

u8 table_rev)

sys/dev/pci/drm/radeon/kv_dpm.c

2441

u8 frev, crev;

sys/dev/pci/drm/radeon/kv_dpm.c

2442

u8 *power_state_offset;

sys/dev/pci/drm/radeon/kv_dpm.c

2465

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/kv_dpm.c

2467

u8 *idx;

sys/dev/pci/drm/radeon/kv_dpm.c

2481

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/radeon/kv_dpm.c

2489

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/radeon/kv_dpm.c

330

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

346

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

360

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

387

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

461

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/pci/drm/radeon/kv_dpm.c

550

(u8 *)&low_sclk_interrupt_t,

sys/dev/pci/drm/radeon/kv_dpm.c

569

pi->graphics_boot_level = (u8)i;

sys/dev/pci/drm/radeon/kv_dpm.c

583

pi->graphics_boot_level = (u8)i;

sys/dev/pci/drm/radeon/kv_dpm.c

600

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

613

(u8 *)&pi->graphics_level,

sys/dev/pci/drm/radeon/kv_dpm.c

624

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

682

(u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);

sys/dev/pci/drm/radeon/kv_dpm.c

684

(u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);

sys/dev/pci/drm/radeon/kv_dpm.c

690

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

696

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

704

(u8 *)&pi->uvd_level_count,

sys/dev/pci/drm/radeon/kv_dpm.c

705

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

715

sizeof(u8), pi->sram_end);

sys/dev/pci/drm/radeon/kv_dpm.c

722

(u8 *)&pi->uvd_level,

sys/dev/pci/drm/radeon/kv_dpm.c

752

(u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);

sys/dev/pci/drm/radeon/kv_dpm.c

758

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

766

(u8 *)&pi->vce_level_count,

sys/dev/pci/drm/radeon/kv_dpm.c

767

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

777

(u8 *)&pi->vce_interval,

sys/dev/pci/drm/radeon/kv_dpm.c

778

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

786

(u8 *)&pi->vce_level,

sys/dev/pci/drm/radeon/kv_dpm.c

815

(u8)kv_get_clk_bypass(rdev, table->entries[i].clk);

sys/dev/pci/drm/radeon/kv_dpm.c

821

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

829

(u8 *)&pi->samu_level_count,

sys/dev/pci/drm/radeon/kv_dpm.c

830

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

840

(u8 *)&pi->samu_interval,

sys/dev/pci/drm/radeon/kv_dpm.c

841

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

849

(u8 *)&pi->samu_level,

sys/dev/pci/drm/radeon/kv_dpm.c

880

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/pci/drm/radeon/kv_dpm.c

888

(u8 *)&pi->acp_level_count,

sys/dev/pci/drm/radeon/kv_dpm.c

889

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

899

(u8 *)&pi->acp_interval,

sys/dev/pci/drm/radeon/kv_dpm.c

900

sizeof(u8),

sys/dev/pci/drm/radeon/kv_dpm.c

908

(u8 *)&pi->acp_level,

sys/dev/pci/drm/radeon/kv_dpm.h

100

u8 htc_hyst_lmt;

sys/dev/pci/drm/radeon/kv_dpm.h

125

u8 graphics_dpm_level_count;

sys/dev/pci/drm/radeon/kv_dpm.h

126

u8 uvd_level_count;

sys/dev/pci/drm/radeon/kv_dpm.h

127

u8 vce_level_count;

sys/dev/pci/drm/radeon/kv_dpm.h

128

u8 acp_level_count;

sys/dev/pci/drm/radeon/kv_dpm.h

129

u8 samu_level_count;

sys/dev/pci/drm/radeon/kv_dpm.h

137

u8 uvd_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.h

138

u8 vce_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.h

139

u8 acp_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.h

140

u8 samu_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.h

141

u8 uvd_interval;

sys/dev/pci/drm/radeon/kv_dpm.h

142

u8 vce_interval;

sys/dev/pci/drm/radeon/kv_dpm.h

143

u8 acp_interval;

sys/dev/pci/drm/radeon/kv_dpm.h

144

u8 samu_interval;

sys/dev/pci/drm/radeon/kv_dpm.h

145

u8 graphics_boot_level;

sys/dev/pci/drm/radeon/kv_dpm.h

146

u8 graphics_interval;

sys/dev/pci/drm/radeon/kv_dpm.h

147

u8 graphics_therm_throttle_enable;

sys/dev/pci/drm/radeon/kv_dpm.h

148

u8 graphics_voltage_change_enable;

sys/dev/pci/drm/radeon/kv_dpm.h

149

u8 graphics_clk_slow_enable;

sys/dev/pci/drm/radeon/kv_dpm.h

150

u8 graphics_clk_slow_divider;

sys/dev/pci/drm/radeon/kv_dpm.h

151

u8 fps_low_t;

sys/dev/pci/drm/radeon/kv_dpm.h

198

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/kv_dpm.h

72

u8 vddc_index;

sys/dev/pci/drm/radeon/kv_dpm.h

73

u8 ds_divider_index;

sys/dev/pci/drm/radeon/kv_dpm.h

74

u8 ss_divider_index;

sys/dev/pci/drm/radeon/kv_dpm.h

75

u8 allow_gnb_slow;

sys/dev/pci/drm/radeon/kv_dpm.h

76

u8 force_nbp_state;

sys/dev/pci/drm/radeon/kv_dpm.h

77

u8 display_wm;

sys/dev/pci/drm/radeon/kv_dpm.h

78

u8 vce_wm;

sys/dev/pci/drm/radeon/kv_dpm.h

85

u8 dpm0_pg_nb_ps_lo;

sys/dev/pci/drm/radeon/kv_dpm.h

86

u8 dpm0_pg_nb_ps_hi;

sys/dev/pci/drm/radeon/kv_dpm.h

87

u8 dpmx_nb_ps_lo;

sys/dev/pci/drm/radeon/kv_dpm.h

88

u8 dpmx_nb_ps_hi;

sys/dev/pci/drm/radeon/kv_dpm.h

99

u8 htc_tmp_lmt;

sys/dev/pci/drm/radeon/kv_smc.c

119

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/ni_dpm.c

1308

voltage->index = (u8)i;

sys/dev/pci/drm/radeon/ni_dpm.c

1356

u16 value, u8 index,

sys/dev/pci/drm/radeon/ni_dpm.c

1495

(u8 *)(&smc_table->dpm2Params.TDPLimit),

sys/dev/pci/drm/radeon/ni_dpm.c

1621

(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);

sys/dev/pci/drm/radeon/ni_dpm.c

1654

(u8 *)&arb_regs,

sys/dev/pci/drm/radeon/ni_dpm.c

1994

return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,

sys/dev/pci/drm/radeon/ni_dpm.c

2152

ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,

sys/dev/pci/drm/radeon/ni_dpm.c

2469

u8 max_ps_percent;

sys/dev/pci/drm/radeon/ni_dpm.c

2528

(u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/pci/drm/radeon/ni_dpm.c

2650

(u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/pci/drm/radeon/ni_dpm.c

2706

ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);

sys/dev/pci/drm/radeon/ni_dpm.c

2718

u8 i, j, k;

sys/dev/pci/drm/radeon/ni_dpm.c

2825

u8 i, j;

sys/dev/pci/drm/radeon/ni_dpm.c

2851

u8 i, j;

sys/dev/pci/drm/radeon/ni_dpm.c

2880

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/pci/drm/radeon/ni_dpm.c

2942

mc_reg_table->last = (u8)i;

sys/dev/pci/drm/radeon/ni_dpm.c

3021

(u8 *)mc_reg_table,

sys/dev/pci/drm/radeon/ni_dpm.c

3044

(u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/pci/drm/radeon/ni_dpm.c

3194

ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,

sys/dev/pci/drm/radeon/ni_dpm.c

3419

u8 perf_req, bool advertise)

sys/dev/pci/drm/radeon/ni_dpm.c

3897

u8 table_rev)

sys/dev/pci/drm/radeon/ni_dpm.c

3995

u8 frev, crev;

sys/dev/pci/drm/radeon/ni_dpm.c

4020

u8 *idx;

sys/dev/pci/drm/radeon/ni_dpm.c

4030

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/ni_dpm.h

157

u8 mc_read_weight;

sys/dev/pci/drm/radeon/ni_dpm.h

158

u8 mc_write_weight;

sys/dev/pci/drm/radeon/ni_dpm.h

199

u8 lta_window_size;

sys/dev/pci/drm/radeon/ni_dpm.h

200

u8 lts_truncate;

sys/dev/pci/drm/radeon/ni_dpm.h

53

u8 last;

sys/dev/pci/drm/radeon/ni_dpm.h

54

u8 num_entries;

sys/dev/pci/drm/radeon/ni_dpm.h

92

u8 mc_wr_weight;

sys/dev/pci/drm/radeon/ni_dpm.h

93

u8 mc_rd_weight;

sys/dev/pci/drm/radeon/ni_dpm.h

94

u8 allow_ovrflw;

sys/dev/pci/drm/radeon/ni_dpm.h

95

u8 num_win_tdp;

sys/dev/pci/drm/radeon/ni_dpm.h

96

u8 l2num_win_tdp;

sys/dev/pci/drm/radeon/ni_dpm.h

97

u8 lts_truncate_n;

sys/dev/pci/drm/radeon/r100.c

2766

u8 byte;

sys/dev/pci/drm/radeon/r600.h

43

u8 enable_mask);

sys/dev/pci/drm/radeon/r600_dpm.c

1008

((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1058

((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1103

((u8 *)&array->entries[0] +

sys/dev/pci/drm/radeon/r600_dpm.c

1112

((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1118

((u8 *)&array->entries[0] +

sys/dev/pci/drm/radeon/r600_dpm.c

1129

((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1156

((u8 *)&array->entries[0] +

sys/dev/pci/drm/radeon/r600_dpm.c

1165

((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1192

((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1250

((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

1255

u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +

sys/dev/pci/drm/radeon/r600_dpm.c

1360

u8 r600_encode_pci_lane_width(u32 lanes)

sys/dev/pci/drm/radeon/r600_dpm.c

1362

static const u8 encoded_lanes[] = {

sys/dev/pci/drm/radeon/r600_dpm.c

836

((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));

sys/dev/pci/drm/radeon/r600_dpm.c

849

u8 frev, crev;

sys/dev/pci/drm/radeon/r600_dpm.c

879

u8 frev, crev;

sys/dev/pci/drm/radeon/r600_dpm.h

235

u8 r600_encode_pci_lane_width(u32 lanes);

sys/dev/pci/drm/radeon/r600_hdmi.c

144

u8 enable_mask)

sys/dev/pci/drm/radeon/r600_hdmi.c

252

const u8 *frame = buffer + 3;

sys/dev/pci/drm/radeon/radeon.h

1275

u8 vddc_id; /* index into vddc voltage table */

sys/dev/pci/drm/radeon/radeon.h

1276

u8 vddci_id; /* index into vddci voltage table */

sys/dev/pci/drm/radeon/radeon.h

1438

u8 count;

sys/dev/pci/drm/radeon/radeon.h

1449

u8 count;

sys/dev/pci/drm/radeon/radeon.h

1454

u8 ppm_design;

sys/dev/pci/drm/radeon/radeon.h

1508

u8 t_hyst;

sys/dev/pci/drm/radeon/radeon.h

1511

u8 control_mode;

sys/dev/pci/drm/radeon/radeon.h

1538

u8 clk_idx;

sys/dev/pci/drm/radeon/radeon.h

1539

u8 pstate;

sys/dev/pci/drm/radeon/radeon.h

1652

u8 fan_pulses_per_revolution;

sys/dev/pci/drm/radeon/radeon.h

1653

u8 fan_min_rpm;

sys/dev/pci/drm/radeon/radeon.h

1654

u8 fan_max_rpm;

sys/dev/pci/drm/radeon/radeon.h

1758

u8 status_bits;

sys/dev/pci/drm/radeon/radeon.h

1759

u8 category_code;

sys/dev/pci/drm/radeon/radeon.h

1907

void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/pci/drm/radeon/radeon.h

1909

u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);

sys/dev/pci/drm/radeon/radeon.h

2922

u8 enable_mask);

sys/dev/pci/drm/radeon/radeon.h

2925

u8 enable_mask);

sys/dev/pci/drm/radeon/radeon.h

2979

u8 perf_req, bool advertise);

sys/dev/pci/drm/radeon/radeon.h

305

u8 clock_type,

sys/dev/pci/drm/radeon/radeon.h

313

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);

sys/dev/pci/drm/radeon/radeon.h

315

u16 voltage_level, u8 voltage_type,

sys/dev/pci/drm/radeon/radeon.h

320

u8 voltage_type, u16 *voltage_step);

sys/dev/pci/drm/radeon/radeon.h

321

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,

sys/dev/pci/drm/radeon/radeon.h

336

u8 voltage_type,

sys/dev/pci/drm/radeon/radeon.h

340

u8 voltage_type, u16 *min_voltage);

sys/dev/pci/drm/radeon/radeon.h

342

u8 voltage_type, u16 *max_voltage);

sys/dev/pci/drm/radeon/radeon.h

344

u8 voltage_type, u8 voltage_mode,

sys/dev/pci/drm/radeon/radeon.h

347

u8 voltage_type, u8 voltage_mode);

sys/dev/pci/drm/radeon/radeon.h

349

u8 voltage_type,

sys/dev/pci/drm/radeon/radeon.h

350

u8 *svd_gpio_id, u8 *svc_gpio_id);

sys/dev/pci/drm/radeon/radeon.h

356

u8 module_index,

sys/dev/pci/drm/radeon/radeon.h

359

u8 module_index, struct atom_memory_info *mem_info);

sys/dev/pci/drm/radeon/radeon.h

361

bool gddr5, u8 module_index,

sys/dev/pci/drm/radeon/radeon.h

363

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,

sys/dev/pci/drm/radeon/radeon_acpi.c

60

u8 command_code; /* notify command code */

sys/dev/pci/drm/radeon/radeon_acpi.c

600

u8 perf_req, bool advertise)

sys/dev/pci/drm/radeon/radeon_acpi.c

66

u8 panel_exp_mode; /* panel expansion mode */

sys/dev/pci/drm/radeon/radeon_acpi.c

67

u8 thermal_gfx; /* thermal state: target gfx controller */

sys/dev/pci/drm/radeon/radeon_acpi.c

68

u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */

sys/dev/pci/drm/radeon/radeon_acpi.c

69

u8 forced_power_gfx; /* forced power state: target gfx controller */

sys/dev/pci/drm/radeon/radeon_acpi.c

70

u8 forced_power_state; /* forced power state: state id */

sys/dev/pci/drm/radeon/radeon_acpi.c

71

u8 system_power_src; /* system power source */

sys/dev/pci/drm/radeon/radeon_acpi.c

72

u8 backlight_level; /* panel backlight level (0-255) */

sys/dev/pci/drm/radeon/radeon_acpi.c

93

u8 req_type; /* request type */

sys/dev/pci/drm/radeon/radeon_acpi.c

94

u8 perf_req; /* performance request */

sys/dev/pci/drm/radeon/radeon_acpi.c

99

u8 ret_val; /* return value */

sys/dev/pci/drm/radeon/radeon_asic.h

45

void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/pci/drm/radeon/radeon_asic.h

46

u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);

sys/dev/pci/drm/radeon/radeon_asic.h

47

void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/pci/drm/radeon/radeon_asic.h

48

u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);

sys/dev/pci/drm/radeon/radeon_atombios.c

1117

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

1304

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

1402

((u8 *)&ss_info->asSS_Info[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

1415

((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));

sys/dev/pci/drm/radeon/radeon_atombios.c

1429

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

1542

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

1554

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));

sys/dev/pci/drm/radeon/radeon_atombios.c

1560

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

1576

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));

sys/dev/pci/drm/radeon/radeon_atombios.c

158

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/pci/drm/radeon/radeon_atombios.c

1582

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);

sys/dev/pci/drm/radeon/radeon_atombios.c

1603

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));

sys/dev/pci/drm/radeon/radeon_atombios.c

1698

u8 *record;

sys/dev/pci/drm/radeon/radeon_atombios.c

1702

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/pci/drm/radeon/radeon_atombios.c

1706

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/pci/drm/radeon/radeon_atombios.c

1801

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

193

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/pci/drm/radeon/radeon_atombios.c

199

u8 id)

sys/dev/pci/drm/radeon/radeon_atombios.c

2095

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

229

((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));

sys/dev/pci/drm/radeon/radeon_atombios.c

2387

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

2592

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

2685

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

2686

u8 *power_state_offset;

sys/dev/pci/drm/radeon/radeon_atombios.c

2710

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/radeon_atombios.c

2772

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

2844

u8 clock_type,

sys/dev/pci/drm/radeon/radeon_atombios.c

2851

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

2967

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3113

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)

sys/dev/pci/drm/radeon/radeon_atombios.c

3117

u8 frev, crev, volt_index = voltage_level;

sys/dev/pci/drm/radeon/radeon_atombios.c

3150

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,

sys/dev/pci/drm/radeon/radeon_atombios.c

3155

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3201

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3231

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3348

u16 voltage_level, u8 voltage_type,

sys/dev/pci/drm/radeon/radeon_atombios.c

3353

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3399

u8 voltage_type)

sys/dev/pci/drm/radeon/radeon_atombios.c

3403

u8 *start = (u8 *)v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

3416

u8 voltage_type)

sys/dev/pci/drm/radeon/radeon_atombios.c

3420

u8 *start = (u8 *)v2;

sys/dev/pci/drm/radeon/radeon_atombios.c

3433

u8 voltage_type, u8 voltage_mode)

sys/dev/pci/drm/radeon/radeon_atombios.c

3437

u8 *start = (u8 *)v3;

sys/dev/pci/drm/radeon/radeon_atombios.c

3451

u8 voltage_type, u8 voltage_mode)

sys/dev/pci/drm/radeon/radeon_atombios.c

3454

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3509

u8 voltage_type,

sys/dev/pci/drm/radeon/radeon_atombios.c

3510

u8 *svd_gpio_id, u8 *svc_gpio_id)

sys/dev/pci/drm/radeon/radeon_atombios.c

3513

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3553

u8 voltage_type, u16 *max_voltage)

sys/dev/pci/drm/radeon/radeon_atombios.c

3556

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3594

((u8 *)&formula->asVIDAdjustEntries[0] +

sys/dev/pci/drm/radeon/radeon_atombios.c

3612

u8 voltage_type, u16 *min_voltage)

sys/dev/pci/drm/radeon/radeon_atombios.c

3615

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3662

u8 voltage_type, u16 *voltage_step)

sys/dev/pci/drm/radeon/radeon_atombios.c

3665

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3703

u8 voltage_type,

sys/dev/pci/drm/radeon/radeon_atombios.c

3729

u8 voltage_type, u8 voltage_mode,

sys/dev/pci/drm/radeon/radeon_atombios.c

3733

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

3772

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));

sys/dev/pci/drm/radeon/radeon_atombios.c

3802

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));

sys/dev/pci/drm/radeon/radeon_atombios.c

3830

u8 module_index, struct atom_memory_info *mem_info)

sys/dev/pci/drm/radeon/radeon_atombios.c

3833

u8 frev, crev, i;

sys/dev/pci/drm/radeon/radeon_atombios.c

3856

((u8 *)vram_module + le16_to_cpu(vram_module->usSize));

sys/dev/pci/drm/radeon/radeon_atombios.c

3873

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/pci/drm/radeon/radeon_atombios.c

3897

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/pci/drm/radeon/radeon_atombios.c

3919

bool gddr5, u8 module_index,

sys/dev/pci/drm/radeon/radeon_atombios.c

3923

u8 frev, crev, i;

sys/dev/pci/drm/radeon/radeon_atombios.c

3952

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/pci/drm/radeon/radeon_atombios.c

3954

mclk_range_table->num_entries = (u8)

sys/dev/pci/drm/radeon/radeon_atombios.c

3961

((u8 *)format + mem_timing_size);

sys/dev/pci/drm/radeon/radeon_atombios.c

3992

u8 module_index,

sys/dev/pci/drm/radeon/radeon_atombios.c

3996

u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;

sys/dev/pci/drm/radeon/radeon_atombios.c

4017

((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));

sys/dev/pci/drm/radeon/radeon_atombios.c

4020

((u8 *)reg_block + (2 * sizeof(u16)) +

sys/dev/pci/drm/radeon/radeon_atombios.c

4023

num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /

sys/dev/pci/drm/radeon/radeon_atombios.c

4033

(u8)(format->ucPreRegDataLength);

sys/dev/pci/drm/radeon/radeon_atombios.c

4036

((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));

sys/dev/pci/drm/radeon/radeon_atombios.c

4041

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/pci/drm/radeon/radeon_atombios.c

4060

((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));

sys/dev/pci/drm/radeon/radeon_atombios.c

49

u8 index)

sys/dev/pci/drm/radeon/radeon_atombios.c

528

u8 frev, crev;

sys/dev/pci/drm/radeon/radeon_atombios.c

697

u8 *num_dst_objs = (u8 *)

sys/dev/pci/drm/radeon/radeon_atombios.c

698

((u8 *)router_src_dst_table + 1 +

sys/dev/pci/drm/radeon/radeon_atombios.c

978

u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;

sys/dev/pci/drm/radeon/radeon_audio.c

188

struct r600_audio_pin *pin, u8 enable_mask)

sys/dev/pci/drm/radeon/radeon_audio.c

332

u8 *sadb = NULL;

sys/dev/pci/drm/radeon/radeon_audio.c

39

u8 enable_mask);

sys/dev/pci/drm/radeon/radeon_audio.c

457

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/pci/drm/radeon/radeon_audio.c

534

u8 i;

sys/dev/pci/drm/radeon/radeon_audio.h

42

struct r600_audio_pin *pin, u8 enable_mask);

sys/dev/pci/drm/radeon/radeon_audio.h

53

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/radeon_audio.h

87

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/radeon_audio.h

89

u8 *sadb, int sad_count);

sys/dev/pci/drm/radeon/radeon_bios.c

239

bios = (u8 *)ISA_HOLE_VADDR(0xc0000);

sys/dev/pci/drm/radeon/radeon_combios.c

2635

u8 rev, tmp;

sys/dev/pci/drm/radeon/radeon_combios.c

2661

u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;

sys/dev/pci/drm/radeon/radeon_combios.c

2761

u8 entries = RBIOS8(offset + 0x5 + 0xb);

sys/dev/pci/drm/radeon/radeon_combios.c

641

u8 id, blocks, clk, data;

sys/dev/pci/drm/radeon/radeon_device.c

1763

u8 bl_level = radeon_get_backlight_level(rdev,

sys/dev/pci/drm/radeon/radeon_device.c

1870

u8 bl_level = radeon_get_backlight_level(rdev,

sys/dev/pci/drm/radeon/radeon_dp_auxch.c

64

u8 byte;

sys/dev/pci/drm/radeon/radeon_dp_auxch.c

65

u8 *buf = msg->buffer;

sys/dev/pci/drm/radeon/radeon_i2c.c

1153

u8 slave_addr,

sys/dev/pci/drm/radeon/radeon_i2c.c

1154

u8 addr,

sys/dev/pci/drm/radeon/radeon_i2c.c

1155

u8 *val)

sys/dev/pci/drm/radeon/radeon_i2c.c

1157

u8 out_buf[2];

sys/dev/pci/drm/radeon/radeon_i2c.c

1158

u8 in_buf[2];

sys/dev/pci/drm/radeon/radeon_i2c.c

1187

u8 slave_addr,

sys/dev/pci/drm/radeon/radeon_i2c.c

1188

u8 addr,

sys/dev/pci/drm/radeon/radeon_i2c.c

1189

u8 val)

sys/dev/pci/drm/radeon/radeon_i2c.c

1210

u8 val;

sys/dev/pci/drm/radeon/radeon_i2c.c

1238

u8 val;

sys/dev/pci/drm/radeon/radeon_i2c.c

335

u8 n, m, loop;

sys/dev/pci/drm/radeon/radeon_i2c.c

42

u8 out = 0x0;

sys/dev/pci/drm/radeon/radeon_i2c.c

43

u8 buf[8];

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

282

u8

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

287

u8 backlight_level;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

296

radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)

sys/dev/pci/drm/radeon/radeon_mode.h

341

u8 h_border;

sys/dev/pci/drm/radeon/radeon_mode.h

342

u8 v_border;

sys/dev/pci/drm/radeon/radeon_mode.h

470

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/pci/drm/radeon/radeon_mode.h

471

u8 dp_sink_type;

sys/dev/pci/drm/radeon/radeon_mode.h

479

u8 id;

sys/dev/pci/drm/radeon/radeon_mode.h

487

u8 plugged_state;

sys/dev/pci/drm/radeon/radeon_mode.h

494

u8 i2c_addr;

sys/dev/pci/drm/radeon/radeon_mode.h

497

u8 ddc_mux_type;

sys/dev/pci/drm/radeon/radeon_mode.h

498

u8 ddc_mux_control_pin;

sys/dev/pci/drm/radeon/radeon_mode.h

499

u8 ddc_mux_state;

sys/dev/pci/drm/radeon/radeon_mode.h

502

u8 cd_mux_type;

sys/dev/pci/drm/radeon/radeon_mode.h

503

u8 cd_mux_control_pin;

sys/dev/pci/drm/radeon/radeon_mode.h

504

u8 cd_mux_state;

sys/dev/pci/drm/radeon/radeon_mode.h

604

u8 mem_vendor;

sys/dev/pci/drm/radeon/radeon_mode.h

605

u8 mem_type;

sys/dev/pci/drm/radeon/radeon_mode.h

611

u8 num_entries;

sys/dev/pci/drm/radeon/radeon_mode.h

612

u8 rsv[3];

sys/dev/pci/drm/radeon/radeon_mode.h

626

u8 pre_reg_data;

sys/dev/pci/drm/radeon/radeon_mode.h

630

u8 last;

sys/dev/pci/drm/radeon/radeon_mode.h

631

u8 num_entries;

sys/dev/pci/drm/radeon/radeon_mode.h

716

extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);

sys/dev/pci/drm/radeon/radeon_mode.h

721

u8 power_state);

sys/dev/pci/drm/radeon/radeon_mode.h

738

void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);

sys/dev/pci/drm/radeon/radeon_mode.h

754

u8 slave_addr,

sys/dev/pci/drm/radeon/radeon_mode.h

755

u8 addr,

sys/dev/pci/drm/radeon/radeon_mode.h

756

u8 *val);

sys/dev/pci/drm/radeon/radeon_mode.h

758

u8 slave_addr,

sys/dev/pci/drm/radeon/radeon_mode.h

759

u8 addr,

sys/dev/pci/drm/radeon/radeon_mode.h

760

u8 val);

sys/dev/pci/drm/radeon/radeon_mode.h

772

u8 id);

sys/dev/pci/drm/radeon/rs780_dpm.c

720

u8 table_rev)

sys/dev/pci/drm/radeon/rs780_dpm.c

799

u8 frev, crev;

sys/dev/pci/drm/radeon/rs780_dpm.c

853

u8 frev, crev;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1002

int d_l, int d_r, u8 *l, u8 *r)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1882

u8 frev, crev;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1907

u8 *idx;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1916

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/rv6xx_dpm.c

241

u32 start_index, u8 *end_index)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

292

*end_index = (u8)step_index - 1;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

42

u8 high_sclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

43

u8 medium_sclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

44

u8 low_sclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

45

u8 high_mclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

46

u8 medium_mclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

47

u8 low_mclk_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

48

u8 high_vddc_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

49

u8 medium_vddc_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

50

u8 low_vddc_index;

sys/dev/pci/drm/radeon/rv6xx_dpm.h

51

u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/pci/drm/radeon/rv6xx_dpm.h

52

u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/pci/drm/radeon/rv730_dpm.c

497

pi->odt_value_0[0] = (u8)0;

sys/dev/pci/drm/radeon/rv730_dpm.c

498

pi->odt_value_1[0] = (u8)0x80;

sys/dev/pci/drm/radeon/rv730_dpm.c

501

pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/pci/drm/radeon/rv730_dpm.c

504

pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/pci/drm/radeon/rv740_dpm.c

408

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/radeon/rv740_dpm.c

410

u8 mc_para_index;

sys/dev/pci/drm/radeon/rv740_dpm.c

415

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/pci/drm/radeon/rv770_dpm.c

1228

(const u8 *)table,

sys/dev/pci/drm/radeon/rv770_dpm.c

1238

u8 vddc_index = 0;

sys/dev/pci/drm/radeon/rv770_dpm.c

1271

pi->valid_vddc_entries = (u8)steps;

sys/dev/pci/drm/radeon/rv770_dpm.c

1305

u8 rv770_get_memory_module_index(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv770_dpm.c

1307

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

sys/dev/pci/drm/radeon/rv770_dpm.c

1313

u8 memory_module_index;

sys/dev/pci/drm/radeon/rv770_dpm.c

1396

return rv770_copy_bytes_to_smc(rdev, address, (const u8 *)&state,

sys/dev/pci/drm/radeon/rv770_dpm.c

1674

u8 memory_module_index;

sys/dev/pci/drm/radeon/rv770_dpm.c

2148

u8 table_rev)

sys/dev/pci/drm/radeon/rv770_dpm.c

2278

u8 frev, crev;

sys/dev/pci/drm/radeon/rv770_dpm.c

228

u8 rv770_get_seq_value(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv770_dpm.c

2303

u8 *idx;

sys/dev/pci/drm/radeon/rv770_dpm.c

2313

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/rv770_dpm.c

266

u8 l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];

sys/dev/pci/drm/radeon/rv770_dpm.c

267

u8 r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];

sys/dev/pci/drm/radeon/rv770_dpm.c

278

l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);

sys/dev/pci/drm/radeon/rv770_dpm.c

279

r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);

sys/dev/pci/drm/radeon/rv770_dpm.c

286

l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);

sys/dev/pci/drm/radeon/rv770_dpm.c

287

r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);

sys/dev/pci/drm/radeon/rv770_dpm.c

392

u8 encoded_reference_dividers[] = { 0, 16, 17, 20, 21 };

sys/dev/pci/drm/radeon/rv770_dpm.c

618

u8 watermark_level)

sys/dev/pci/drm/radeon/rv770_dpm.h

107

u8 valid_vddc_entries;

sys/dev/pci/drm/radeon/rv770_dpm.h

110

u8 odt_value_0[2];

sys/dev/pci/drm/radeon/rv770_dpm.h

111

u8 odt_value_1[2];

sys/dev/pci/drm/radeon/rv770_dpm.h

212

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);

sys/dev/pci/drm/radeon/rv770_dpm.h

222

u8 rv770_get_seq_value(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/rv770_dpm.h

238

u8 rv770_get_memory_module_index(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/rv770_dpm.h

67

u8 vddc_index;

sys/dev/pci/drm/radeon/rv770_dpm.h

68

u8 high_smio;

sys/dev/pci/drm/radeon/rv770_smc.c

113

static const u8 cedar_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

132

static const u8 redwood_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

151

static const u8 juniper_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

170

static const u8 cypress_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

189

static const u8 barts_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

208

static const u8 turks_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

227

static const u8 caicos_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

246

static const u8 cayman_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

284

u16 smc_start_address, const u8 *src,

sys/dev/pci/drm/radeon/rv770_smc.c

351

u32 smc_first_vector, const u8 *src,

sys/dev/pci/drm/radeon/rv770_smc.c

37

static const u8 rv770_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

472

const u8 *int_vect;

sys/dev/pci/drm/radeon/rv770_smc.c

475

const u8 *ucode_data;

sys/dev/pci/drm/radeon/rv770_smc.c

488

int_vect = (const u8 *)&rv770_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

495

int_vect = (const u8 *)&rv730_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

502

int_vect = (const u8 *)&rv710_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

509

int_vect = (const u8 *)&rv740_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

516

int_vect = (const u8 *)&cedar_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

523

int_vect = (const u8 *)&redwood_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

530

int_vect = (const u8 *)&juniper_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

538

int_vect = (const u8 *)&cypress_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

545

int_vect = (const u8 *)&barts_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

552

int_vect = (const u8 *)&turks_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

559

int_vect = (const u8 *)&caicos_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

56

static const u8 rv730_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

566

int_vect = (const u8 *)&cayman_smc_int_vectors;

sys/dev/pci/drm/radeon/rv770_smc.c

576

ucode_data = (const u8 *)rdev->smc_fw->data;

sys/dev/pci/drm/radeon/rv770_smc.c

75

static const u8 rv710_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.c

94

static const u8 rv740_smc_int_vectors[] = {

sys/dev/pci/drm/radeon/rv770_smc.h

182

u16 smc_start_address, const u8 *src,

sys/dev/pci/drm/radeon/si_dpm.c

2129

(u8 *)(&(smc_table->dpm2Params.TDPLimit)),

sys/dev/pci/drm/radeon/si_dpm.c

2146

(u8 *)papm_parm,

sys/dev/pci/drm/radeon/si_dpm.c

2178

(u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),

sys/dev/pci/drm/radeon/si_dpm.c

2237

u8 max_ps_percent;

sys/dev/pci/drm/radeon/si_dpm.c

2306

smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/pci/drm/radeon/si_dpm.c

2410

u8 tdep_count;

sys/dev/pci/drm/radeon/si_dpm.c

2461

ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,

sys/dev/pci/drm/radeon/si_dpm.c

2653

ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,

sys/dev/pci/drm/radeon/si_dpm.c

2841

(u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),

sys/dev/pci/drm/radeon/si_dpm.c

3767

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/pci/drm/radeon/si_dpm.c

3769

u8 mc_para_index;

sys/dev/pci/drm/radeon/si_dpm.c

3776

mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);

sys/dev/pci/drm/radeon/si_dpm.c

3780

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/pci/drm/radeon/si_dpm.c

3782

u8 mc_para_index;

sys/dev/pci/drm/radeon/si_dpm.c

3790

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/pci/drm/radeon/si_dpm.c

3797

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/pci/drm/radeon/si_dpm.c

3802

static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/pci/drm/radeon/si_dpm.c

3806

u8 result = 0;

sys/dev/pci/drm/radeon/si_dpm.c

3996

u8 i;

sys/dev/pci/drm/radeon/si_dpm.c

4061

voltage->index = (u8)i;

sys/dev/pci/drm/radeon/si_dpm.c

4083

voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;

sys/dev/pci/drm/radeon/si_dpm.c

4142

u16 value, u8 index,

sys/dev/pci/drm/radeon/si_dpm.c

4165

smc_voltage->phase_settings = (u8)i;

sys/dev/pci/drm/radeon/si_dpm.c

4244

(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);

sys/dev/pci/drm/radeon/si_dpm.c

4256

arb_regs->mc_arb_burst_time = (u8)burst_time;

sys/dev/pci/drm/radeon/si_dpm.c

4278

(u8 *)&arb_regs,

sys/dev/pci/drm/radeon/si_dpm.c

4399

table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/pci/drm/radeon/si_dpm.c

4492

table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,

sys/dev/pci/drm/radeon/si_dpm.c

4592

state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);

sys/dev/pci/drm/radeon/si_dpm.c

4622

(u8 *)&arb_regs,

sys/dev/pci/drm/radeon/si_dpm.c

4722

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/pci/drm/radeon/si_dpm.c

4935

level->gen2PCIE = (u8)si_pi->force_pcie_gen;

sys/dev/pci/drm/radeon/si_dpm.c

4937

level->gen2PCIE = (u8)pl->pcie_gen;

sys/dev/pci/drm/radeon/si_dpm.c

5175

(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/pci/drm/radeon/si_dpm.c

5231

ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,

sys/dev/pci/drm/radeon/si_dpm.c

5253

ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,

sys/dev/pci/drm/radeon/si_dpm.c

5303

u8 i, j, k;

sys/dev/pci/drm/radeon/si_dpm.c

5426

u8 i, j;

sys/dev/pci/drm/radeon/si_dpm.c

5452

u8 i, j;

sys/dev/pci/drm/radeon/si_dpm.c

5481

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/pci/drm/radeon/si_dpm.c

5543

mc_reg_table->last = (u8)i;

sys/dev/pci/drm/radeon/si_dpm.c

5628

(u8 *)smc_mc_reg_table,

sys/dev/pci/drm/radeon/si_dpm.c

5648

(u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/pci/drm/radeon/si_dpm.c

5733

u8 request;

sys/dev/pci/drm/radeon/si_dpm.c

6038

(u8 *)(&fan_table),

sys/dev/pci/drm/radeon/si_dpm.c

6652

u8 table_rev)

sys/dev/pci/drm/radeon/si_dpm.c

6764

u8 frev, crev;

sys/dev/pci/drm/radeon/si_dpm.c

6765

u8 *power_state_offset;

sys/dev/pci/drm/radeon/si_dpm.c

6788

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/si_dpm.c

6790

u8 *idx;

sys/dev/pci/drm/radeon/si_dpm.c

6807

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/radeon/si_dpm.c

6815

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/radeon/si_dpm.h

108

u8 last;

sys/dev/pci/drm/radeon/si_dpm.h

109

u8 num_entries;

sys/dev/pci/drm/radeon/si_dpm.h

192

u8 svd_gpio_id;

sys/dev/pci/drm/radeon/si_dpm.h

193

u8 svc_gpio_id;

sys/dev/pci/drm/radeon/si_dpm.h

230

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);

sys/dev/pci/drm/radeon/si_dpm.h

231

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);

sys/dev/pci/drm/radeon/si_dpm.h

46

u8 lts_truncate_default;

sys/dev/pci/drm/radeon/si_dpm.h

47

u8 shift_n_default;

sys/dev/pci/drm/radeon/si_dpm.h

48

u8 operating_temp;

sys/dev/pci/drm/radeon/si_dpm.h

52

u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/pci/drm/radeon/si_dpm.h

61

u8 lts_truncate;

sys/dev/pci/drm/radeon/si_dpm.h

62

u8 shift_n;

sys/dev/pci/drm/radeon/si_dpm.h

63

u8 dc_pwr_value;

sys/dev/pci/drm/radeon/si_dpm.h

73

u8 window_size;

sys/dev/pci/drm/radeon/si_dpm.h

74

u8 temp_select;

sys/dev/pci/drm/radeon/si_dpm.h

75

u8 dte_mode;

sys/dev/pci/drm/radeon/si_dpm.h

76

u8 tdep_count;

sys/dev/pci/drm/radeon/si_dpm.h

77

u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/radeon/si_smc.c

138

static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };

sys/dev/pci/drm/radeon/si_smc.c

216

const u8 *src;

sys/dev/pci/drm/radeon/si_smc.c

230

src = (const u8 *)

sys/dev/pci/drm/radeon/si_smc.c

258

src = (const u8 *)rdev->smc_fw->data;

sys/dev/pci/drm/radeon/si_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/pci/drm/radeon/sislands_smc.h

399

const u8 *src, u32 byte_count, u32 limit);

sys/dev/pci/drm/radeon/sumo_dpm.c

1403

u8 table_rev)

sys/dev/pci/drm/radeon/sumo_dpm.c

1463

u8 frev, crev;

sys/dev/pci/drm/radeon/sumo_dpm.c

1464

u8 *power_state_offset;

sys/dev/pci/drm/radeon/sumo_dpm.c

1487

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/sumo_dpm.c

1489

u8 *idx;

sys/dev/pci/drm/radeon/sumo_dpm.c

1505

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/radeon/sumo_dpm.c

1512

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/radeon/sumo_dpm.c

1663

u8 frev, crev;

sys/dev/pci/drm/radeon/sumo_dpm.h

86

u8 htc_tmp_lmt;

sys/dev/pci/drm/radeon/sumo_dpm.h

87

u8 htc_hyst_lmt;

sys/dev/pci/drm/radeon/trinity_dpm.c

1286

static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)

sys/dev/pci/drm/radeon/trinity_dpm.c

1309

static u8 trinity_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/trinity_dpm.c

1330

return (u8)i;

sys/dev/pci/drm/radeon/trinity_dpm.c

1383

static u8 trinity_calculate_display_wm(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/trinity_dpm.c

1635

u8 table_rev)

sys/dev/pci/drm/radeon/trinity_dpm.c

1694

u8 frev, crev;

sys/dev/pci/drm/radeon/trinity_dpm.c

1695

u8 *power_state_offset;

sys/dev/pci/drm/radeon/trinity_dpm.c

1718

power_state_offset = (u8 *)state_array->states;

sys/dev/pci/drm/radeon/trinity_dpm.c

1720

u8 *idx;

sys/dev/pci/drm/radeon/trinity_dpm.c

1736

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/pci/drm/radeon/trinity_dpm.c

1744

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/pci/drm/radeon/trinity_dpm.c

1781

static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)

sys/dev/pci/drm/radeon/trinity_dpm.c

1806

u8 frev, crev;

sys/dev/pci/drm/radeon/trinity_dpm.h

32

u8 vddc_index;

sys/dev/pci/drm/radeon/trinity_dpm.h

33

u8 ds_divider_index;

sys/dev/pci/drm/radeon/trinity_dpm.h

34

u8 ss_divider_index;

sys/dev/pci/drm/radeon/trinity_dpm.h

35

u8 allow_gnb_slow;

sys/dev/pci/drm/radeon/trinity_dpm.h

36

u8 force_nbp_state;

sys/dev/pci/drm/radeon/trinity_dpm.h

37

u8 display_wm;

sys/dev/pci/drm/radeon/trinity_dpm.h

38

u8 vce_wm;

sys/dev/pci/drm/radeon/trinity_dpm.h

54

u8 Dpm0PgNbPsLo;

sys/dev/pci/drm/radeon/trinity_dpm.h

55

u8 Dpm0PgNbPsHi;

sys/dev/pci/drm/radeon/trinity_dpm.h

56

u8 DpmXNbPsLo;

sys/dev/pci/drm/radeon/trinity_dpm.h

57

u8 DpmXNbPsHi;

sys/dev/pci/drm/radeon/trinity_dpm.h

70

u8 vclk_did;

sys/dev/pci/drm/radeon/trinity_dpm.h

71

u8 dclk_did;

sys/dev/pci/drm/radeon/trinity_dpm.h

72

u8 rsv[2];

sys/dev/pci/drm/radeon/trinity_dpm.h

85

u8 htc_tmp_lmt;

sys/dev/pci/drm/radeon/trinity_dpm.h

86

u8 htc_hyst_lmt;

sys/dev/pci/drm/ttm/ttm_bo_util.c

326

map->virtual = ((u8 *)bo->resource->bus.addr) + offset;

sys/dev/pci/if_ice.c

27041

SDT_PROBE2(ice_fwlog, , , message, (const u8 *)buf, desc->datalen);

sys/dev/pci/if_mcx.c

3179

mcx_mix_u8(uint32_t xor, uint8_t u8)

sys/dev/pci/if_mcx.c

3181

xor ^= u8;

sys/dev/pci/if_mwx.c

4338

u8 *data = (u8 *)rxd;

sys/dev/pci/if_mwx.c

4388

u8 stbc, gi;

sys/dev/pci/if_mwx.c

4515

u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);

sys/dev/pci/igc_defines.h

1268

(u8)((invm_dword) & 0x7)

sys/dev/pci/igc_defines.h

1270

(u8)(((invm_dword) & 0x0000FE00) >> 9)

sys/dev/usb/dwc2/dwc2_core.h

1215

u8 *status_buf;

sys/dev/usb/dwc2/dwc2_core.h

1223

u8 otg_port;

sys/dev/usb/dwc2/dwc2_core.h

1250

u8 test_mode;

sys/dev/usb/dwc2/dwc2_core.h

1366

void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);

sys/dev/usb/dwc2/dwc2_core.h

200

u8 desc_count;

sys/dev/usb/dwc2/dwc2_core.h

496

u8 phy_type;

sys/dev/usb/dwc2/dwc2_core.h

501

u8 speed;

sys/dev/usb/dwc2/dwc2_core.h

506

u8 phy_utmi_width;

sys/dev/usb/dwc2/dwc2_core.h

530

u8 hird_threshold;

sys/dev/usb/dwc2/dwc2_core.h

551

u8 host_channels;

sys/dev/usb/dwc2/dwc2_hcd.c

2019

u8 in_process = urb_qtd->in_process;

sys/dev/usb/dwc2/dwc2_hcd.c

2391

chan->hub_addr = (u8)hub_addr;

sys/dev/usb/dwc2/dwc2_hcd.c

2392

chan->hub_port = (u8)hub_port;

sys/dev/usb/dwc2/dwc2_hcd.c

2693

chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;

sys/dev/usb/dwc2/dwc2_hcd.c

3933

struct dwc2_hcd_urb *urb, u8 dev_addr,

sys/dev/usb/dwc2/dwc2_hcd.c

3934

u8 ep_num, u8 ep_type, u8 ep_dir,

sys/dev/usb/dwc2/dwc2_hcd.c

423

void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)

sys/dev/usb/dwc2/dwc2_hcd.c

4782

u8 ep_type = 0;

sys/dev/usb/dwc2/dwc2_hcd.c

709

u8 hc_num = chan->hc_num;

sys/dev/usb/dwc2/dwc2_hcd.h

121

u8 hc_num;

sys/dev/usb/dwc2/dwc2_hcd.h

139

u8 *xfer_buf;

sys/dev/usb/dwc2/dwc2_hcd.h

145

u8 xfer_started;

sys/dev/usb/dwc2/dwc2_hcd.h

146

u8 do_ping;

sys/dev/usb/dwc2/dwc2_hcd.h

147

u8 error_state;

sys/dev/usb/dwc2/dwc2_hcd.h

148

u8 halt_on_queue;

sys/dev/usb/dwc2/dwc2_hcd.h

149

u8 halt_pending;

sys/dev/usb/dwc2/dwc2_hcd.h

150

u8 do_split;

sys/dev/usb/dwc2/dwc2_hcd.h

151

u8 complete_split;

sys/dev/usb/dwc2/dwc2_hcd.h

152

u8 hub_addr;

sys/dev/usb/dwc2/dwc2_hcd.h

153

u8 hub_port;

sys/dev/usb/dwc2/dwc2_hcd.h

154

u8 xact_pos;

sys/dev/usb/dwc2/dwc2_hcd.h

160

u8 requests;

sys/dev/usb/dwc2/dwc2_hcd.h

161

u8 schinfo;

sys/dev/usb/dwc2/dwc2_hcd.h

174

u8 dev_addr;

sys/dev/usb/dwc2/dwc2_hcd.h

175

u8 ep_num;

sys/dev/usb/dwc2/dwc2_hcd.h

176

u8 pipe_type;

sys/dev/usb/dwc2/dwc2_hcd.h

177

u8 pipe_dir;

sys/dev/usb/dwc2/dwc2_hcd.h

348

u8 ep_type;

sys/dev/usb/dwc2/dwc2_hcd.h

349

u8 ep_is_in;

sys/dev/usb/dwc2/dwc2_hcd.h

352

u8 dev_speed;

sys/dev/usb/dwc2/dwc2_hcd.h

353

u8 data_toggle;

sys/dev/usb/dwc2/dwc2_hcd.h

354

u8 ping_state;

sys/dev/usb/dwc2/dwc2_hcd.h

355

u8 do_split;

sys/dev/usb/dwc2/dwc2_hcd.h

356

u8 td_first;

sys/dev/usb/dwc2/dwc2_hcd.h

357

u8 td_last;

sys/dev/usb/dwc2/dwc2_hcd.h

368

u8 *dw_align_buf;

sys/dev/usb/dwc2/dwc2_hcd.h

442

u8 in_process;

sys/dev/usb/dwc2/dwc2_hcd.h

443

u8 data_toggle;

sys/dev/usb/dwc2/dwc2_hcd.h

444

u8 complete_split;

sys/dev/usb/dwc2/dwc2_hcd.h

445

u8 isoc_split_pos;

sys/dev/usb/dwc2/dwc2_hcd.h

451

u8 error_count;

sys/dev/usb/dwc2/dwc2_hcd.h

452

u8 n_desc;

sys/dev/usb/dwc2/dwc2_hcd.h

510

static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

515

static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

530

static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

535

static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

540

static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

545

static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

550

static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

555

static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

560

static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)

sys/dev/usb/dwc2/dwc2_hcd.h

839

u8, u8, u8, u8, u16, u16);

sys/dev/usb/dwc2/dwc2_hcdddma.c

425

STATIC u8 dwc2_frame_to_desc_idx(struct dwc2_qh *qh, u16 frame_idx)

sys/dev/usb/dwc2/dwc2_hcdddma.c

66

STATIC u16 dwc2_desclist_idx_inc(u16 idx, u16 inc, u8 speed)

sys/dev/usb/dwc2/dwc2_hcdddma.c

73

STATIC u16 dwc2_desclist_idx_dec(u16 idx, u16 inc, u8 speed)

sys/dev/usb/dwc2/dwc2_hcdqueue.c

1516

u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);

sys/lib/libsa/rijndael.c

1038

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

sys/lib/libsa/rijndael.c

1039

u8 pt[16])

sys/lib/libsa/rijndael.c

716

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

sys/lib/libsa/rijndael.c

724

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/lib/libsa/rijndael.c

811

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

sys/lib/libsa/rijndael.c

854

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

sys/lib/libsa/rijndael.c

855

u8 ct[16])

sys/netinet/inet_nat64.c

109

d->u8[j] = s->u8[i++];

sys/netinet/inet_nat64.c

150

d->u8[8] = 0;

sys/netinet/inet_nat64.c

156

d->u8[i++] = s->u8[j];

sys/netinet/inet_nat64.c

28

u_int8_t u8[16];

usr.bin/hexdump/display.c

122

u_int64_t u8;

usr.bin/hexdump/display.c

194

memmove(&u8, bp, sizeof(u8));

usr.bin/hexdump/display.c

195

(void)printf(pr->fmt, u8);

usr.bin/openssl/ca.c

1656

is_printablestring_octet(const uint8_t u8)

usr.bin/openssl/ca.c

1662

if (u8 >= 'A' && u8 <= 'Z')

usr.bin/openssl/ca.c

1664

if (u8 >= 'a' && u8 <= 'z')

usr.bin/openssl/ca.c

1666

if (u8 >= '0' && u8 <= '9')

usr.bin/openssl/ca.c

1669

return u8 == ' ' || u8 == '\'' || u8 == '(' || u8 == ')' || u8 == '+' ||

usr.bin/openssl/ca.c

1670

u8 == ',' || u8 == '-' || u8 == '.' || u8 == '/' || u8 == ':' ||

usr.bin/openssl/ca.c

1671

u8 == '=' || u8 == '?';

usr.bin/ssh/chacha.c

18

#define U8V(v) ((u8)(v) & U8C(0xFF))

usr.bin/ssh/chacha.c

53

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

usr.bin/ssh/chacha.c

78

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

usr.bin/ssh/chacha.c

87

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

usr.bin/ssh/chacha.c

91

u8 *ctarget = NULL;

usr.bin/ssh/chacha.c

92

u8 tmp[64];

usr.bin/ssh/cipher-aesctr.c

29

aesctr_inc(u8 *ctr, u32 len)

usr.bin/ssh/cipher-aesctr.c

38

u8 x, add = 1;

usr.bin/ssh/cipher-aesctr.c

53

aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits)

usr.bin/ssh/cipher-aesctr.c

59

aesctr_ivsetup(aesctr_ctx *x,const u8 *iv)

usr.bin/ssh/cipher-aesctr.c

65

aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes)

usr.bin/ssh/cipher-aesctr.c

68

u8 buf[AES_BLOCK_SIZE];

usr.bin/ssh/cipher-aesctr.h

28

u8 ctr[AES_BLOCK_SIZE]; /* counter */

usr.bin/ssh/cipher-aesctr.h

31

void aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits);

usr.bin/ssh/cipher-aesctr.h

32

void aesctr_ivsetup(aesctr_ctx *x,const u8 *iv);

usr.bin/ssh/cipher-aesctr.h

33

void aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes);

usr.bin/ssh/rijndael.c

580

static const u8 Td4[256] = {

usr.bin/ssh/rijndael.c

622

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

usr.bin/ssh/rijndael.c

630

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

usr.bin/ssh/rijndael.c

718

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

usr.bin/ssh/rijndael.c

762

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

usr.bin/ssh/rijndael.c

763

u8 ct[16])

usr.bin/ssh/rijndael.c

947

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

usr.bin/ssh/rijndael.c

948

u8 pt[16])

usr.bin/ssh/rijndael.h

41

void rijndaelEncrypt(const unsigned int [], int, const u8 [16], u8 [16]);

usr.bin/ssh/umac.c

167

rijndaelEncrypt((u32 *)(int_key), AES_ROUNDS, (u8 *)(in), (u8 *)(out))

usr.bin/tic/tic.c

3166

NO_QUERY(user8, u8);

usr.sbin/bgpctl/parser.c

1511

uint8_t u8, flag = 0;

usr.sbin/bgpctl/parser.c

1522

u8 = val;

usr.sbin/bgpctl/parser.c

1523

data = &u8;

usr.sbin/bgpd/parse.y

212

uint8_t u8;

usr.sbin/bgpd/parse.y

282

%type <v.u8> action quick direction delete community

usr.sbin/bgpd/parse.y

293

%type <v.u8> unaryop equalityop binaryop filter_as_type

usr.sbin/bgpd/parse.y

5777

uint8_t u8;

usr.sbin/bgpd/parse.y

5783

u8 = val;

usr.sbin/bgpd/parse.y

5794

comp[complen++] = u8;

usr.sbin/bgpd/parse.y

5854

uint8_t u8;

usr.sbin/bgpd/parse.y

5862

u8 = val;

usr.sbin/bgpd/parse.y

5863

data = &u8;

usr.sbin/rpki-client/x509.c

354

valid_printable_octet(const uint8_t u8)

usr.sbin/rpki-client/x509.c

360

if ('A' <= u8 && u8 <= 'Z')

usr.sbin/rpki-client/x509.c

362

if ('a' <= u8 && u8 <= 'z')

usr.sbin/rpki-client/x509.c

364

if ('0' <= u8 && u8 <= '9')

usr.sbin/rpki-client/x509.c

367

return u8 == ' ' || u8 == '\'' || u8 == '(' || u8 == ')' || u8 == '+' ||

usr.sbin/rpki-client/x509.c

368

u8 == ',' || u8 == '-' || u8 == '.' || u8 == '/' || u8 == ':' ||

usr.sbin/rpki-client/x509.c

369

u8 == '=' || u8 == '?';

usr.sbin/snmpd/ax.c

106

uint8_t *u8;

usr.sbin/snmpd/ax.c

124

u8 = ax->ax_rbuf;

usr.sbin/snmpd/ax.c

125

header.aph_version = *u8++;

usr.sbin/snmpd/ax.c

126

header.aph_type = *u8++;

usr.sbin/snmpd/ax.c

127

header.aph_flags = *u8++;

usr.sbin/snmpd/ax.c

128

u8++;

usr.sbin/snmpd/ax.c

129

header.aph_sessionid = ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

130

u8 += 4;

usr.sbin/snmpd/ax.c

131

header.aph_transactionid = ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

132

u8 += 4;

usr.sbin/snmpd/ax.c

133

header.aph_packetid = ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

134

u8 += 4;

usr.sbin/snmpd/ax.c

135

header.aph_plength = ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

191

u8 = (ax->ax_rbuf) + AX_PDU_HEADER;

usr.sbin/snmpd/ax.c

194

nread = ax_pdutoostring(&header, &(pdu->ap_context), u8,

usr.sbin/snmpd/ax.c

199

u8 += nread;

usr.sbin/snmpd/ax.c

208

pdu->ap_payload.ap_open.ap_timeout = *u8;

usr.sbin/snmpd/ax.c

210

u8 += 4;

usr.sbin/snmpd/ax.c

212

&(pdu->ap_payload.ap_open.ap_oid), u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

215

u8 += nread;

usr.sbin/snmpd/ax.c

217

&(pdu->ap_payload.ap_open.ap_descr), u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

229

if (u8[0] != AX_CLOSE_OTHER &&

usr.sbin/snmpd/ax.c

230

u8[0] != AX_CLOSEN_PARSEERROR &&

usr.sbin/snmpd/ax.c

231

u8[0] != AX_CLOSE_PROTOCOLERROR &&

usr.sbin/snmpd/ax.c

232

u8[0] != AX_CLOSE_TIMEOUTS &&

usr.sbin/snmpd/ax.c

233

u8[0] != AX_CLOSE_SHUTDOWN &&

usr.sbin/snmpd/ax.c

234

u8[0] != AX_CLOSE_BYMANAGER) {

usr.sbin/snmpd/ax.c

238

pdu->ap_payload.ap_close.ap_reason = u8[0];

usr.sbin/snmpd/ax.c

245

pdu->ap_payload.ap_register.ap_timeout = *u8++;

usr.sbin/snmpd/ax.c

246

pdu->ap_payload.ap_register.ap_priority = *u8++;

usr.sbin/snmpd/ax.c

247

pdu->ap_payload.ap_register.ap_range_subid = *u8++;

usr.sbin/snmpd/ax.c

248

u8++;

usr.sbin/snmpd/ax.c

252

u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

255

u8 += nread;

usr.sbin/snmpd/ax.c

262

ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

275

u8++;

usr.sbin/snmpd/ax.c

276

pdu->ap_payload.ap_unregister.ap_priority = *u8++;

usr.sbin/snmpd/ax.c

277

pdu->ap_payload.ap_unregister.ap_range_subid = *u8++;

usr.sbin/snmpd/ax.c

278

u8++;

usr.sbin/snmpd/ax.c

282

u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

285

u8 += nread;

usr.sbin/snmpd/ax.c

292

ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

306

ax_pdutoh16(&header, u8);

usr.sbin/snmpd/ax.c

307

u8 += 2;

usr.sbin/snmpd/ax.c

309

ax_pdutoh16(&header, u8);

usr.sbin/snmpd/ax.c

310

u8 += 2;

usr.sbin/snmpd/ax.c

326

u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

329

u8 += nread;

usr.sbin/snmpd/ax.c

331

u8, rawlen)) == -1)

usr.sbin/snmpd/ax.c

334

u8 += nread;

usr.sbin/snmpd/ax.c

350

&(vbl->ap_varbind[vbl->ap_nvarbind]), u8, rawlen);

usr.sbin/snmpd/ax.c

354

u8 += nread;

usr.sbin/snmpd/ax.c

369

&(pdu->ap_payload.ap_addagentcaps.ap_oid), u8, rawlen);

usr.sbin/snmpd/ax.c

373

u8 += nread;

usr.sbin/snmpd/ax.c

375

&(pdu->ap_payload.ap_addagentcaps.ap_descr), u8, rawlen);

usr.sbin/snmpd/ax.c

385

&(pdu->ap_payload.ap_removeagentcaps.ap_oid), u8, rawlen);

usr.sbin/snmpd/ax.c

399

response->ap_uptime = ax_pdutoh32(&header, u8);

usr.sbin/snmpd/ax.c

400

u8 += 4;

usr.sbin/snmpd/ax.c

401

response->ap_error = ax_pdutoh16(&header, u8);

usr.sbin/snmpd/ax.c

402

u8 += 2;

usr.sbin/snmpd/ax.c

403

response->ap_index = ax_pdutoh16(&header, u8);

usr.sbin/snmpd/ax.c

404

u8 += 2;

usr.sbin/snmpd/ax.c

415

u8, rawlen);

usr.sbin/snmpd/ax.c

419

u8 += nread;