lib/libcrypto/asn1/t_x509.c

185

uint64_t u64;

lib/libcrypto/asn1/t_x509.c

187

if (ASN1_INTEGER_get_uint64(&u64, bs) && u64 <= LONG_MAX)

lib/libcrypto/asn1/t_x509.c

188

l = (long)u64;

lib/libcrypto/x509/x509_policy.c

703

uint64_t u64;

lib/libcrypto/x509/x509_policy.c

704

if (ASN1_INTEGER_get_uint64(&u64, skip_certs) && u64 < *value)

lib/libcrypto/x509/x509_policy.c

705

*value = (size_t)u64;

lib/libexpat/lib/siphash.h

158

sip_tobin(void *dst, uint64_t u64) {

lib/libexpat/lib/siphash.h

159

SIP_U64TO8_LE((unsigned char *)dst, u64);

regress/lib/libssl/bytestring/bytestringtest.c

73

uint64_t u64;

regress/lib/libssl/bytestring/bytestringtest.c

86

CHECK(CBS_get_u64(&data, &u64));

regress/lib/libssl/bytestring/bytestringtest.c

87

CHECK(u64 == 0x0b0c0d0e0f101112ULL);

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

35

uint64_t u64;

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

43

ASSERT_INT_EQ(sshbuf_get_u64(p1, &u64), 0);

regress/usr.sbin/snmpd/agentx.c

2996

uint64_t u64;

sys/arch/amd64/amd64/cpu.c

1369

uint64_t u64;

sys/arch/amd64/amd64/cpu.c

1380

: "=r" (r.u64), "=qm" (valid) );

sys/arch/amd64/amd64/cpu.c

1385

: "=r" (r.u64), "=qm" (valid) );

sys/arch/amd64/amd64/cpu.c

1387

t.u64 = tsc;

sys/arch/amd64/amd64/cpu.c

1388

t.u64 ^= r.u64;

sys/arch/amd64/amd64/cpu.c

1389

t.u64 ^= valid; /* potential rdrand empty */

sys/arch/amd64/amd64/cpu.c

1391

t.u64 += rdtsc(); /* potential vmexit latency */

sys/arch/octeon/dev/cn30xxfpareg.h

291

uint64_t u64;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1116

u64 fence_context;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1130

u64 cg_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1414

u64 reg_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1422

u64 reg_addr, u32 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1434

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1436

u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1437

u64 reg_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1441

u32 reg_addr, u64 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1443

u64 reg_addr, u64 reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1608

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1609

u64 num_vis_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1732

int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1733

u64 *tmr_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1744

u64 *tmr_offset, u64 *tmr_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

200

extern u64 amdgpu_cg_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

378

u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

707

u64 (*encode_ext_smn_addressing)(int ext_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

731

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

116

u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

139

u64 ipid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

296

enum aca_error_type type, u64 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

509

u64 count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

821

u64 ipid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

885

static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

129

u64 regs[ACA_MAX_REGS_COUNT];

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

152

u64 count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.h

231

enum aca_error_type type, u64 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_acp.c

228

u64 acp_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1168

int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

1169

u64 *tmr_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

926

u64 pxm;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

790

u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

793

u64 tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

189

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

357

u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

63

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1706

u64 alloc_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

313

u64 size = amdgpu_bo_size(bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

583

(u64)ttm->num_pages << PAGE_SHIFT,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1671

u64 start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1672

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

446

static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

454

static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

457

u64 p;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

489

u64 pos, wptr_old, rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

544

static u64 amdgpu_cper_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

549

static u64 amdgpu_cper_ring_get_wptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

457

uint32_t handle, u64 point,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

458

u64 flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

664

static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

675

static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

697

u64 *max_bytes,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

698

u64 *max_vis_bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

701

u64 free_vram, total_vram, used_vram;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

763

u64 total_vis_vram = adev->gmc.visible_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

764

u64 used_vis_vram =

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

768

u64 free_vis_vram = total_vis_vram - used_vis_vram;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

791

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

792

u64 num_vis_bytes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.h

46

u64 point;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1350

u64 value = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1356

r = put_user(value, (u64 *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1710

static int amdgpu_debugfs_evict_vram(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1731

static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1751

static int amdgpu_debugfs_benchmark(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1912

static int amdgpu_debugfs_ib_preempt(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1987

static int amdgpu_debugfs_sclk_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1039

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1045

u64 r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1061

r |= ((u64)readl(pcie_data_offset) << 32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1067

u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1068

u64 reg_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1075

u64 r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1104

r |= ((u64)readl(pcie_data_offset) << 32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1147

u64 reg_addr, u32 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1195

u32 reg_addr, u64 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1222

u64 reg_addr, u64 reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2393

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

6311

u64 expires;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7898

u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

980

u64 reg_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

44

u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1706

u64 mall_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

246

u64 tmr_offset, tmr_size, pos;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

204

u64 tiling_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

716

*offset = ((u64)metadata[9] << 16u) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

720

*offset = ((u64)metadata[9] << 8u) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

721

((u64)(metadata[7] & 0x1FE0000u) << 23);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

729

u64 modifier = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

869

u64 render_dcc_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

948

u64 micro_tile_mode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

353

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

354

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

103

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

80

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

180

u64 amdgpu_cg_mask = 0xffffffffffffffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_eviction_fence.h

36

u64 ev_fence_ctx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

1035

static int gpu_recover_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

384

u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

811

u64 start_wptr, u64 end_wptr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

828

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gart.c

313

u64 page_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

1359

u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

1375

args->size = (u64)args->pitch * args->height;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

245

u64 flags, enum ttm_bo_type type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.h

46

u64 flags, enum ttm_bo_type type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2365

static int amdgpu_debugfs_gfx_sched_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2369

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2391

static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2395

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2435

static int amdgpu_debugfs_compute_sched_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2439

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2462

static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

2466

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

897

int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

104

u64 hpd_eop_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

106

u64 mec_fw_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

108

u64 mec_fw_data_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

137

u64 gpu_addr, u64 seq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

140

u64 addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

141

u64 seq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

158

u64 eop_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

515

u64 cleaner_shader_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

522

u64 userq_sch_req_count[MAX_XCP];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

607

int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfxhub.h

27

u64 (*get_fb_location)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfxhub.h

28

u64 (*get_mc_fb_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1085

u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1086

u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1087

u64 vram_addr, vram_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1088

u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1664

((u64)size << AMDGPU_GPU_PAGE_SHIFT);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1677

((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

214

u64 base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

257

u64 hive_vram_start = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

258

u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

296

u64 size_af, size_bf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

298

u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

349

u64 size_af, size_bf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

41

static const u64 four_gb = 0x100000000ULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

60

u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

159

u64 *dst, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

221

u64 mc_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

222

u64 visible_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

233

u64 agp_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

234

u64 agp_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

235

u64 agp_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

244

u64 gart_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

245

u64 gart_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

246

u64 gart_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

257

u64 vram_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

258

u64 vram_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

265

u64 fb_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

266

u64 fb_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

268

u64 real_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

270

u64 mc_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

280

u64 shared_aperture_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

281

u64 shared_aperture_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

282

u64 private_aperture_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

283

u64 private_aperture_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

318

u64 mall_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

324

u64 VM_L2_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

325

u64 VM_L2_CNTL2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

326

u64 VM_DUMMY_PAGE_FAULT_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

327

u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

328

u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

329

u64 VM_L2_PROTECTION_FAULT_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

330

u64 VM_L2_PROTECTION_FAULT_CNTL2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

331

u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

332

u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

333

u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

334

u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

335

u64 VM_DEBUG;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

336

u64 VM_L2_MM_GROUP_RT_CLASSES;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

337

u64 VM_L2_BANK_SELECT_RESERVED_CID;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

338

u64 VM_L2_BANK_SELECT_RESERVED_CID2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

339

u64 VM_L2_CACHE_PARITY_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

340

u64 VM_L2_IH_LOG_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

341

u64 VM_CONTEXT_CNTL[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

342

u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

343

u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

344

u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

345

u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

346

u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

347

u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

348

u64 MC_VM_MX_L1_TLB_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

350

u64 noretry_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

411

u64 base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_hdp.h

36

void (*get_clock_gating_state)(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

138

u64 shadow_va, csa_va, gds_va;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

241

u64 fence_context = adev->vm_manager.fence_context + ring->idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

305

entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

330

return dw1 | ((u64)(dw2 & 0xffff) << 32);

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

173

void **buf_obj, u64 *buf_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

180

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

250

int isp_kernel_buffer_alloc(struct device *dev, u64 size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

251

void **buf_obj, u64 *gpu_addr, void **cpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_isp.c

313

void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

186

u64 drm_client_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.c

211

struct amdgpu_job **job, u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

111

u64 drm_client_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

116

u64 k_job_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

358

static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

362

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

386

static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

390

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1268

min_t(u64, size, sizeof(ras_mask))) ?

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

280

u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

516

static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

333

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

414

u64 gpu_addr, u64 seq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

52

u64 (*get_fb_location)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

53

u64 (*get_mc_fb_offset)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

61

void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

279

int crtc_id, u64 crtc_base, bool async);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.c

49

u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

105

u64 (*get_pcie_replay_count)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

120

u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_nbio.h

90

u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1141

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

115

u64 flags = abo->flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1164

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1489

u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1508

u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1528

u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1624

u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1631

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

249

u64 *gpu_addr, void **cpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

348

u64 *gpu_addr, void **cpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

385

u64 *gpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

511

void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

588

bool amdgpu_bo_support_uswc(u64 bo_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

110

u64 flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

131

u64 tiling_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

132

u64 metadata_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

228

static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

261

u64 *gpu_addr, void **cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

265

u64 *gpu_addr, void **cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

269

u64 *gpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

279

void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

291

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

292

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

309

u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

310

u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

311

u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

352

u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

356

bool amdgpu_bo_support_uswc(u64 bo_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

54

u64 flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pmu.c

273

u64 count, prev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

265

u64 train_data_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

274

u64 p2c_train_data_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

277

u64 c2p_train_data_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1135

u64 event_id = qctx->evid.event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1223

u64 event_id = qctx->evid.event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1303

u64 event_id = qctx->evid.event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2290

u64 event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2341

u64 event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

300

s = min_t(u64, s, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3308

u64 val = adev->gmc.mc_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

334

ssize_t s = min_t(u64, 64, size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

341

u64 address, value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3446

u64 de_queried_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3447

u64 consumption_q_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4664

u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4667

u64 id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4696

u64 event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5252

u64 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5274

u64 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5296

u64 count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5324

u64 reg_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5396

u64 reg_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5443

void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

1013

void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

448

u64 last_seqno;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

459

u64 event_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

608

u64 ce_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

609

u64 ue_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

610

u64 de_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

975

u64 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

978

u64 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

981

u64 count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

997

u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

627

static int amdgpu_debugfs_ring_error(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

121

u64 signalled_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

147

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

149

u64 context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

182

u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

228

u64 (*get_rptr)(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

229

u64 (*get_wptr)(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

271

void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

272

u64 gds_va, bool init_shadow, int vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

311

u64 rptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

320

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

328

u64 wptr_old;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

384

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

394

u64 fence_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

400

u64 trail_fence_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

403

u64 cond_exe_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

407

u64 set_q_mode_token;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

229

void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

269

u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

298

u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

301

u64 readp, offset, start, end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

332

u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

341

u64 amdgpu_sw_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

509

struct amdgpu_ring *ring, u64 offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

53

u64 s_start, u64 s_end)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

55

u64 start, end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

100

u64 de_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

101

u64 ce_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

108

void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

109

u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

110

u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

114

u64 offset, enum amdgpu_ring_mux_offset_type type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

117

u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

118

u64 amdgpu_sw_ring_get_wptr_gfx(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

45

u64 start_ptr_in_hw_ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

46

u64 end_ptr_in_hw_ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

47

u64 sw_cptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

48

u64 sw_rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

49

u64 sw_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

78

u64 wptr_resubmit;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

97

u64 start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

98

u64 end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

99

u64 cntl_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

340

u64 rlc_autoload_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

351

static int amdgpu_debugfs_sdma_sched_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

354

u64 i, num_ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

355

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

398

static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

401

u64 i, num_ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

402

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

173

int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va,

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

174

u64 *gpu_addr, u64 **cpu_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

184

*va = bit_pos * sizeof(u64) + amdgpu_seq64_get_va_base(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

187

*gpu_addr = bit_pos * sizeof(u64) + adev->seq64.gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

202

void amdgpu_seq64_free(struct amdgpu_device *adev, u64 va)

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

206

bit_pos = (va - amdgpu_seq64_get_va_base(adev)) / sizeof(u64);

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

46

static inline u64 amdgpu_seq64_get_va_base(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

48

u64 addr = AMDGPU_VA_RESERVED_SEQ64_START(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.c

72

u64 seq64_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

30

#define AMDGPU_MAX_SEQ64_SLOTS (AMDGPU_VA_RESERVED_SEQ64_SIZE / sizeof(u64))

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

35

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

36

u64 *cpu_base_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

42

int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 *gpu_addr, u64 **cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_seq64.h

43

void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

42

void (*get_clock_gating_state)(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_smuio.h

47

u64 (*get_gpu_clock_counter)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

171

__field(u64, context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

172

__field(u64, seqno)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

195

__field(u64, context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

196

__field(u64, seqno)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

224

__field(u64, pd_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

249

__field(u64, offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

250

__field(u64, flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

273

__field(u64, offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

274

__field(u64, flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

293

__field(u64, soffset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

294

__field(u64, eoffset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

295

__field(u64, flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

330

__field(u64, start)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

331

__field(u64, end)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

332

__field(u64, flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

334

__field(u64, incr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

336

__field(u64, vm_ctx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

337

__dynamic_array(u64, dst, nptes)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

351

u64 addr = p->pages_addr ? amdgpu_vm_map_gart(

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

354

((u64 *)__get_dynamic_array(dst))[i] = addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

370

__field(u64, pe)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

371

__field(u64, addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

374

__field(u64, flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

395

__field(u64, pe)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

396

__field(u64, src)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

420

__field(u64, pd_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

478

__field(u64, seqno)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

494

__field(u64, bo_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

512

__field(u64, total_bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

513

__field(u64, total_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

529

__field(u64, bo_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

551

__field(u64, ctx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

552

__field(u64, seqno)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1047

gtt->offset = (u64)tmp->start << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1732

u64 vram_size = adev->gmc.visible_vram_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

220

*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2319

bool delayed, u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2406

u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2457

u64 addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2473

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2510

u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

655

amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

693

u64 offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

828

(u64)ttm->num_pages << PAGE_SHIFT,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

998

gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

100

u64 drv_vram_usage_start_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

101

u64 drv_vram_usage_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

145

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

148

u64 offset, u64 size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

188

u64 k_job_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

94

u64 fw_vram_usage_start_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

95

u64 fw_vram_usage_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

77

static u64 umsch_mm_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

85

static u64 umsch_mm_ring_get_wptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

341

db_size = sizeof(u64);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

48

struct amdgpu_bo_va_mapping *va_map, u64 addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

66

u64 addr, u64 expected_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

70

u64 user_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

71

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

148

u64 addr, u64 expected_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

51

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

106

memset(fence_drv->cpu_addr, 0, sizeof(u64));

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

173

u64 rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

258

u64 seq, struct dma_fence **f)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

338

u64 rptr, wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

391

u64 *wptr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

395

u64 addr, *ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

471

u64 wptr = fence->base.seqno;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

497

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

76

static u64 amdgpu_userq_fence_read(struct amdgpu_userq_fence_driver *fence_drv)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

83

u64 seq)

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.h

47

u64 va;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.h

48

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.h

49

u64 *cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.h

50

u64 context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

559

static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1088

void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.h

69

void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1398

static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1402

u64 mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1423

static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1427

u64 mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

620

u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1539

int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

101

int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

122

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

123

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

472

int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

99

int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3128

u64 total_idle = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3129

u64 total_evicted = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3130

u64 total_relocated = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3131

u64 total_moved = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3132

u64 total_invalidated = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3133

u64 total_done = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

619

uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

311

struct amdgpu_sync *sync, u64 k_job_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

431

DECLARE_KFIFO(faults, u64, 128);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

467

u64 fence_context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

476

u64 vram_base_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_cpu.c

50

u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

43

unsigned int count, u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

78

struct amdgpu_sync *sync, u64 k_job_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

260

static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

263

u64 start = amdgpu_vram_mgr_block_start(block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

264

u64 end = start + amdgpu_vram_mgr_block_size(block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

281

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

287

u64 usage = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

37

u64 start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

38

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

411

u64 start, size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

453

u64 vis_usage = 0, max_bytes, min_block_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

455

u64 size, remaining_size, lpfn, fpfn;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

462

lpfn = (u64)place->lpfn << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

466

fpfn = (u64)place->fpfn << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

516

remaining_size = (u64)vres->base.size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

521

remaining_size = (u64)dcc_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

529

min_block_size = (u64)tbo->page_alignment << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

537

else if ((size >= (u64)pages_per_block << PAGE_SHIFT) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

538

!(size & (((u64)pages_per_block << PAGE_SHIFT) - 1)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

539

min_block_size = (u64)pages_per_block << PAGE_SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

581

u64 trim_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

588

trim_start = (u64)dcc_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

590

(u64)vres->base.size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

596

size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks),

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

64

u64 start, size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

687

u64 offset, u64 length,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

82

static inline u64 amdgpu_vram_mgr_blocks_size(struct list_head *head)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.c

85

u64 size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

37

u64 default_page_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

47

u64 start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

48

u64 size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

60

static inline u64 amdgpu_vram_mgr_block_start(struct drm_buddy_block *block)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

65

static inline u64 amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vram_mgr.h

67

return (u64)PAGE_SIZE << drm_buddy_block_order(block);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1201

u64 status, count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

121

static const u64 xgmi_v6_4_0_mca_base_array[] = {

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1334

static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1518

static enum aca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1543

u64 mca_base, struct ras_err_data *err_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1546

u64 status = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

320

u64 addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

80

u64 node_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

81

u64 hive_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

83

u64 node_segment_size;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

69

u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id)

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

71

u64 ext_offset;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

78

ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34);

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

90

void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.h

28

void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

96

void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.h

28

void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

88

void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.h

28

void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

127

void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.h

28

void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

110

void athub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.h

28

void athub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags);

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

278

static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

607

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

659

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1038

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1040

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

235

int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

921

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

202

int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

774

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

896

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

898

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

186

int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

874

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

991

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

993

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

104

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

337

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3710

u64 shader_mc_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3769

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3795

u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3796

u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6504

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8498

static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8542

static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8548

static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8551

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8558

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8581

static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8587

static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8589

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8713

static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8714

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8781

static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8782

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9521

u64 addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

350

u64 shader_mc_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3718

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

413

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

445

u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

446

u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5718

static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5759

static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5765

static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5768

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5775

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5798

static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5804

static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5806

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5928

static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5929

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6002

static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6003

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6067

u64 shadow_va, u64 csa_va,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6068

u64 gds_va, bool init_shadow,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2714

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

352

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

384

u64 addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4273

static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4314

static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4320

static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4323

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4330

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4353

static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4359

static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4361

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4456

static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4457

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4522

static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4523

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1825

static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1826

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2075

u64 rptr_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2123

static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2128

static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2172

u64 rptr_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2359

u64 reg_list_mc_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2121

static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2122

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2168

u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2541

u64 rb_addr, rptr_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2595

static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2600

static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2615

static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2772

u64 eop_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2828

u64 hqd_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2829

u64 wb_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2971

u64 mqd_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1482

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1534

gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1560

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

1586

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4232

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5399

static void gfx_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5969

static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5974

static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6109

static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6110

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6191

static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6206

u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6226

static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6227

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1011

u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1012

u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3393

u64 rb_addr, rptr_addr, wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4627

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4696

gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4724

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4752

gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5299

static void gfx_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5343

static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5348

static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5351

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5358

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5543

static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5544

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5608

static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5613

static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5615

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5638

static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5639

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

916

static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

931

u64 shader_mc_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

984

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

351

u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

356

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

388

gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

179

u64 shader_mc_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

233

u64 gpu_addr, u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

259

u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

260

u64 seq)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2787

static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2884

static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2885

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2935

static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2940

static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2942

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2965

static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2966

u64 seq, unsigned int flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

858

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

109

static u64 gfxhub_v11_5_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

111

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

119

static u64 gfxhub_v11_5_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

121

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

181

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

111

static u64 gfxhub_v12_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

113

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

121

static u64 gfxhub_v12_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

123

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

185

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

135

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

34

static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

36

return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

50

u64 seg_size;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

174

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

37

static u64 gfxhub_v1_2_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

599

u64 seg_size;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

105

static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

107

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

115

static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

117

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

179

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

108

static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

110

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

118

static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

120

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

183

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

104

static u64 gfxhub_v3_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

106

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

114

static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

116

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

177

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

107

static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

109

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

117

static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

119

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

182

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

110

u64 addr;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

1109

static void gmc_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

112

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

113

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

668

u64 base = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

738

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

1045

static void gmc_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

109

u64 addr;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

111

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

112

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

668

u64 base = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

728

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

100

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

1032

static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

682

u64 base = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

741

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

97

u64 addr;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

99

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

210

u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

345

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

880

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1059

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

1274

((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

241

u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

389

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

414

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1174

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1452

((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1690

static void gmc_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

414

u64 base = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

580

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

605

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1680

u64 base = adev->mmhub.funcs->get_fb_location(adev);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1782

adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2354

static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

555

u64 addr;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

562

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

563

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

121

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

175

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

171

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

126

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

114

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

774

static void ih_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

751

static void ih_v6_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

741

static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_0.c

46

u64 isp_base;

sys/dev/pci/drm/amd/amdgpu/isp_v4_1_1.c

192

u64 isp_base;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

223

static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

503

void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

50

void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1386

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

782

void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

62

void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

1000

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

425

u64 fence_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

427

u64 *fence_ptr;

sys/dev/pci/drm/amd/amdgpu/mes_userqueue.c

437

fence_ptr = (u64 *)&adev->wb.wb[fence_offset];

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

177

u64 status_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

179

u64 *status_ptr;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

198

status_ptr = (u64 *)&adev->wb.wb[status_offset];

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

85

static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

90

static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

92

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

162

u64 status_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

164

u64 *status_ptr;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

183

status_ptr = (u64 *)&adev->wb.wb[status_offset];

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

66

static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

71

static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

73

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

129

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

37

static u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

39

u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

40

u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

601

static void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

147

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

37

static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

39

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

40

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

570

static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

184

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

38

static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

40

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

41

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

623

static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

779

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

250

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

675

static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

178

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

584

static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

203

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

526

static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

528

u64 base;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

538

static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

540

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

637

static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

209

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

509

static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

511

u64 base;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

520

static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

522

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

570

static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

195

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

515

static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

517

u64 base;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

526

static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

528

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

556

static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

301

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

651

static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

653

u64 base;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

662

static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

664

u64 offset;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

718

static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

196

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

520

static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

522

u64 base;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

532

static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

534

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

618

static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

161

(u32)((u64)adev->dummy_page_addr >> 44));

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

39

static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

42

u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

43

u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

689

static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

547

static int xgpu_nv_req_ras_cper_dump(struct amdgpu_device *adev, u64 vf_rptr)

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

562

static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

685

static void navi10_ih_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

256

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

281

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

288

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

212

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

207

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

348

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

308

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

275

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

317

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

318

u64 *flags)

sys/dev/pci/drm/amd/amdgpu/nv.c

1081

static void nv_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

307

static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

538

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

591

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1517

static void sdma_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

483

static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

644

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

812

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

865

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1095

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1180

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1470

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1524

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2169

u64 addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2177

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2178

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2334

static void sdma_v4_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

655

u64 *rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

658

rptr = ((u64 *)ring->rptr_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

674

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

678

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

704

u64 *wb = (u64 *)ring->wptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

743

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

747

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

769

u64 *wb = (u64 *)ring->wptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

886

static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1066

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1120

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1865

u64 addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1873

addr = (u64)entry->src_data[0] << 12;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1874

addr |= ((u64)entry->src_data[1] & 0xf) << 44;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2031

static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

222

u64 rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

225

rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

241

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

245

wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2532

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

271

u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

310

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

314

wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

336

u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

454

static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

693

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

694

u64 rwptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

799

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

800

u64 rwptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1019

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1082

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1631

u64 sdma_gfx_preempt;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1853

static void sdma_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

329

u64 *rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

332

rptr = (u64 *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

348

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

352

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

523

static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

697

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1542

u64 sdma_gfx_preempt;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

169

u64 *rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

172

rptr = (u64 *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1825

static void sdma_v5_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

188

u64 wptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

192

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

373

static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

546

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

919

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

982

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1526

u64 sdma_gfx_preempt;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1681

static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

170

u64 *rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

173

rptr = (u64 *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

188

u64 wptr = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

192

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

355

static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

490

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

925

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

988

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1005

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1482

u64 sdma_gfx_preempt;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1614

static void sdma_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

170

u64 *rptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

173

rptr = (u64 *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

188

u64 wptr = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

192

wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

359

static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

483

u64 wptr_gpu_addr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

942

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

107

static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/si_dma.c

215

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

266

u64 gpu_addr;

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

62

static void smuio_v11_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

59

static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

61

static void smuio_v13_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

39

static u64 smuio_v14_0_2_get_gpu_clock_counter(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

41

u64 clock;

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

42

u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

45

clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

46

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

48

clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

50

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

59

static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/soc15.c

1469

static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/soc15.h

121

u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);

sys/dev/pci/drm/amd/amdgpu/soc21.c

1005

static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/soc24.c

577

static void soc24_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

463

u64 status, count;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

110

static void uvd_v3_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

477

static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

492

static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

840

static void uvd_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1503

static void uvd_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

925

static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

957

static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

958

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1181

static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1222

static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1223

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

831

static void vce_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

724

static void vce_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

725

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

27

void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

28

u64 seq, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

32

void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

33

u64 seq, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1552

static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1730

static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1731

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2111

((u64)msg_hi) << 32 | msg_lo);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1535

void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1722

void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1723

u64 seq, unsigned flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

30

extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

43

extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

44

u64 seq, unsigned flags);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2012

((u64)msg_hi) << 32 | msg_lo);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1945

addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2005

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1630

u64 misc0;

sys/dev/pci/drm/amd/amdgpu/vi.c

1996

static void vi_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2302

u64 offset;

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

198

void write_kernel_doorbell64(void __iomem *db, u64 value)

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

203

writeq(value, (u64 __iomem *)db);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

909

size = sizeof(u64);

sys/dev/pci/drm/amd/amdkfd/kfd_events.h

56

u64 event_age;

sys/dev/pci/drm/amd/amdkfd/kfd_flat_memory.c

312

#define SVM_USER_BASE (u64)(KFD_CWSR_TBA_TMA_SIZE + 2*PAGE_SIZE)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

151

u64 event_id;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

126

u64 *vram, u64 npages,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

130

const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

132

u64 gart_s, gart_d;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

134

u64 size;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

280

dma_addr_t *scratch, u64 ttm_res_offset)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

282

u64 npages = migrate->npages;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

286

u64 mpages = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

288

u64 *dst;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

289

u64 i, j;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

296

dst = (u64 *)(scratch + npages);

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

389

struct vm_area_struct *vma, u64 start,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

390

u64 end, uint32_t trigger, u64 ttm_res_offset)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

393

u64 npages = (end - start) >> PAGE_SHIFT;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

412

2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t),

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

42

static u64

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

43

svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

49

svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

494

u64 ttm_res_offset;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

50

dma_addr_t *addr, u64 *gart_addr, u64 flags)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

56

u64 src_addr, dst_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

57

u64 pte_flags;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

584

dma_addr_t *scratch, u64 npages)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

587

u64 *src;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

590

u64 i = 0, j;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

591

u64 addr;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

599

src = (u64 *)(scratch + npages);

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

687

struct vm_area_struct *vma, u64 start, u64 end,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

691

u64 npages = (end - start) >> PAGE_SHIFT;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

713

2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t),

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1120

void write_kernel_doorbell64(void __iomem *db, u64 value);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1323

u64 expected_size);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

943

u64 signal_handle;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

151

static void kfd_queue_buffer_svm_put(struct kfd_process_device *pdd, u64 addr, u64 size)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

185

static int kfd_queue_buffer_svm_get(struct kfd_process_device *pdd, u64 addr, u64 size)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

190

static void kfd_queue_buffer_svm_put(struct kfd_process_device *pdd, u64 addr, u64 size)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

197

u64 expected_size)

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

200

u64 user_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

201

u64 size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

203

user_addr = (u64)addr >> AMDGPU_GPU_PAGE_SHIFT;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

236

u64 expected_queue_size;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

90

static int kfd_queue_buffer_svm_get(struct kfd_process_device *pdd, u64 addr, u64 size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11182

u64 num, den, res;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1472

u64 pt_base;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4969

static inline u32 scale_input_to_fw(int min, int max, u64 input)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4975

static inline u32 scale_fw_to_input(int min, int max, u64 input)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5055

return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5069

return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6039

const u64 tiling_flags,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8642

u64 target_vtotal, target_vtotal_diff;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8643

u64 num, den;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9126

offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9138

offdelay = DIV64_U64_ROUND_UP((u64)20 *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9645

const u64 current_ts)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9702

u64 timestamp_ns = ktime_get_ns();

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

256

u64 gpu_addr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

403

u64 dmub_bo_gpu_addr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3070

static int force_yuv420_output_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3082

static int force_yuv420_output_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3097

static int replay_get_state(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3113

static int replay_set_residency(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3127

static int replay_get_residency(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3134

*val = (u64)residency;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3142

static int psr_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3158

static int psr_read_residency(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3166

*val = (u64)residency;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3172

static int allow_edp_hotplug_detection_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3185

static int allow_edp_hotplug_detection_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3201

static int disallow_edp_enter_psr_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3205

*val = (u64) aconnector->disallow_edp_enter_psr;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3236

static int disallow_edp_enter_psr_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3244

static int dmub_trace_mask_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3249

u64 mask = 0xffff;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3287

static int dmub_trace_mask_show(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3293

u64 raw = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3294

u64 res = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3328

static int dmcub_trace_event_state_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3346

static int dmcub_trace_event_state_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3574

static int crc_win_x_start_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3591

static int crc_win_x_start_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3611

static int crc_win_y_start_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3628

static int crc_win_y_start_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3647

static int crc_win_x_end_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3664

static int crc_win_x_end_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3683

static int crc_win_y_end_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3700

static int crc_win_y_end_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3718

static int crc_win_update_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3749

static int crc_win_update_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3880

static int trigger_hpd_mst_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3938

static int trigger_hpd_mst_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3953

static int force_timing_sync_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3968

static int force_timing_sync_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3985

static int disable_hpd_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3999

static int disable_hpd_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4045

static int dp_force_sst_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4054

static int dp_force_sst_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4069

static int dp_ignore_cable_id_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4078

static int dp_ignore_cable_id_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4093

static int visual_confirm_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4106

static int visual_confirm_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4124

static int skip_detection_link_training_set(void *data, u64 val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4140

static int skip_detection_link_training_get(void *data, u64 *val)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

901

u64 peak_kbps = kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

969

u64 kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

977

kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

95

const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

61

const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

245

div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

819

timing.pix_clk_100hz * (u64)100),

sys/dev/pci/drm/amd/include/amd_shared.h

476

void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

924

int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4959

static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4971

u64 flags = 0;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

470

int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value);

sys/dev/pci/drm/amd/pm/inc/amdgpu_pm.h

28

u64 flag;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2355

u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2356

u64 prev_vddc = (u64)prev_std_vddc;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2357

u64 curr_vddc = (u64)curr_std_vddc;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2358

u64 pwr_efficiency_ratio, n, d;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2363

n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

2367

if (pwr_efficiency_ratio > (u64)0xFFFF)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5339

u64 tmp;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5352

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6543

u64 tmp64;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6557

tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6636

u64 tmp64;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6651

tmp64 = (u64)duty * 255;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6665

u64 tmp64;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

6681

tmp64 = (u64)speed * duty100;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

122

int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1761

int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3331

u64 ipid = entry->regs[MCA_REG_IDX_IPID];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3807

int idx, int reg_idx, u64 *val)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3820

*val = (u64)data[1] << 32 | data[0];

sys/dev/pci/drm/apple/afk.c

101

static void afk_getbuf(struct apple_dcp_afkep *ep, u64 message)

sys/dev/pci/drm/apple/afk.c

105

u64 reply;

sys/dev/pci/drm/apple/afk.c

131

static void afk_init_rxtx(struct apple_dcp_afkep *ep, u64 message,

sys/dev/pci/drm/apple/afk.c

15

u64 message;

sys/dev/pci/drm/apple/afk.c

48

static void afk_send(struct apple_dcp_afkep *ep, u64 message)

sys/dev/pci/drm/apple/afk.c

677

int afk_receive_message(struct apple_dcp_afkep *ep, u64 message)

sys/dev/pci/drm/apple/afk.h

182

int afk_receive_message(struct apple_dcp_afkep *ep, u64 message);

sys/dev/pci/drm/apple/apple_drv.c

156

u64 apple_format_modifiers[] = {

sys/dev/pci/drm/apple/apple_drv.c

415

u64 timeout;

sys/dev/pci/drm/apple/apple_drv.c

452

u64 jiffies = get_jiffies_64();

sys/dev/pci/drm/apple/apple_drv.c

453

u64 wait = time_after_eq64(jiffies, timeout) ?

sys/dev/pci/drm/apple/dcp-internal.h

57

u64 reg;

sys/dev/pci/drm/apple/dcp.c

113

static void dcp_recv_msg(void *cookie, u8 endpoint, u64 message)

sys/dev/pci/drm/apple/dcp.c

206

void dcp_send_message(struct apple_dcp *dcp, u8 endpoint, u64 message)

sys/dev/pci/drm/apple/dcp.c

406

int dcp_wait_ready(struct platform_device *pdev, u64 timeout)

sys/dev/pci/drm/apple/dcp.h

52

int dcp_wait_ready(struct platform_device *pdev, u64 timeout);

sys/dev/pci/drm/apple/dcp.h

66

void dcp_send_message(struct apple_dcp *dcp, u8 endpoint, u64 message);

sys/dev/pci/drm/apple/dcp.h

71

void iomfb_recv_msg(struct apple_dcp *dcp, u64 message);

sys/dev/pci/drm/apple/dcp_backlight.c

97

u64 low, high;

sys/dev/pci/drm/apple/dptxep.c

273

u64 lane_count = cpu_to_le64(request->lane_count);

sys/dev/pci/drm/apple/iomfb.c

314

static void dcpep_got_msg(struct apple_dcp *dcp, u64 message)

sys/dev/pci/drm/apple/iomfb.c

530

void iomfb_recv_msg(struct apple_dcp *dcp, u64 message)

sys/dev/pci/drm/apple/iomfb.c

63

static inline u64 dcpep_set_shmem(u64 dart_va)

sys/dev/pci/drm/apple/iomfb.c

70

static inline u64 dcpep_msg(enum dcp_context_id id, u32 length, u16 offset)

sys/dev/pci/drm/apple/iomfb.c

78

static inline u64 dcpep_ack(enum dcp_context_id id)

sys/dev/pci/drm/apple/iomfb.h

134

u64 unk1;

sys/dev/pci/drm/apple/iomfb.h

135

u64 unk2;

sys/dev/pci/drm/apple/iomfb.h

136

u64 unk3;

sys/dev/pci/drm/apple/iomfb.h

143

u64 unk1;

sys/dev/pci/drm/apple/iomfb.h

144

u64 unk2;

sys/dev/pci/drm/apple/iomfb.h

149

u64 unk1;

sys/dev/pci/drm/apple/iomfb.h

150

u64 reg_scratch;

sys/dev/pci/drm/apple/iomfb.h

151

u64 reg_doorbell;

sys/dev/pci/drm/apple/iomfb.h

220

u64 buffer;

sys/dev/pci/drm/apple/iomfb.h

228

u64 vaddr;

sys/dev/pci/drm/apple/iomfb.h

229

u64 dva;

sys/dev/pci/drm/apple/iomfb.h

234

u64 buffer;

sys/dev/pci/drm/apple/iomfb.h

235

u64 vaddr;

sys/dev/pci/drm/apple/iomfb.h

236

u64 dva;

sys/dev/pci/drm/apple/iomfb.h

243

u64 size;

sys/dev/pci/drm/apple/iomfb.h

252

u64 paddr;

sys/dev/pci/drm/apple/iomfb.h

253

u64 dva;

sys/dev/pci/drm/apple/iomfb.h

254

u64 dva_size;

sys/dev/pci/drm/apple/iomfb.h

259

u64 paddr;

sys/dev/pci/drm/apple/iomfb.h

260

u64 size;

sys/dev/pci/drm/apple/iomfb.h

268

u64 dva;

sys/dev/pci/drm/apple/iomfb.h

269

u64 dva_size;

sys/dev/pci/drm/apple/iomfb.h

290

u64 value;

sys/dev/pci/drm/apple/iomfb.h

296

u64 value;

sys/dev/pci/drm/apple/iomfb.h

304

u64 value;

sys/dev/pci/drm/apple/iomfb.h

316

u64 unklong;

sys/dev/pci/drm/apple/iomfb.h

388

u64 addr;

sys/dev/pci/drm/apple/iomfb.h

408

u64 r[3];

sys/dev/pci/drm/apple/iomfb.h

409

u64 g[3];

sys/dev/pci/drm/apple/iomfb.h

410

u64 b[3];

sys/dev/pci/drm/apple/iomfb.h

95

u64 handle;

sys/dev/pci/drm/apple/iomfb_template.c

1097

TRAMPOLINE_OUT(trampoline_get_frequency, dcpep_cb_get_frequency, u64);

sys/dev/pci/drm/apple/iomfb_template.c

1098

TRAMPOLINE_OUT(trampoline_get_time, dcpep_cb_get_time, u64);

sys/dev/pci/drm/apple/iomfb_template.c

1099

TRAMPOLINE_IN(trampoline_hotplug, dcpep_cb_hotplug, u64);

sys/dev/pci/drm/apple/iomfb_template.c

403

static bool is_disp_register(struct apple_dcp *dcp, u64 start, u64 end)

sys/dev/pci/drm/apple/iomfb_template.c

451

static u64 dcpep_cb_get_frequency(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

698

static u64 dcpep_cb_get_time(struct apple_dcp *dcp)

sys/dev/pci/drm/apple/iomfb_template.c

989

static void dcpep_cb_hotplug(struct apple_dcp *dcp, u64 *connected)

sys/dev/pci/drm/apple/iomfb_template.h

100

u64 surf2_iova[5];

sys/dev/pci/drm/apple/iomfb_template.h

103

u64 unkdouble;

sys/dev/pci/drm/apple/iomfb_template.h

105

u64 unkU64;

sys/dev/pci/drm/apple/iomfb_template.h

137

u64 swap_data;

sys/dev/pci/drm/apple/iomfb_template.h

165

u64 dva;

sys/dev/pci/drm/apple/iomfb_template.h

167

u64 addr;

sys/dev/pci/drm/apple/iomfb_template.h

168

u64 length;

sys/dev/pci/drm/apple/iomfb_template.h

19

u64 ts1;

sys/dev/pci/drm/apple/iomfb_template.h

20

u64 ts2;

sys/dev/pci/drm/apple/iomfb_template.h

21

u64 unk_10[6];

sys/dev/pci/drm/apple/iomfb_template.h

22

u64 flags1;

sys/dev/pci/drm/apple/iomfb_template.h

23

u64 flags2;

sys/dev/pci/drm/apple/iomfb_template.h

45

u64 bl_unk;

sys/dev/pci/drm/apple/iomfb_template.h

51

u64 unk_1;

sys/dev/pci/drm/apple/iomfb_template.h

74

u64 protection_opts;

sys/dev/pci/drm/apple/iomfb_template.h

77

u64 has_comp;

sys/dev/pci/drm/apple/iomfb_template.h

79

u64 has_planes;

sys/dev/pci/drm/apple/iomfb_template.h

81

u64 has_compr_info;

sys/dev/pci/drm/apple/iomfb_template.h

96

u64 surf_iova[SWAP_SURFACES];

sys/dev/pci/drm/apple/iomfb_template.h

98

u64 unk_u64_a[SWAP_SURFACES];

sys/dev/pci/drm/apple/parser.c

422

u64 clock = mul_u32_u32(pixels, vert->precise_sync_rate);

sys/dev/pci/drm/apple/parser.c

718

static int parse_sample_fmtbit(struct dcp_parse_ctx *handle, u64 *fmtbit)

sys/dev/pci/drm/apple/parser.h

111

u64 formats; /* SNDRV_PCM_FMTBIT_* */

sys/dev/pci/drm/apple/trace.h

101

__field(u64, message)),

sys/dev/pci/drm/apple/trace.h

254

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

258

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

270

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

274

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

287

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

293

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

310

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

314

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

354

TRACE_EVENT(dptxport_init, TP_PROTO(struct apple_dcp *dcp, u64 unit),

sys/dev/pci/drm/apple/trace.h

358

__field(u64, unit)),

sys/dev/pci/drm/apple/trace.h

429

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

433

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

498

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

508

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

534

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

543

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

564

TP_PROTO(struct apple_dcp *dcp, u32 rates, u64 formats, unsigned int nchans),

sys/dev/pci/drm/apple/trace.h

567

__field(u64, dcp)

sys/dev/pci/drm/apple/trace.h

569

__field(u64, formats)

sys/dev/pci/drm/apple/trace.h

573

__entry->dcp = (u64)dcp;

sys/dev/pci/drm/apple/trace.h

80

TP_PROTO(struct apple_dcp *dcp, u8 endpoint, u64 message),

sys/dev/pci/drm/apple/trace.h

85

__field(u64, message)),

sys/dev/pci/drm/apple/trace.h

96

TP_PROTO(struct apple_dcp *dcp, u8 endpoint, u64 message),

sys/dev/pci/drm/display/drm_dp_mst_topology.c

1635

u64 ts_nsec = entry->ts_nsec;

sys/dev/pci/drm/display/drm_hdcp_helper.c

21

drm_hdcp_update_content_protection(struct drm_connector *connector, u64 val)

sys/dev/pci/drm/display/drm_hdmi_audio_helper.c

160

u64 i2s_formats,

sys/dev/pci/drm/drm_atomic_state_helper.c

249

u64 val;

sys/dev/pci/drm/drm_atomic_uapi.c

1015

u64 prop_value,

sys/dev/pci/drm/drm_atomic_uapi.c

1019

u64 old_val;

sys/dev/pci/drm/drm_buddy.c

1006

u64 *start,

sys/dev/pci/drm/drm_buddy.c

1007

u64 new_size,

sys/dev/pci/drm/drm_buddy.c

1012

u64 block_start, block_end;

sys/dev/pci/drm/drm_buddy.c

1014

u64 new_start;

sys/dev/pci/drm/drm_buddy.c

1080

u64 start, u64 end,

sys/dev/pci/drm/drm_buddy.c

1114

u64 start, u64 end, u64 size,

sys/dev/pci/drm/drm_buddy.c

1115

u64 min_block_size,

sys/dev/pci/drm/drm_buddy.c

1120

u64 original_size, original_min_size;

sys/dev/pci/drm/drm_buddy.c

1237

u64 trim_size;

sys/dev/pci/drm/drm_buddy.c

1279

u64 start = drm_buddy_block_offset(block);

sys/dev/pci/drm/drm_buddy.c

1280

u64 size = drm_buddy_block_size(mm, block);

sys/dev/pci/drm/drm_buddy.c

1302

u64 count = 0, free;

sys/dev/pci/drm/drm_buddy.c

165

static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)

sys/dev/pci/drm/drm_buddy.c

170

static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)

sys/dev/pci/drm/drm_buddy.c

235

u64 start,

sys/dev/pci/drm/drm_buddy.c

236

u64 end,

sys/dev/pci/drm/drm_buddy.c

254

u64 block_start, block_end;

sys/dev/pci/drm/drm_buddy.c

308

int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size)

sys/dev/pci/drm/drm_buddy.c

31

u64 offset)

sys/dev/pci/drm/drm_buddy.c

311

u64 offset = 0;

sys/dev/pci/drm/drm_buddy.c

364

u64 root_size;

sys/dev/pci/drm/drm_buddy.c

408

u64 root_size, size, start;

sys/dev/pci/drm/drm_buddy.c

441

u64 offset = drm_buddy_block_offset(block);

sys/dev/pci/drm/drm_buddy.c

500

u64 root_size, size, start;

sys/dev/pci/drm/drm_buddy.c

612

u64 start, u64 end,

sys/dev/pci/drm/drm_buddy.c

617

u64 req_size = mm->chunk_size << order;

sys/dev/pci/drm/drm_buddy.c

630

u64 block_start;

sys/dev/pci/drm/drm_buddy.c

631

u64 block_end;

sys/dev/pci/drm/drm_buddy.c

654

u64 adjusted_start = max(block_start, start);

sys/dev/pci/drm/drm_buddy.c

655

u64 adjusted_end = min(block_end, end);

sys/dev/pci/drm/drm_buddy.c

704

u64 start, u64 end,

sys/dev/pci/drm/drm_buddy.c

814

u64 start, u64 size,

sys/dev/pci/drm/drm_buddy.c

816

u64 *total_allocated_on_err)

sys/dev/pci/drm/drm_buddy.c

820

u64 total_allocated = 0;

sys/dev/pci/drm/drm_buddy.c

822

u64 end;

sys/dev/pci/drm/drm_buddy.c

828

u64 block_start;

sys/dev/pci/drm/drm_buddy.c

829

u64 block_end;

sys/dev/pci/drm/drm_buddy.c

908

u64 start,

sys/dev/pci/drm/drm_buddy.c

909

u64 size,

sys/dev/pci/drm/drm_buddy.c

910

u64 *total_allocated_on_err,

sys/dev/pci/drm/drm_buddy.c

924

u64 size,

sys/dev/pci/drm/drm_buddy.c

925

u64 min_block_size,

sys/dev/pci/drm/drm_buddy.c

928

u64 rhs_offset, lhs_offset, lhs_size, filled;

sys/dev/pci/drm/drm_buddy.c

933

u64 modify_size;

sys/dev/pci/drm/drm_cache.c

209

return max_iomem > ((u64)1 << dma_bits);

sys/dev/pci/drm/drm_client_modeset.c

423

const u64 mask = BIT_ULL(connector_count) - 1;

sys/dev/pci/drm/drm_client_modeset.c

424

u64 conn_configured = 0;

sys/dev/pci/drm/drm_client_modeset.c

975

u64 valid_mask = 0;

sys/dev/pci/drm/drm_color_mgmt.c

136

u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n)

sys/dev/pci/drm/drm_color_mgmt.c

138

u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);

sys/dev/pci/drm/drm_crtc_internal.h

263

u64 prop_value, bool async_flip);

sys/dev/pci/drm/drm_debugfs.c

230

(u64)(uintptr_t)va->gem.obj, va->gem.offset);

sys/dev/pci/drm/drm_drv.c

1064

struct dmem_cgroup_region *drmm_cgroup_register_region(struct drm_device *dev, const char *region_name, u64 size)

sys/dev/pci/drm/drm_edid.c

5319

const struct cea_db *db, u64 *y420cmdb_map)

sys/dev/pci/drm/drm_edid.c

5324

u64 map = 0;

sys/dev/pci/drm/drm_edid.c

5348

map |= (u64)data[i] << (8 * i);

sys/dev/pci/drm/drm_edid.c

6090

static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)

sys/dev/pci/drm/drm_edid.c

6453

u64 y420cmdb_map = 0;

sys/dev/pci/drm/drm_file.c

888

u64 sz)

sys/dev/pci/drm/drm_format_helper.c

313

u64 val64 = ((u64)xfrm_pixel(pix[0])) |

sys/dev/pci/drm/drm_format_helper.c

314

((u64)xfrm_pixel(pix[1]) << 16) |

sys/dev/pci/drm/drm_format_helper.c

315

((u64)xfrm_pixel(pix[2]) << 32) |

sys/dev/pci/drm/drm_format_helper.c

316

((u64)xfrm_pixel(pix[3]) << 48);

sys/dev/pci/drm/drm_fourcc.c

429

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/drm_fourcc.c

519

return DIV_ROUND_UP_ULL((u64)buffer_width * info->char_per_block[plane],

sys/dev/pci/drm/drm_framebuffer.c

175

u64 min_pitch = drm_format_info_min_pitch(info, i, width);

sys/dev/pci/drm/drm_gem.c

581

u32 handle, u64 *offset)

sys/dev/pci/drm/drm_gpuvm.c

1003

u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

1071

u64 start_offset, u64 range,

sys/dev/pci/drm/drm_gpuvm.c

1072

u64 reserve_offset, u64 reserve_range,

sys/dev/pci/drm/drm_gpuvm.c

1283

u64 addr, u64 range, unsigned int num_fences)

sys/dev/pci/drm/drm_gpuvm.c

1286

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

1408

u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

1832

u64 addr = va->va.addr;

sys/dev/pci/drm/drm_gpuvm.c

1833

u64 range = va->va.range;

sys/dev/pci/drm/drm_gpuvm.c

1961

u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

1963

u64 last = addr + range - 1;

sys/dev/pci/drm/drm_gpuvm.c

1979

u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

2011

drm_gpuva_find_prev(struct drm_gpuvm *gpuvm, u64 start)

sys/dev/pci/drm/drm_gpuvm.c

2033

drm_gpuva_find_next(struct drm_gpuvm *gpuvm, u64 end)

sys/dev/pci/drm/drm_gpuvm.c

2052

drm_gpuvm_interval_empty(struct drm_gpuvm *gpuvm, u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

2184

u64 req_offset = req->map.gem.offset;

sys/dev/pci/drm/drm_gpuvm.c

2185

u64 req_range = req->map.va.range;

sys/dev/pci/drm/drm_gpuvm.c

2186

u64 req_addr = req->map.va.addr;

sys/dev/pci/drm/drm_gpuvm.c

2187

u64 req_end = req_addr + req_range;

sys/dev/pci/drm/drm_gpuvm.c

2195

u64 offset = va->gem.offset;

sys/dev/pci/drm/drm_gpuvm.c

2196

u64 addr = va->va.addr;

sys/dev/pci/drm/drm_gpuvm.c

2197

u64 range = va->va.range;

sys/dev/pci/drm/drm_gpuvm.c

2198

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

2243

u64 ls_range = req_addr - addr;

sys/dev/pci/drm/drm_gpuvm.c

2357

u64 req_addr, u64 req_range)

sys/dev/pci/drm/drm_gpuvm.c

2360

u64 req_end = req_addr + req_range;

sys/dev/pci/drm/drm_gpuvm.c

2370

u64 offset = va->gem.offset;

sys/dev/pci/drm/drm_gpuvm.c

2371

u64 addr = va->va.addr;

sys/dev/pci/drm/drm_gpuvm.c

2372

u64 range = va->va.range;

sys/dev/pci/drm/drm_gpuvm.c

2373

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

2485

u64 req_addr, u64 req_range)

sys/dev/pci/drm/drm_gpuvm.c

2611

u64 req_addr, u64 req_range)

sys/dev/pci/drm/drm_gpuvm.c

2846

u64 req_addr, u64 req_range)

sys/dev/pci/drm/drm_gpuvm.c

2897

u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

2902

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

946

INTERVAL_TREE_DEFINE(struct drm_gpuva, rb.node, u64, rb.__subtree_last,

sys/dev/pci/drm/drm_gpuvm.c

955

drm_gpuvm_check_overflow(u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

957

u64 end;

sys/dev/pci/drm/drm_gpuvm.c

963

drm_gpuvm_warn_check_overflow(struct drm_gpuvm *gpuvm, u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

970

drm_gpuvm_in_mm_range(struct drm_gpuvm *gpuvm, u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

972

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

973

u64 mm_start = gpuvm->mm_start;

sys/dev/pci/drm/drm_gpuvm.c

974

u64 mm_end = mm_start + gpuvm->mm_range;

sys/dev/pci/drm/drm_gpuvm.c

980

drm_gpuvm_in_kernel_node(struct drm_gpuvm *gpuvm, u64 addr, u64 range)

sys/dev/pci/drm/drm_gpuvm.c

982

u64 end = addr + range;

sys/dev/pci/drm/drm_gpuvm.c

983

u64 kstart = gpuvm->kernel_alloc_node.va.addr;

sys/dev/pci/drm/drm_gpuvm.c

984

u64 krange = gpuvm->kernel_alloc_node.va.range;

sys/dev/pci/drm/drm_gpuvm.c

985

u64 kend = kstart + krange;

sys/dev/pci/drm/drm_internal.h

106

u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe);

sys/dev/pci/drm/drm_internal.h

98

static inline bool drm_vblank_passed(u64 seq, u64 ref)

sys/dev/pci/drm/drm_ioc32.c

231

u64 data; /**< Pointer */

sys/dev/pci/drm/drm_ioc32.c

298

u64 modifier[4];

sys/dev/pci/drm/drm_linux.c

2306

dma_fence_array_create(int num_fences, struct dma_fence **fences, u64 context,

sys/dev/pci/drm/drm_mm.c

1000

u64 total_used = 0, total_free = 0, total = 0;

sys/dev/pci/drm/drm_mm.c

157

u64, __subtree_last,

sys/dev/pci/drm/drm_mm.c

184

__drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last)

sys/dev/pci/drm/drm_mm.c

245

u64 x = expr(node); \

sys/dev/pci/drm/drm_mm.c

260

static u64 rb_to_hole_size(struct rb_node *rb)

sys/dev/pci/drm/drm_mm.c

269

u64 x = node->hole_size;

sys/dev/pci/drm/drm_mm.c

322

static inline u64 rb_hole_size(struct rb_node *rb)

sys/dev/pci/drm/drm_mm.c

327

static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size)

sys/dev/pci/drm/drm_mm.c

347

static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr)

sys/dev/pci/drm/drm_mm.c

353

u64 hole_start;

sys/dev/pci/drm/drm_mm.c

371

u64 start, u64 end, u64 size,

sys/dev/pci/drm/drm_mm.c

431

u64 hole_start, hole_end;

sys/dev/pci/drm/drm_mm.c

432

u64 adj_start, adj_end;

sys/dev/pci/drm/drm_mm.c

433

u64 end;

sys/dev/pci/drm/drm_mm.c

471

static u64 rb_to_hole_size_or_zero(struct rb_node *rb)

sys/dev/pci/drm/drm_mm.c

494

u64 size, u64 alignment,

sys/dev/pci/drm/drm_mm.c

496

u64 range_start, u64 range_end,

sys/dev/pci/drm/drm_mm.c

500

u64 remainder_mask;

sys/dev/pci/drm/drm_mm.c

521

u64 hole_start = __drm_mm_hole_node_start(hole);

sys/dev/pci/drm/drm_mm.c

522

u64 hole_end = hole_start + hole->hole_size;

sys/dev/pci/drm/drm_mm.c

523

u64 adj_start, adj_end;

sys/dev/pci/drm/drm_mm.c

524

u64 col_start, col_end;

sys/dev/pci/drm/drm_mm.c

547

u64 rem;

sys/dev/pci/drm/drm_mm.c

716

u64 size,

sys/dev/pci/drm/drm_mm.c

717

u64 alignment,

sys/dev/pci/drm/drm_mm.c

719

u64 start,

sys/dev/pci/drm/drm_mm.c

720

u64 end,

sys/dev/pci/drm/drm_mm.c

763

u64 hole_start, hole_end;

sys/dev/pci/drm/drm_mm.c

764

u64 col_start, col_end;

sys/dev/pci/drm/drm_mm.c

765

u64 adj_start, adj_end;

sys/dev/pci/drm/drm_mm.c

799

u64 rem;

sys/dev/pci/drm/drm_mm.c

894

u64 hole_start, hole_end;

sys/dev/pci/drm/drm_mm.c

941

void drm_mm_init(struct drm_mm *mm, u64 start, u64 size)

sys/dev/pci/drm/drm_mm.c

979

static u64 drm_mm_dump_hole(struct drm_printer *p, const struct drm_mm_node *entry)

sys/dev/pci/drm/drm_mm.c

981

u64 start, size;

sys/dev/pci/drm/drm_modes.c

346

u64 result;

sys/dev/pci/drm/drm_modes.c

366

result = (u64)params->line_duration_ns * pixel_clock_hz;

sys/dev/pci/drm/drm_modes.c

642

u64 tmp;

sys/dev/pci/drm/drm_plane.c

202

u64 modifier))

sys/dev/pci/drm/drm_plane.c

917

u32 format, u64 modifier)

sys/dev/pci/drm/drm_plane.c

997

u32 format, u64 modifier)

sys/dev/pci/drm/drm_probe_helper.c

764

u64 old_epoch_counter;

sys/dev/pci/drm/drm_probe_helper.c

982

u64 old_epoch_counter;

sys/dev/pci/drm/drm_rect.c

57

u64 tmp;

sys/dev/pci/drm/drm_syncobj.c

1295

u64 timeout_ns, timeout_jiffies64;

sys/dev/pci/drm/drm_syncobj.c

224

u64 point;

sys/dev/pci/drm/drm_syncobj.c

236

u64 point;

sys/dev/pci/drm/drm_syncobj.c

443

u32 handle, u64 point, u64 flags,

sys/dev/pci/drm/drm_syncobj.c

448

u64 timeout = nsecs_to_jiffies64(DRM_SYNCOBJ_WAIT_FOR_SUBMIT_TIMEOUT);

sys/dev/pci/drm/drm_syncobj.c

765

int fd, int handle, u64 point)

sys/dev/pci/drm/drm_syncobj.c

796

int handle, u64 point, int *p_fd)

sys/dev/pci/drm/drm_syncobj.c

905

u64 point = 0;

sys/dev/pci/drm/drm_syncobj.c

937

u64 point = 0;

sys/dev/pci/drm/drm_vblank.c

1005

u64 vblank_start;

sys/dev/pci/drm/drm_vblank.c

1020

(u64)vblank->framedur_ns * mode->crtc_vblank_start,

sys/dev/pci/drm/drm_vblank.c

1030

u64 seq, ktime_t now)

sys/dev/pci/drm/drm_vblank.c

1131

u64 seq;

sys/dev/pci/drm/drm_vblank.c

1295

u64 last;

sys/dev/pci/drm/drm_vblank.c

1362

u64 seq;

sys/dev/pci/drm/drm_vblank.c

1560

u64 diff_ns;

sys/dev/pci/drm/drm_vblank.c

1624

u64 req_seq,

sys/dev/pci/drm/drm_vblank.c

1631

u64 seq;

sys/dev/pci/drm/drm_vblank.c

1723

static u64 widen_32_to_64(u32 narrow, u64 near)

sys/dev/pci/drm/drm_vblank.c

1757

u64 req_seq, seq;

sys/dev/pci/drm/drm_vblank.c

1898

u64 seq;

sys/dev/pci/drm/drm_vblank.c

2089

u64 seq;

sys/dev/pci/drm/drm_vblank.c

2090

u64 req_seq;

sys/dev/pci/drm/drm_vblank.c

318

u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));

sys/dev/pci/drm/drm_vblank.c

378

u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/pci/drm/drm_vblank.c

381

u64 count;

sys/dev/pci/drm/drm_vblank.c

411

u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc)

sys/dev/pci/drm/drm_vblank.c

415

u64 vblank;

sys/dev/pci/drm/drm_vblank.c

639

linedur_ns = div_u64((u64) mode->crtc_htotal * 1000000, dotclock);

sys/dev/pci/drm/drm_vblank.c

640

framedur_ns = div_u64((u64) frame_size * 1000000, dotclock);

sys/dev/pci/drm/drm_vblank.c

802

(u64)ts_etime.tv_sec, ts_etime.tv_nsec / 1000,

sys/dev/pci/drm/drm_vblank.c

803

(u64)ts_vblank_time.tv_sec, ts_vblank_time.tv_nsec / 1000,

sys/dev/pci/drm/drm_vblank.c

925

u64 drm_crtc_vblank_count(struct drm_crtc *crtc)

sys/dev/pci/drm/drm_vblank.c

945

static u64 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,

sys/dev/pci/drm/drm_vblank.c

949

u64 vblank_count;

sys/dev/pci/drm/drm_vblank.c

985

u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,

sys/dev/pci/drm/drm_vblank_work.c

114

u64 count, bool nextonmiss)

sys/dev/pci/drm/drm_vblank_work.c

118

u64 cur_vbl;

sys/dev/pci/drm/drm_vblank_work.c

53

u64 count = atomic64_read(&vblank->count);

sys/dev/pci/drm/i915/display/hsw_ips.c

297

static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)

sys/dev/pci/drm/i915/display/hsw_ips.c

307

static int hsw_ips_debugfs_false_color_set(void *data, u64 val)

sys/dev/pci/drm/i915/display/i9xx_plane.c

716

static bool i9xx_plane_can_async_flip(u64 modifier)

sys/dev/pci/drm/i915/display/i9xx_plane.c

74

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/i9xx_plane.c

757

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

769

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

784

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

799

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

810

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.c

92

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/i9xx_plane.c

934

const u64 *modifiers;

sys/dev/pci/drm/i915/display/i9xx_plane.h

21

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_plane.h

38

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/i9xx_wm.c

2747

u64 sskpd;

sys/dev/pci/drm/i915/display/i9xx_wm.c

488

u64 ret;

sys/dev/pci/drm/i915/display/intel_alpm.c

528

i915_edp_lobf_debug_get(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_alpm.c

539

i915_edp_lobf_debug_set(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_atomic.c

61

u64 *val)

sys/dev/pci/drm/i915/display/intel_atomic.c

93

u64 val)

sys/dev/pci/drm/i915/display/intel_atomic.h

26

u64 *val);

sys/dev/pci/drm/i915/display/intel_atomic.h

30

u64 val);

sys/dev/pci/drm/i915/display/intel_backlight.c

46

u64 target_val;

sys/dev/pci/drm/i915/display/intel_bo.c

44

int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, int size)

sys/dev/pci/drm/i915/display/intel_bo.h

21

int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, int size);

sys/dev/pci/drm/i915/display/intel_color.c

192

static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)

sys/dev/pci/drm/i915/display/intel_color.c

197

u64 user_coeff = input[i];

sys/dev/pci/drm/i915/display/intel_color.c

463

const u64 *input;

sys/dev/pci/drm/i915/display/intel_color.c

464

u64 temp[9];

sys/dev/pci/drm/i915/display/intel_color.c

483

u64 abs_coeff = ((1ULL << 63) - 1) & input[i];

sys/dev/pci/drm/i915/display/intel_color.c

599

static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)

sys/dev/pci/drm/i915/display/intel_crtc.c

589

u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time));

sys/dev/pci/drm/i915/display/intel_cursor.c

1007

u64 *modifiers;

sys/dev/pci/drm/i915/display/intel_cursor.c

185

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_cursor.c

346

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_cursor.c

780

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2250

u64 datarate;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2251

u64 mpll_tx_clk_div;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2252

u64 vco_freq_shift;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2253

u64 vco_freq;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2254

u64 multiplier;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2255

u64 mpll_multiplier;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2256

u64 mpll_fracn_quot;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2257

u64 mpll_fracn_rem;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2264

datarate = ((u64)crtc_state->port_clock * 1000) * 10;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2265

mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2266

vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));

sys/dev/pci/drm/i915/display/intel_ddi.c

3521

u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);

sys/dev/pci/drm/i915/display/intel_de.h

48

static inline u64

sys/dev/pci/drm/i915/display/intel_de.h

52

u64 val;

sys/dev/pci/drm/i915/display/intel_display.c

609

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_display.h

404

u32 pixel_format, u64 modifier);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

437

u64 count;

sys/dev/pci/drm/i915/display/intel_display_power_map.c

1812

u64 power_well_ids = 0;

sys/dev/pci/drm/i915/display/intel_display_types.h

1195

u64 rel_data_rate[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_display_types.h

1196

u64 rel_data_rate_y[I915_MAX_PLANES];

sys/dev/pci/drm/i915/display/intel_display_types.h

1330

u64 cmrr_n, cmrr_m;

sys/dev/pci/drm/i915/display/intel_display_types.h

1457

u64 min;

sys/dev/pci/drm/i915/display/intel_display_types.h

1458

u64 max;

sys/dev/pci/drm/i915/display/intel_display_types.h

1459

u64 sum;

sys/dev/pci/drm/i915/display/intel_display_types.h

1517

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_display_types.h

1519

bool (*can_async_flip)(u64 modifier);

sys/dev/pci/drm/i915/display/intel_display_types.h

453

u64 value;

sys/dev/pci/drm/i915/display/intel_display_types.h

708

u64 ccval;

sys/dev/pci/drm/i915/display/intel_dp.c

4897

as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1932

static int i915_dp_max_link_rate_show(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1951

static int i915_dp_max_lane_count_show(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1970

static int i915_dp_force_link_training_failure_show(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1988

static int i915_dp_force_link_training_failure_write(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2012

static int i915_dp_force_link_retrain_show(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

2030

static int i915_dp_force_link_retrain_write(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1306

u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

928

u64 m2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1500

u64 min_deviation; /* current minimal deviation */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1501

u64 central_freq; /* chosen central freq */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1502

u64 dco_freq; /* chosen dco freq */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1511

u64 central_freq,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1512

u64 dco_freq,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1515

u64 deviation;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1599

u64 afe_clock,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1601

u64 central_freq,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1604

u64 dco_freq;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1671

static const u64 dco_central_freq[3] = { 8400000000ULL,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1692

u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1698

u64 dco_freq = p * afe_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2602

dco = div_u64((u64)dco_freq << 15, ref_freq);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3016

u64 ssc_stepsize, ssc_steplen, ssc_steplog;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3017

u64 tmp;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3041

tmp = (u64)m2div_rem * (1 << 22);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3215

u64 tmp;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3275

tmp = (u64)m1 * m2_int * ref_clock +

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3276

(((u64)m1 * m2_frac * ref_clock) >> 22);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

873

static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

878

u64 a, b, c, d, diff, diff_best;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

937

u64 freq2k;

sys/dev/pci/drm/i915/display/intel_dpt.c

134

u64 pin_flags = 0;

sys/dev/pci/drm/i915/display/intel_dpt.c

321

u64 intel_dpt_offset(struct i915_vma *dpt_vma)

sys/dev/pci/drm/i915/display/intel_dpt.c

43

u64 offset,

sys/dev/pci/drm/i915/display/intel_dpt.c

77

u64 start, u64 length)

sys/dev/pci/drm/i915/display/intel_dpt.h

24

u64 intel_dpt_offset(struct i915_vma *dpt_vma);

sys/dev/pci/drm/i915/display/intel_drrs.c

352

static int intel_drrs_debugfs_ctl_set(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_dsb.c

443

u64 window = ((u64)upper << DSB_SCANLINE_UPPER_SHIFT) |

sys/dev/pci/drm/i915/display/intel_dsb.c

444

((u64)lower << DSB_SCANLINE_LOWER_SHIFT);

sys/dev/pci/drm/i915/display/intel_dsb.c

574

u64 head_tail;

sys/dev/pci/drm/i915/display/intel_dsb.c

603

head_tail = ((u64)(DSB_GOSUB_CONVERT_ADDR(head)) << DSB_GOSUB_HEAD_SHIFT) |

sys/dev/pci/drm/i915/display/intel_dsb.c

604

((u64)(DSB_GOSUB_CONVERT_ADDR(tail)) << DSB_GOSUB_TAIL_SHIFT);

sys/dev/pci/drm/i915/display/intel_fb.c

1978

u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

217

u64 modifier;

sys/dev/pci/drm/i915/display/intel_fb.c

363

static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

374

static const struct intel_modifier_desc *lookup_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

398

unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

435

intel_fb_get_format_info(u32 pixel_format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

462

bool intel_fb_is_tiled_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

476

bool intel_fb_is_ccs_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

489

bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

502

bool intel_fb_is_mc_ccs_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

515

bool intel_fb_needs_64k_phys(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

533

bool intel_fb_is_tile4_modifier(u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

586

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.c

589

u64 *list, *p;

sys/dev/pci/drm/i915/display/intel_fb.c

620

bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

652

u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.c

902

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier)

sys/dev/pci/drm/i915/display/intel_fb.h

120

bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

123

unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

35

bool intel_fb_is_tiled_modifier(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

36

bool intel_fb_is_ccs_modifier(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

37

bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

38

bool intel_fb_is_mc_ccs_modifier(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

39

bool intel_fb_needs_64k_phys(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

40

bool intel_fb_is_tile4_modifier(u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

45

u64 *intel_fb_plane_get_modifiers(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_fb.h

47

bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

50

intel_fb_get_format_info(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/i915/display/intel_fb.h

54

u64 modifier);

sys/dev/pci/drm/i915/display/intel_fbc.c

2189

static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_fbc.c

2198

static int intel_fbc_debugfs_false_color_set(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_fbc.c

382

range_end_overflows_t(u64, i915_gem_stolen_area_address(i915),

sys/dev/pci/drm/i915/display/intel_fbc.c

386

range_end_overflows_t(u64, i915_gem_stolen_area_address(i915),

sys/dev/pci/drm/i915/display/intel_fbc.c

790

static u64 intel_fbc_cfb_base_max(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

798

static u64 intel_fbc_stolen_end(struct intel_display *display)

sys/dev/pci/drm/i915/display/intel_fbc.c

801

u64 end;

sys/dev/pci/drm/i915/display/intel_fbc.c

839

u64 end = intel_fbc_stolen_end(display);

sys/dev/pci/drm/i915/display/intel_fixed.h

101

tmp = (u64)val << 16;

sys/dev/pci/drm/i915/display/intel_fixed.h

109

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

111

tmp = (u64)val << 16;

sys/dev/pci/drm/i915/display/intel_fixed.h

120

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

130

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

132

tmp = (u64)add1.val + add2.val;

sys/dev/pci/drm/i915/display/intel_fixed.h

141

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

143

tmp = (u64)add1.val + tmp_add2.val;

sys/dev/pci/drm/i915/display/intel_fixed.h

60

static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val)

sys/dev/pci/drm/i915/display/intel_fixed.h

77

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

89

u64 tmp;

sys/dev/pci/drm/i915/display/intel_fixed.h

99

u64 tmp;

sys/dev/pci/drm/i915/display/intel_hdcp.c

1091

u64 value, bool update_property)

sys/dev/pci/drm/i915/display/intel_hdcp.c

2695

u64 old_cp = old_state->content_protection;

sys/dev/pci/drm/i915/display/intel_hdcp.c

2696

u64 new_cp = new_state->content_protection;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

126

u64 addr_in, u64 addr_out,

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

179

u64 addr_in, addr_out, host_session_id;

sys/dev/pci/drm/i915/display/intel_hdcp_gsc.c

198

get_random_bytes(&host_session_id, sizeof(u64));

sys/dev/pci/drm/i915/display/intel_hotplug.c

314

u64 old_epoch_counter;

sys/dev/pci/drm/i915/display/intel_opregion.c

133

u64 fdss;

sys/dev/pci/drm/i915/display/intel_opregion.c

136

u64 rvda; /* Physical (2.0) or relative from opregion (2.1+)

sys/dev/pci/drm/i915/display/intel_plane.c

1354

static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width,

sys/dev/pci/drm/i915/display/intel_plane.c

182

u64 modifier)

sys/dev/pci/drm/i915/display/intel_plane.c

193

u64 modifier)

sys/dev/pci/drm/i915/display/intel_plane.h

25

u64 modifier);

sys/dev/pci/drm/i915/display/intel_plane.h

92

u64 modifier);

sys/dev/pci/drm/i915/display/intel_plane_initial.c

135

u64 pinctl;

sys/dev/pci/drm/i915/display/intel_psr.c

3243

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)

sys/dev/pci/drm/i915/display/intel_psr.c

4202

i915_edp_psr_debug_set(void *data, u64 val)

sys/dev/pci/drm/i915/display/intel_psr.c

4225

i915_edp_psr_debug_get(void *data, u64 *val)

sys/dev/pci/drm/i915/display/intel_psr.h

39

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);

sys/dev/pci/drm/i915/display/intel_sdvo.c

2376

u64 *val)

sys/dev/pci/drm/i915/display/intel_sdvo.c

2435

u64 val)

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

131

static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

135

const u64 curve_freq_hz[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

136

const u64 curve_0[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

137

const u64 curve_1[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

138

const u64 curve_2[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

142

u64 datarate = pixel_clock * 10000;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

150

u64 vco_clk;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

151

u64 vco_clk_do_div;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

219

void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock)

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

222

static const u64 dg2_curve_freq_hz[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

230

static const u64 dg2_curve_0[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

236

static const u64 dg2_curve_1[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

244

static const u64 dg2_curve_2[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

291

void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock)

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

294

static const u64 c10_curve_freq_hz[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

302

static const u64 c10_curve_0[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

307

static const u64 c10_curve_1[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

315

static const u64 c10_curve_2[2][8] = {

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

49

static void get_ana_cp_int_prop(u64 vco_clk,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

53

const u64 curve_freq_hz[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

54

const u64 curve_0[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

55

const u64 curve_1[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

56

const u64 curve_2[2][8],

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

60

u64 vco_div_refclk_float;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

61

u64 curve_0_interpolated;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

62

u64 curve_2_interpolated;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

63

u64 curve_1_interpolated;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

64

u64 curve_2_scaled1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

65

u64 curve_2_scaled2;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

66

u64 adjusted_vco_clk1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

67

u64 adjusted_vco_clk2;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

68

u64 curve_2_scaled_int;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

69

u64 interpolated_product;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

70

u64 scaled_interpolated_sqrt;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

71

u64 scaled_vco_div_refclk1;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

72

u64 scaled_vco_div_refclk2;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

73

u64 ana_cp_int_temp;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

74

u64 temp;

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.h

14

void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.h

15

void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock);

sys/dev/pci/drm/i915/display/intel_sprite.c

1489

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1510

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1536

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/intel_sprite.c

1599

const u64 *modifiers;

sys/dev/pci/drm/i915/display/intel_sprite.c

961

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_sprite.c

976

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/intel_vblank.c

80

u64 frame;

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

1098

u64 edp_vswing_preemph; /* 173+ */

sys/dev/pci/drm/i915/display/intel_vrr.c

210

u64 adjusted_pixel_rate;

sys/dev/pci/drm/i915/display/skl_scaler.c

158

u64 modifier, bool need_scaler)

sys/dev/pci/drm/i915/display/skl_scaler.c

84

u64 modifier, int *min_w, int *min_h)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1042

static u32 skl_plane_ctl_tiling(u64 fb_modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2494

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2548

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2602

u32 format, u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2820

const u64 *modifiers;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

475

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

491

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

504

u32 pixel_format, u64 modifier,

sys/dev/pci/drm/i915/display/skl_universal_plane.c

515

static bool tgl_plane_can_async_flip(u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

540

static bool icl_plane_can_async_flip(u64 modifier)

sys/dev/pci/drm/i915/display/skl_universal_plane.c

561

static bool skl_plane_can_async_flip(u64 modifier)

sys/dev/pci/drm/i915/display/skl_watermark.c

1284

static u64

sys/dev/pci/drm/i915/display/skl_watermark.c

1290

u64 data_rate = 0;

sys/dev/pci/drm/i915/display/skl_watermark.c

1379

u64 data_rate;

sys/dev/pci/drm/i915/display/skl_watermark.c

1387

u64 data_rate)

sys/dev/pci/drm/i915/display/skl_watermark.c

1664

u64 modifier, unsigned int rotation,

sys/dev/pci/drm/i915/display/skl_watermark.c

2199

u64 hscale_k, vscale_k;

sys/dev/pci/drm/i915/display/skl_watermark.c

2228

u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);

sys/dev/pci/drm/i915/display/skl_watermark.c

2229

u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);

sys/dev/pci/drm/i915/display/skl_watermark.c

595

u64 modifier, unsigned int rotation,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1005

intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

595

u64 flags;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

751

u64 extensions;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

159

__i915_gem_object_create_user(struct drm_i915_private *i915, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_create.c

74

u64 *size_p,

sys/dev/pci/drm/i915/gem/i915_gem_create.c

77

u64 size = obj->base.size;

sys/dev/pci/drm/i915/gem/i915_gem_create.c

91

__i915_gem_object_create_user_ext(struct drm_i915_private *i915, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1095

static u64

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1375

static u64

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1381

u64 target_addr = relocation_target(reloc, target);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1382

u64 offset = reloc->offset;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1407

static u64

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1554

u64 offset = eb_relocate_entry(eb, ev, r);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1604

u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

1677

min_t(u64, BIT_ULL(31), size - copied);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2371

u64 batch_len)

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

240

u64 value;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2793

u64 __user *user_values;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2795

u64 nfences;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2844

u64 point;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

296

u64 invalid_flags; /** Set of execobj.flags that are invalid */

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

299

u64 batch_len[MAX_ENGINE_INSTANCE + 1];

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3526

args->rsvd2 |= (u64)out_fence_fd << 32;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

382

const u64 start = i915_vma_offset(vma);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

383

const u64 size = i915_vma_size(vma);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

410

static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

413

u64 pin_flags = 0;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

442

u64 pin_flags;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

607

if (range_overflows_t(u64,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

656

u64 pin_flags)

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

111

if (range_overflows(args->offset, args->size, (u64)obj->base.size)) {

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

1167

u64 *offset, struct drm_file *file)

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

1202

u64 *offset)

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

1225

u64 *offset)

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

156

args->addr_ptr = (u64)addr;

sys/dev/pci/drm/i915/gem/i915_gem_mman.c

555

if (range_overflows_t(u64, addr, len, obj->base.size))

sys/dev/pci/drm/i915/gem/i915_gem_mman.h

30

u32 handle, u64 *offset);

sys/dev/pci/drm/i915/gem/i915_gem_object.c

514

i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size)

sys/dev/pci/drm/i915/gem/i915_gem_object.c

529

i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size)

sys/dev/pci/drm/i915/gem/i915_gem_object.c

571

int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size)

sys/dev/pci/drm/i915/gem/i915_gem_object.h

25

static inline bool i915_gem_object_size_2big(u64 size)

sys/dev/pci/drm/i915/gem/i915_gem_object.h

61

__i915_gem_object_create_user(struct drm_i915_private *i915, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_object.h

813

int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size);

sys/dev/pci/drm/i915/gem/i915_gem_object_types.h

732

u64 encode;

sys/dev/pci/drm/i915/gem/i915_gem_object_types.h

87

u64 (*mmap_offset)(struct drm_i915_gem_object *obj);

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

487

u64 remain;

sys/dev/pci/drm/i915/gem/i915_gem_shmem.c

492

u64 size = arg->size;

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1072

u64 i915_gem_stolen_area_address(const struct drm_i915_private *i915)

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1077

u64 i915_gem_stolen_area_size(const struct drm_i915_private *i915)

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1082

u64 i915_gem_stolen_node_address(const struct drm_i915_private *i915,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1093

u64 i915_gem_stolen_node_offset(const struct drm_mm_node *node)

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

1098

u64 i915_gem_stolen_node_size(const struct drm_mm_node *node)

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

386

u64 reg_val = intel_uncore_read64(uncore, GEN6_STOLEN_RESERVED);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

40

struct drm_mm_node *node, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

400

u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

41

unsigned alignment, u64 start, u64 end)

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

555

(u64)resource_size(&i915->dsm.stolen) >> 10,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

556

(u64)i915->dsm.usable_size >> 10);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.c

62

struct drm_mm_node *node, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

18

struct drm_mm_node *node, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

21

struct drm_mm_node *node, u64 size,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

22

unsigned alignment, u64 start,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

23

u64 end);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

42

u64 i915_gem_stolen_area_address(const struct drm_i915_private *i915);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

43

u64 i915_gem_stolen_area_size(const struct drm_i915_private *i915);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

45

u64 i915_gem_stolen_node_address(const struct drm_i915_private *i915,

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

49

u64 i915_gem_stolen_node_offset(const struct drm_mm_node *node);

sys/dev/pci/drm/i915/gem/i915_gem_stolen.h

50

u64 i915_gem_stolen_node_size(const struct drm_mm_node *node);

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

1401

static u64 i915_ttm_mmap_offset(struct drm_i915_gem_object *obj)

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

180

static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

187

return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1148

u64 size, u64 offset,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1204

u64 max;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1205

u64 num;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1206

u64 size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1265

u64 offset_low = num * max_page_size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1266

u64 offset_high = (max - num) * max_page_size;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1355

u64 mask;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

175

u64 size,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

214

const u64 max_len = rounddown_pow_of_two(UINT_MAX);

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

217

u64 rem;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

328

fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

51

u64 rem)

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

744

u64 size = page_num << PAGE_SHIFT;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

85

u64 rem;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

105

u64 hole;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

106

u64 align;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

344

static u64 swizzle_bit(unsigned int bit, u64 offset)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

349

static u64 tiled_offset(const struct intel_gt *gt,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

350

u64 v,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

356

u64 x, y;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

435

u64 v = tiled_offset(buf->vma->vm->gt,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

453

static int pin_buffer(struct i915_vma *vma, u64 addr)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

473

struct blit_buffer *dst, u64 dst_addr,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

474

struct blit_buffer *src, u64 src_addr)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

538

u64 hole_size;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

601

u64 offset = round_up(t->width * t->height * 4, t->align);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

632

u64 offset = round_up(t->width * t->height * 4, 2 * t->align);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1490

static int check_scratch(struct i915_address_space *vm, u64 offset)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1511

u64 offset, u32 value)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1599

u64 offset, u32 *value)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1780

u64 vm_total;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1855

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

583

u64 size;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1053

u64 size, total;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1105

u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1162

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1436

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1545

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1570

ux = u64_to_user_ptr((u64)addr);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1716

static int prefault_range(u64 start, u64 len)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1740

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

39

static u64 swizzle_bit(unsigned int bit, u64 offset)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

44

static u64 tiled_offset(const struct tile *tile, u64 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

46

u64 x, y;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

617

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

663

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

902

u64 offset;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

934

u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

112

struct i915_vma *vma, u64 offset,

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

43

u64 offset,

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h

26

u64 offset,

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h

31

struct i915_vma *vma, u64 offset,

sys/dev/pci/drm/i915/gt/agp_intel_gtt.c

173

intel_gmch_gtt_get(u64 *gtt_total,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

187

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

252

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

272

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

22

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

25

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

28

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

230

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

252

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

27

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

30

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

150

static void gen6_flush_pd(struct gen6_ppgtt *ppgtt, u64 start, u64 end)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

174

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

180

u64 from = start;

sys/dev/pci/drm/i915/gt/gen6_ppgtt.c

75

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

482

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

523

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

530

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

537

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

573

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

30

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

33

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

37

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

40

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

103

const u64 daddr = px_dma(ppgtt->pd);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

115

const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

139

#define GEN8_PDES (GEN8_PAGE_SIZE / sizeof(u64))

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

148

gen8_pd_range(u64 start, u64 end, int lvl, unsigned int *idx)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

151

const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

163

static bool gen8_pd_contains(u64 start, u64 end, int lvl)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

165

const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

171

static unsigned int gen8_pt_count(u64 start, u64 end)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

188

gen8_pdp_for_page_index(struct i915_address_space * const vm, const u64 idx)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

19

static u64 gen8_pde_encode(const dma_addr_t addr,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

199

gen8_pdp_for_page_address(struct i915_address_space * const vm, const u64 addr)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

22

u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

239

static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

241

u64 start, const u64 end, int lvl)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

263

start += (u64)I915_PDES << gen8_pd_shift(lvl);

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

274

u64 *vaddr;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

308

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

32

static u64 gen8_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

325

u64 * const start, const u64 end, int lvl)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

392

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

408

u64 *start, u64 end, int lvl,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

440

u64 start, u64 length,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

454

static __always_inline u64

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

458

u64 idx,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

511

u64 start = vma_res->start;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

512

u64 end = start + vma_res->vma_size;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

61

static u64 gen12_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

619

u64 start = vma_res->start;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

749

u64 idx = vma_res->start >> GEN8_PTE_SHIFT;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

765

u64 offset,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

769

u64 idx = offset >> GEN8_PTE_SHIFT;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

786

u64 offset,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

790

u64 idx = offset >> GEN8_PTE_SHIFT;

sys/dev/pci/drm/i915/gt/gen8_ppgtt.c

815

u64 offset,

sys/dev/pci/drm/i915/gt/gen8_ppgtt.h

17

u64 gen8_ggtt_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_context.c

614

u64 intel_context_get_total_runtime_ns(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_context.c

616

u64 total, active;

sys/dev/pci/drm/i915/gt/intel_context.c

632

u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)

sys/dev/pci/drm/i915/gt/intel_context.c

634

u64 avg = ewma_runtime_read(&ce->stats.runtime.avg);

sys/dev/pci/drm/i915/gt/intel_context.h

400

u64 intel_context_get_total_runtime_ns(struct intel_context *ce);

sys/dev/pci/drm/i915/gt/intel_context.h

401

u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);

sys/dev/pci/drm/i915/gt/intel_context.h

403

static inline u64 intel_context_clock(void)

sys/dev/pci/drm/i915/gt/intel_context_param.h

14

intel_context_set_watchdog_us(struct intel_context *ce, u64 timeout_us)

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

20

u64 offset;

sys/dev/pci/drm/i915/gt/intel_context_types.h

138

u64 timeout_us;

sys/dev/pci/drm/i915/gt/intel_context_types.h

147

u64 desc;

sys/dev/pci/drm/i915/gt/intel_context_types.h

153

u64 active;

sys/dev/pci/drm/i915/gt/intel_context_types.h

158

u64 total;

sys/dev/pci/drm/i915/gt/intel_context_types.h

278

u64 fence_context;

sys/dev/pci/drm/i915/gt/intel_engine.h

232

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

233

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

375

u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

376

u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

377

u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

378

u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

379

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1586

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1590

u64 acthd;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1602

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1604

u64 bbaddr;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2089

u64 addr;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

533

u64 clamp = intel_clamp_##field(engine, engine->props.field); \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

571

u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

573

value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

578

u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

585

u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

592

value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

594

value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

599

u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

601

value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

606

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

613

value = min_t(u64, value, guc_policy_max_exec_quantum_ms());

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

615

value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));

sys/dev/pci/drm/i915/gt/intel_engine_types.h

281

u64 *csb_status;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

340

u64 total_gt_clks;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

345

u64 start_gt_clk;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

350

u64 total;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

542

u64 offset, u32 length,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1728

static bool xehp_csb_parse(const u64 csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1736

static bool gen12_csb_parse(const u64 csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1744

static bool gen8_csb_parse(const u64 csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1749

static noinline u64

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1750

wa_csb_read(const struct intel_engine_cs *engine, u64 * const csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1752

u64 entry;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1773

status += sizeof(u64) * idx;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1783

static u64 csb_read(const struct intel_engine_cs *engine, u64 * const csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1785

u64 entry = READ_ONCE(*csb);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1818

u64 * const buf = execlists->csb_status;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1881

u64 csb;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2836

memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3579

(u64 *)&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

673

static u64 execlists_update_context(struct i915_request *rq)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

676

u64 desc;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

724

static void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1228

static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1280

static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1474

static u64 snb_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1495

static u64 ivb_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1518

static u64 byt_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1533

static u64 hsw_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1545

static u64 iris_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1565

static dma_addr_t gen6_pte_decode(u64 pte, bool *is_present, bool *is_local)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1679

min_t(u64, ggtt->mappable_end, ggtt->vm.total);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1693

(u64)ggtt->mappable_end >> 20);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

1695

(u64)resource_size(&intel_graphics_stolen_res) >> 20);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

290

static u64 mtl_ggtt_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

310

u64 gen8_ggtt_pte_encode(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

322

static dma_addr_t gen8_ggtt_pte_decode(u64 pte, bool *is_present, bool *is_local)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

38

u64 *start,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

39

u64 *end)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

434

memset64((u64 *)cs, scratch_pte,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

439

memset64((u64 *)cs, pte, n_ptes);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

483

u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

497

u64 offset, bool *is_present, bool *is_local)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

507

dma_addr_t addr, u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

567

u64 start, end;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

605

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

626

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

648

u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

662

u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

712

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

731

u64 offset;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

748

u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

786

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

837

u64 offset, bool *is_present, bool *is_local)

sys/dev/pci/drm/i915/gt/intel_ggtt.c

857

u64 offset;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

954

u64 start = ggtt->error_capture.start;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

955

u64 size = ggtt->error_capture.size;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

63

u64 val;

sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c

85

val |= (u64)((stride / 128) - 1) << fence_pitch_shift;

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

20

u64 offset,

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

31

u64 offset, bool *is_present, bool *is_local)

sys/dev/pci/drm/i915/gt/intel_ggtt_gmch.c

55

u64 start, u64 length)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

457

static inline u64 gen8_canonical_addr(u64 address)

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

462

static inline u64 gen8_noncanonical_addr(u64 address)

sys/dev/pci/drm/i915/gt/intel_gt.c

329

u64 fault_addr;

sys/dev/pci/drm/i915/gt/intel_gt.c

331

fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

sys/dev/pci/drm/i915/gt/intel_gt.c

332

((u64)fault_data0 << 12);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

201

static u64 div_u64_roundup(u64 nom, u32 den)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

206

u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

211

u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

216

u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

221

u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c

223

u64 val;

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.h

21

u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.h

22

u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.h

24

u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns);

sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.h

25

u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns);

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c

17

int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val)

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c

33

void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val)

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c

47

static int __intel_gt_debugfs_reset_show(void *data, u64 *val)

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.c

54

static int __intel_gt_debugfs_reset_store(void *data, u64 val)

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.h

52

int intel_gt_debugfs_reset_show(struct intel_gt *gt, u64 *val);

sys/dev/pci/drm/i915/gt/intel_gt_debugfs.h

53

void intel_gt_debugfs_reset_store(struct intel_gt *gt, u64 val);

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

550

static int perf_limit_reasons_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gt/intel_gt_pm_debugfs.c

561

static int perf_limit_reasons_clear(void *data, u64 val)

sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c

173

u64 res = 0;

sys/dev/pci/drm/i915/gt/intel_gtt.c

338

fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)

sys/dev/pci/drm/i915/gt/intel_gtt.c

612

u64 pat;

sys/dev/pci/drm/i915/gt/intel_gtt.c

634

u64 pat;

sys/dev/pci/drm/i915/gt/intel_gtt.h

150

#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))

sys/dev/pci/drm/i915/gt/intel_gtt.h

260

u64 total; /* size addr space maps (ex. 2GB for ggtt) */

sys/dev/pci/drm/i915/gt/intel_gtt.h

261

u64 reserved; /* size addr space reserved */

sys/dev/pci/drm/i915/gt/intel_gtt.h

262

u64 min_alignment[INTEL_MEMORY_STOLEN_LOCAL + 1];

sys/dev/pci/drm/i915/gt/intel_gtt.h

312

u64 (*pte_encode)(dma_addr_t addr,

sys/dev/pci/drm/i915/gt/intel_gtt.h

315

dma_addr_t (*pte_decode)(u64 pte, bool *is_present, bool *is_local);

sys/dev/pci/drm/i915/gt/intel_gtt.h

321

u64 start, u64 length);

sys/dev/pci/drm/i915/gt/intel_gtt.h

323

u64 start, u64 length);

sys/dev/pci/drm/i915/gt/intel_gtt.h

325

u64 start, u64 length);

sys/dev/pci/drm/i915/gt/intel_gtt.h

328

u64 offset,

sys/dev/pci/drm/i915/gt/intel_gtt.h

337

u64 offset,

sys/dev/pci/drm/i915/gt/intel_gtt.h

345

u64 offset, bool *is_present, bool *is_local);

sys/dev/pci/drm/i915/gt/intel_gtt.h

349

u64 start, u64 length,

sys/dev/pci/drm/i915/gt/intel_gtt.h

441

static inline u64 i915_vm_min_alignment(struct i915_address_space *vm,

sys/dev/pci/drm/i915/gt/intel_gtt.h

451

static inline u64 i915_vm_obj_min_alignment(struct i915_address_space *vm,

sys/dev/pci/drm/i915/gt/intel_gtt.h

533

static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

545

static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

547

const u64 mask = ~((1ULL << pde_shift) - 1);

sys/dev/pci/drm/i915/gt/intel_gtt.h

548

u64 end;

sys/dev/pci/drm/i915/gt/intel_gtt.h

561

static inline u32 i915_pde_index(u64 addr, u32 shift)

sys/dev/pci/drm/i915/gt/intel_gtt.h

599

u64 offset, bool *is_present, bool *is_local);

sys/dev/pci/drm/i915/gt/intel_gtt.h

62

typedef u64 gen8_pte_t;

sys/dev/pci/drm/i915/gt/intel_gtt.h

625

fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);

sys/dev/pci/drm/i915/gt/intel_gtt.h

627

#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))

sys/dev/pci/drm/i915/gt/intel_gtt.h

629

u64 v__ = lower_32_bits(v); \

sys/dev/pci/drm/i915/gt/intel_gtt.h

654

u64 (*encode)(const dma_addr_t, const enum i915_cache_level));

sys/dev/pci/drm/i915/gt/intel_gtt.h

685

u64 size);

sys/dev/pci/drm/i915/gt/intel_lrc.h

140

#define DG2_PREDICATE_RESULT_WA (PAGE_SIZE - sizeof(u64))

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

35

const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \

sys/dev/pci/drm/i915/gt/intel_lrc_reg.h

42

const u64 addr__ = px_dma((ppgtt)->pd); \

sys/dev/pci/drm/i915/gt/intel_migrate.c

16

u64 offset;

sys/dev/pci/drm/i915/gt/intel_migrate.c

163

u64 base = (u64)i << 32;

sys/dev/pci/drm/i915/gt/intel_migrate.c

166

u64 sz;

sys/dev/pci/drm/i915/gt/intel_migrate.c

189

sz += (sz >> 12) * sizeof(u64);

sys/dev/pci/drm/i915/gt/intel_migrate.c

366

u64 offset,

sys/dev/pci/drm/i915/gt/intel_migrate.c

370

const u64 encode = rq->context->vm->pte_encode(0, pat_index,

sys/dev/pci/drm/i915/gt/intel_migrate.c

397

offset *= sizeof(u64);

sys/dev/pci/drm/i915/gt/intel_migrate.c

401

offset += (u64)rq->engine->instance << 32;

sys/dev/pci/drm/i915/gt/intel_migrate.c

628

static u64 scatter_list_length(struct scatterlist *sg)

sys/dev/pci/drm/i915/gt/intel_migrate.c

630

u64 len = 0;

sys/dev/pci/drm/i915/gt/intel_migrate.c

642

u64 bytes_to_cpy, u64 ccs_bytes_to_cpy)

sys/dev/pci/drm/i915/gt/intel_migrate.c

652

return min_t(u64, bytes_to_cpy, CHUNK_SZ);

sys/dev/pci/drm/i915/gt/intel_migrate.c

657

static void get_ccs_sg_sgt(struct sgt_dma *it, u64 bytes_to_cpy)

sys/dev/pci/drm/i915/gt/intel_migrate.c

659

u64 len;

sys/dev/pci/drm/i915/gt/intel_migrate.c

690

u64 ccs_bytes_to_cpy = 0, bytes_to_cpy;

sys/dev/pci/drm/i915/gt/intel_migrate.c

695

u64 src_sz, dst_sz;

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

102

u64 (*encode)(const dma_addr_t, const enum i915_cache_level))

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

217

static unsigned long pd_count(u64 size, int shift)

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

225

u64 size)

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

90

const u64 encoded_entry)

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

92

u64 * const vaddr = __px_vaddr(pdma);

sys/dev/pci/drm/i915/gt/intel_ppgtt.c

95

drm_clflush_virt_range(&vaddr[idx], sizeof(u64));

sys/dev/pci/drm/i915/gt/intel_rc6.c

344

GEM_BUG_ON(range_end_overflows_t(u64,

sys/dev/pci/drm/i915/gt/intel_rc6.c

739

static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)

sys/dev/pci/drm/i915/gt/intel_rc6.c

781

return lower | (u64)upper << 8;

sys/dev/pci/drm/i915/gt/intel_rc6.c

784

u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

788

u64 time_hw, prev_hw, overflow_hw;

sys/dev/pci/drm/i915/gt/intel_rc6.c

847

u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)

sys/dev/pci/drm/i915/gt/intel_rc6.h

25

u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);

sys/dev/pci/drm/i915/gt/intel_rc6.h

26

u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);

sys/dev/pci/drm/i915/gt/intel_rc6_types.h

28

u64 prev_hw_residency[INTEL_RC6_RES_MAX];

sys/dev/pci/drm/i915/gt/intel_rc6_types.h

29

u64 cur_residency[INTEL_RC6_RES_MAX];

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

208

u64 *start, u32 *size)

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

225

u64 reserve_start;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

261

u64 tile_stolen, flat_ccs_base;

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

331

(u64)io_size >> 20);

sys/dev/pci/drm/i915/gt/intel_region_lmem.c

87

(u64)lmem_size >> 20);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

66

u64 r = s + i915_vma_offset(so->vma);

sys/dev/pci/drm/i915/gt/intel_reset.c

849

u64 vma_offset;

sys/dev/pci/drm/i915/gt/intel_ring.c

292

GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));

sys/dev/pci/drm/i915/gt/intel_ring.c

295

memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));

sys/dev/pci/drm/i915/gt/intel_rps.c

1502

u64 corr, corr2;

sys/dev/pci/drm/i915/gt/intel_rps.c

1796

u64 time, c0;

sys/dev/pci/drm/i915/gt/intel_rps.c

330

u64 total, delta;

sys/dev/pci/drm/i915/gt/intel_rps.c

400

u64 now, delta, dt;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

16

u64 last_count1;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

19

u64 last_count2;

sys/dev/pci/drm/i915/gt/intel_rps_types.h

20

u64 last_time2;

sys/dev/pci/drm/i915/gt/intel_timeline.h

47

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.h

59

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline_types.h

22

u64 fence_context;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2748

u64 offset = i915_vma_offset((*prev)->batch);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3085

u64 addr;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

101

u64 time;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

102

u64 dt;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

17

const u64 *a = A, *b = B;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

96

static u64 hws_address(const struct i915_vma *hws,

sys/dev/pci/drm/i915/gt/selftest_rc6.c

17

static u64 rc6_residency(struct intel_rc6 *rc6)

sys/dev/pci/drm/i915/gt/selftest_rc6.c

19

u64 result;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

38

u64 rc0_sample_energy[2];

sys/dev/pci/drm/i915/gt/selftest_rc6.c

39

u64 rc6_sample_energy[2];

sys/dev/pci/drm/i915/gt/selftest_rc6.c

40

u64 sleep_time = 1000;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

43

u64 rc0_power;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

44

u64 rc6_power;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

46

u64 threshold;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

48

u64 res[2];

sys/dev/pci/drm/i915/gt/selftest_rc6.c

50

u64 diff;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1098

static u64 __measure_power(int duration_ms)

sys/dev/pci/drm/i915/gt/selftest_rps.c

1100

u64 dE, dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1111

static u64 measure_power(struct intel_rps *rps, int *freq)

sys/dev/pci/drm/i915/gt/selftest_rps.c

1113

u64 x[5];

sys/dev/pci/drm/i915/gt/selftest_rps.c

1126

static u64 measure_power_at(struct intel_rps *rps, int *freq)

sys/dev/pci/drm/i915/gt/selftest_rps.c

1165

u64 power;

sys/dev/pci/drm/i915/gt/selftest_rps.c

248

u64 dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

329

u64 time = intel_gt_pm_interval_to_ns(gt, cycles);

sys/dev/pci/drm/i915/gt/selftest_rps.c

34

const u64 *a = A, *b = B;

sys/dev/pci/drm/i915/gt/selftest_rps.c

540

static u64 __measure_frequency(u32 *cntr, int duration_ms)

sys/dev/pci/drm/i915/gt/selftest_rps.c

542

u64 dc, dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

553

static u64 measure_frequency_at(struct intel_rps *rps, u32 *cntr, int *freq)

sys/dev/pci/drm/i915/gt/selftest_rps.c

555

u64 x[5];

sys/dev/pci/drm/i915/gt/selftest_rps.c

568

static u64 __measure_cs_frequency(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

571

u64 dc, dt;

sys/dev/pci/drm/i915/gt/selftest_rps.c

582

static u64 measure_cs_frequency_at(struct intel_rps *rps,

sys/dev/pci/drm/i915/gt/selftest_rps.c

586

u64 x[5];

sys/dev/pci/drm/i915/gt/selftest_rps.c

599

static bool scaled_within(u64 x, u64 y, u32 f_n, u32 f_d)

sys/dev/pci/drm/i915/gt/selftest_rps.c

638

u64 count;

sys/dev/pci/drm/i915/gt/selftest_rps.c

701

u64 count;

sys/dev/pci/drm/i915/gt/selftest_rps.c

777

u64 count;

sys/dev/pci/drm/i915/gt/selftest_rps.c

839

u64 count;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

100

u64 x[5];

sys/dev/pci/drm/i915/gt/selftest_slpc.c

113

static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

202

u64 power;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

98

static u64 slpc_measure_power(struct intel_rps *rps, int *freq)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

205

u64 ctx,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

254

u64 ctx = BIT_ULL(order) + offset;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

267

u64 ctx = BIT_ULL(order) + offset;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

292

u64 prng32_1M;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

326

u64 id = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

341

u64 id = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

425

u64 id = (u64)(count & mask) << order;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

23

static void vma_set_qw(struct i915_vma *vma, u64 addr, u64 val)

sys/dev/pci/drm/i915/gt/selftest_tlb.c

230

void (*tlbinv)(struct i915_address_space *vm, u64 addr, u64 length))

sys/dev/pci/drm/i915/gt/selftest_tlb.c

35

u64 align,

sys/dev/pci/drm/i915/gt/selftest_tlb.c

36

void (*tlbinv)(struct i915_address_space *vm, u64 addr, u64 length),

sys/dev/pci/drm/i915/gt/selftest_tlb.c

363

static void tlbinv_full(struct i915_address_space *vm, u64 addr, u64 length)

sys/dev/pci/drm/i915/gt/selftest_tlb.c

37

u64 length,

sys/dev/pci/drm/i915/gt/selftest_tlb.c

46

u64 addr;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

522

u64 addr = i915_vma_offset(scratch);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

869

u64 offset = i915_vma_offset(results) + sizeof(u32) * i;

sys/dev/pci/drm/i915/gt/selftests/mock_timeline.c

11

void mock_timeline_init(struct intel_timeline *timeline, u64 context)

sys/dev/pci/drm/i915/gt/selftests/mock_timeline.h

14

void mock_timeline_init(struct intel_timeline *timeline, u64 context);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

395

u64 offset;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

129

u64 addr_in = i915_ggtt_offset(gsc->proxy.vma);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

130

u64 addr_out = addr_in + GSC_PROXY_BUFFER_SIZE;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

110

u64 host_session_id)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

16

u64 addr_in;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

18

u64 addr_out;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

44

int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64 addr_in,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

45

u32 size_in, u64 addr_out,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

44

u64 host_session_handle;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

47

u64 gsc_message_handle;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

68

u64 addr_in, u32 size_in,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

69

u64 addr_out, u32 size_out);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

72

u64 host_session_id);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

75

u64 addr_in;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

77

u64 addr_out;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

86

u64 host_session_id);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

408

u64 ktime;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

782

u64 flags;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

858

static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

887

static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

902

int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

261

u64 gt_stamp;

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

422

GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

445

int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value);

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

104

static int guc_sched_disable_gucid_threshold_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

115

static int guc_sched_disable_gucid_threshold_set(void *data, u64 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

76

static int guc_sched_disable_delay_ms_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

83

*val = (u64)guc->submission_state.sched_disable_delay_ms;

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

88

static int guc_sched_disable_delay_ms_set(void *data, u64 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_debugfs.c

96

guc->submission_state.sched_disable_delay_ms = min_t(u64, val, 60000);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

172

u64 delta_ms;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

209

u64 db_base_addr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_fwif.h

213

u64 wq_base_addr;

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

84

static int guc_log_level_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_log_debugfs.c

96

static int guc_log_level_set(void *data, u64 val)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1182

__extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1211

*prev_start = ((u64)gt_stamp_hi << 32) | new_start;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1300

u64 gpm_ts;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1313

guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_lo;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1327

u64 total, gt_stamp_saved;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1373

u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1458

u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2899

u64 wq_desc_offset, wq_base_offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2904

wq_desc_offset = (u64)i915_ggtt_offset(ce->state) +

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2906

wq_base_offset = (u64)i915_ggtt_offset(ce->state) +

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3377

u64 delay = guc->submission_state.sched_disable_delay_ms;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4204

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4207

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5639

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5686

u64 offset, u32 len,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

883

FIELD_PREP(WQ_RING_TAIL_MASK, ce->ring->tail / sizeof(u64));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

886

*wqi++ = child->ring->tail / sizeof(u64);

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

472

u64 delta_ms;

sys/dev/pci/drm/i915/gt/uc/intel_huc_fw.c

34

u64 pkt_offset;

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1092

u64 offset;

sys/dev/pci/drm/i915/gvt/aperture_gm.c

131

u32 fence, u64 value)

sys/dev/pci/drm/i915/gvt/aperture_gm.c

47

u64 start, end, size;

sys/dev/pci/drm/i915/gvt/cfg_space.c

186

u64 size;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1211

ret |= cmd_address_audit(s, gma, sizeof(u64),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1275

u64 stride_val;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1276

u64 tile_val;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1277

u64 surf_val;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1740

ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

762

s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

866

u64 pdps[GEN8_3LVL_PDPES];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

870

pdps[0] = (u64)cmd_val(s, 2) << 32;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

984

u64 ro_mask = mmio_info->ro_mask;

sys/dev/pci/drm/i915/gvt/debugfs.c

128

vgpu_scan_nonprivbb_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gvt/debugfs.c

143

vgpu_scan_nonprivbb_set(void *data, u64 val)

sys/dev/pci/drm/i915/gvt/debugfs.c

155

static int vgpu_status_get(void *data, u64 *val)

sys/dev/pci/drm/i915/gvt/display.c

801

int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)

sys/dev/pci/drm/i915/gvt/display.h

121

u64 period;

sys/dev/pci/drm/i915/gvt/display.h

163

int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);

sys/dev/pci/drm/i915/gvt/fb_decoder.h

113

u64 base_gpa;

sys/dev/pci/drm/i915/gvt/fb_decoder.h

128

u64 base_gpa;

sys/dev/pci/drm/i915/gvt/fb_decoder.h

144

u64 base_gpa;

sys/dev/pci/drm/i915/gvt/firmware.c

139

u64 file, request;

sys/dev/pci/drm/i915/gvt/firmware.c

147

item = (s); file = (u64)(a); request = (u64)(b); \

sys/dev/pci/drm/i915/gvt/firmware.c

42

u64 magic;

sys/dev/pci/drm/i915/gvt/firmware.c

45

u64 cfg_space_size;

sys/dev/pci/drm/i915/gvt/firmware.c

46

u64 cfg_space_offset; /* offset in the file */

sys/dev/pci/drm/i915/gvt/firmware.c

47

u64 mmio_size;

sys/dev/pci/drm/i915/gvt/firmware.c

48

u64 mmio_offset; /* offset in the file */

sys/dev/pci/drm/i915/gvt/gtt.c

1627

u64 pa, void *p_data, int bytes)

sys/dev/pci/drm/i915/gvt/gtt.c

1798

enum intel_gvt_gtt_type root_entry_type, u64 pdps[])

sys/dev/pci/drm/i915/gvt/gtt.c

1860

mm->ggtt_mm.host_ggtt_aperture = vzalloc((vgpu_aperture_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));

sys/dev/pci/drm/i915/gvt/gtt.c

1867

mm->ggtt_mm.host_ggtt_hidden = vzalloc((vgpu_hidden_sz(vgpu) >> PAGE_SHIFT) * sizeof(u64));

sys/dev/pci/drm/i915/gvt/gtt.c

214

static u64 read_pte64(struct i915_ggtt *ggtt, unsigned long index)

sys/dev/pci/drm/i915/gvt/gtt.c

230

static void write_pte64(struct i915_ggtt *ggtt, unsigned long index, u64 pte)

sys/dev/pci/drm/i915/gvt/gtt.c

2539

u64 pdps[])

sys/dev/pci/drm/i915/gvt/gtt.c

257

e->val64 = *((u64 *)pt + index);

sys/dev/pci/drm/i915/gvt/gtt.c

2576

enum intel_gvt_gtt_type root_entry_type, u64 pdps[])

sys/dev/pci/drm/i915/gvt/gtt.c

2601

int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])

sys/dev/pci/drm/i915/gvt/gtt.c

282

*((u64 *)pt + index) = e->val64;

sys/dev/pci/drm/i915/gvt/gtt.c

57

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)

sys/dev/pci/drm/i915/gvt/gtt.c

717

u64 pa, void *p_data, int bytes);

sys/dev/pci/drm/i915/gvt/gtt.c

721

u64 gpa, void *data, int bytes)

sys/dev/pci/drm/i915/gvt/gtt.h

145

u64 data;

sys/dev/pci/drm/i915/gvt/gtt.h

164

u64 guest_pdps[GVT_RING_CTX_NR_PDPS];

sys/dev/pci/drm/i915/gvt/gtt.h

165

u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];

sys/dev/pci/drm/i915/gvt/gtt.h

175

u64 *host_ggtt_aperture;

sys/dev/pci/drm/i915/gvt/gtt.h

176

u64 *host_ggtt_hidden;

sys/dev/pci/drm/i915/gvt/gtt.h

183

enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);

sys/dev/pci/drm/i915/gvt/gtt.h

277

u64 pdps[]);

sys/dev/pci/drm/i915/gvt/gtt.h

280

enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);

sys/dev/pci/drm/i915/gvt/gtt.h

282

int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);

sys/dev/pci/drm/i915/gvt/gtt.h

53

u64 val64;

sys/dev/pci/drm/i915/gvt/gvt.h

102

u64 size;

sys/dev/pci/drm/i915/gvt/gvt.h

157

u64 i915_context_pml4;

sys/dev/pci/drm/i915/gvt/gvt.h

158

u64 i915_context_pdps[GEN8_3LVL_PDPES];

sys/dev/pci/drm/i915/gvt/gvt.h

170

u64 ring_context_gpa;

sys/dev/pci/drm/i915/gvt/gvt.h

453

u32 fence, u64 value);

sys/dev/pci/drm/i915/gvt/gvt.h

464

(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

sys/dev/pci/drm/i915/gvt/gvt.h

466

(*(u64 *)(vgpu->mmio.vreg + (offset)))

sys/dev/pci/drm/i915/gvt/gvt.h

535

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);

sys/dev/pci/drm/i915/gvt/gvt.h

549

static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)

sys/dev/pci/drm/i915/gvt/gvt.h

552

return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &

sys/dev/pci/drm/i915/gvt/gvt.h

750

int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn);

sys/dev/pci/drm/i915/gvt/gvt.h

751

int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn);

sys/dev/pci/drm/i915/gvt/gvt.h

81

u64 aperture_sz;

sys/dev/pci/drm/i915/gvt/gvt.h

82

u64 hidden_sz;

sys/dev/pci/drm/i915/gvt/handlers.c

1494

u64 *pdps;

sys/dev/pci/drm/i915/gvt/handlers.c

1496

pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));

sys/dev/pci/drm/i915/gvt/handlers.c

1939

u64 pat =

sys/dev/pci/drm/i915/gvt/handlers.c

3174

u64 ro_mask = mmio_info->ro_mask;

sys/dev/pci/drm/i915/gvt/handlers.c

3176

u64 data = 0;

sys/dev/pci/drm/i915/gvt/handlers.c

693

u64 pixel_clk = 0;

sys/dev/pci/drm/i915/gvt/kvmgt.c

1018

u64 virtaddr;

sys/dev/pci/drm/i915/gvt/kvmgt.c

1553

int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn)

sys/dev/pci/drm/i915/gvt/kvmgt.c

1571

int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn)

sys/dev/pci/drm/i915/gvt/kvmgt.c

62

#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)

sys/dev/pci/drm/i915/gvt/kvmgt.c

620

static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova,

sys/dev/pci/drm/i915/gvt/kvmgt.c

621

u64 length)

sys/dev/pci/drm/i915/gvt/kvmgt.c

625

u64 iov_pfn = iova >> PAGE_SHIFT;

sys/dev/pci/drm/i915/gvt/kvmgt.c

626

u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE;

sys/dev/pci/drm/i915/gvt/kvmgt.c

63

#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)

sys/dev/pci/drm/i915/gvt/kvmgt.c

724

static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)

sys/dev/pci/drm/i915/gvt/kvmgt.c

748

return ((u64)start_hi << 32) | start_lo;

sys/dev/pci/drm/i915/gvt/kvmgt.c

751

static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off,

sys/dev/pci/drm/i915/gvt/kvmgt.c

754

u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar);

sys/dev/pci/drm/i915/gvt/kvmgt.c

766

static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off)

sys/dev/pci/drm/i915/gvt/kvmgt.c

772

static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,

sys/dev/pci/drm/i915/gvt/kvmgt.c

803

u64 pos = *ppos & VFIO_PCI_OFFSET_MASK;

sys/dev/pci/drm/i915/gvt/kvmgt.c

857

offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) -

sys/dev/pci/drm/i915/gvt/kvmgt.c

878

u64 val;

sys/dev/pci/drm/i915/gvt/kvmgt.c

953

u64 val;

sys/dev/pci/drm/i915/gvt/mmio.c

109

int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,

sys/dev/pci/drm/i915/gvt/mmio.c

184

int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,

sys/dev/pci/drm/i915/gvt/mmio.c

54

int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)

sys/dev/pci/drm/i915/gvt/mmio.c

56

u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);

sys/dev/pci/drm/i915/gvt/mmio.c

67

static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,

sys/dev/pci/drm/i915/gvt/mmio.h

64

u64 ro_mask;

sys/dev/pci/drm/i915/gvt/mmio.h

87

int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);

sys/dev/pci/drm/i915/gvt/mmio.h

89

int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,

sys/dev/pci/drm/i915/gvt/mmio.h

91

int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,

sys/dev/pci/drm/i915/gvt/opregion.c

418

u64 scic_pa = 0, parm_pa = 0;

sys/dev/pci/drm/i915/gvt/page_track.c

159

int intel_vgpu_page_track_handler(struct intel_vgpu *vgpu, u64 gpa,

sys/dev/pci/drm/i915/gvt/page_track.h

35

u64 gpa, void *data, int bytes);

sys/dev/pci/drm/i915/gvt/page_track.h

56

int intel_vgpu_page_track_handler(struct intel_vgpu *vgpu, u64 gpa,

sys/dev/pci/drm/i915/gvt/sched_policy.c

97

static u64 stage_check;

sys/dev/pci/drm/i915/gvt/scheduler.c

1569

u64 ring_context_gpa, u32 pdp[8])

sys/dev/pci/drm/i915/gvt/scheduler.c

1571

u64 gpa;

sys/dev/pci/drm/i915/gvt/scheduler.c

1587

u64 pdps[GVT_RING_CTX_NR_PDPS];

sys/dev/pci/drm/i915/gvt/scheduler.c

1636

u64 ring_context_gpa;

sys/dev/pci/drm/i915/gvt/scheduler.c

348

u64 desc = ce->lrc.desc;

sys/dev/pci/drm/i915/gvt/scheduler.c

355

desc |= (u64)workload->ctx_desc.addressing_mode <<

sys/dev/pci/drm/i915/gvt/scheduler.c

908

u64 ring_context_gpa, u32 pdp[8])

sys/dev/pci/drm/i915/gvt/scheduler.c

910

u64 gpa;

sys/dev/pci/drm/i915/gvt/scheduler.c

923

u64 shadow_pdp = c->pdps[7].val | (u64) c->pdps[6].val << 32;

sys/dev/pci/drm/i915/gvt/scheduler.h

113

u64 ring_context_gpa;

sys/dev/pci/drm/i915/gvt/trace.h

172

TP_PROTO(int id, const char *tag, void *spt, int type, u64 v,

sys/dev/pci/drm/i915/gvt/trace.h

209

TP_PROTO(int id, int page_id, void *gpt, int type, u64 v,

sys/dev/pci/drm/i915/i915_active.c

236

static struct active_node *__active_lookup(struct i915_active *ref, u64 idx)

sys/dev/pci/drm/i915/i915_active.c

251

u64 cached = READ_ONCE(it->timeline);

sys/dev/pci/drm/i915/i915_active.c

292

active_instance(struct i915_active *ref, u64 idx)

sys/dev/pci/drm/i915/i915_active.c

30

u64 timeline __aligned(8);

sys/dev/pci/drm/i915/i915_active.c

440

u64 idx = i915_request_timeline(rq)->fence_context;

sys/dev/pci/drm/i915/i915_active.c

766

static inline bool is_idle_barrier(struct active_node *node, u64 idx)

sys/dev/pci/drm/i915/i915_active.c

771

static struct active_node *reuse_idle_barrier(struct i915_active *ref, u64 idx)

sys/dev/pci/drm/i915/i915_active.c

875

u64 idx = engine->kernel_context->timeline->fence_context;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1352

u64 batch_addr,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1353

u64 shadow_addr,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1356

u64 jump_offset, jump_target;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1371

jump_target = *(u64 *)(cmd + 1);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1391

*(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1457

u64 batch_addr, shadow_addr;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1462

GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length,

sys/dev/pci/drm/i915/i915_config.c

12

i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context)

sys/dev/pci/drm/i915/i915_config.h

15

u64 context);

sys/dev/pci/drm/i915/i915_debugfs.c

491

static int i915_wedged_get(void *data, u64 *val)

sys/dev/pci/drm/i915/i915_debugfs.c

514

static int i915_wedged_set(void *data, u64 val)

sys/dev/pci/drm/i915/i915_debugfs.c

531

i915_perf_noa_delay_set(void *data, u64 val)

sys/dev/pci/drm/i915/i915_debugfs.c

547

i915_perf_noa_delay_get(void *data, u64 *val)

sys/dev/pci/drm/i915/i915_debugfs.c

581

i915_drop_caches_get(void *data, u64 *val)

sys/dev/pci/drm/i915/i915_debugfs.c

589

gt_drop_caches(struct intel_gt *gt, u64 val)

sys/dev/pci/drm/i915/i915_debugfs.c

622

i915_drop_caches_set(void *data, u64 val)

sys/dev/pci/drm/i915/i915_drm_client.c

119

static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)

sys/dev/pci/drm/i915/i915_drm_client.c

123

u64 total = 0;

sys/dev/pci/drm/i915/i915_drm_client.c

142

u64 total = atomic64_read(&client->past_runtime[class]);

sys/dev/pci/drm/i915/i915_drm_client.c

54

const u64 sz = obj->base.size;

sys/dev/pci/drm/i915/i915_drv.h

171

u64 shrink_memory;

sys/dev/pci/drm/i915/i915_gem.c

1007

u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_gem.c

232

u64 remain;

sys/dev/pci/drm/i915/i915_gem.c

255

unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);

sys/dev/pci/drm/i915/i915_gem.c

481

if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {

sys/dev/pci/drm/i915/i915_gem.c

672

u64 remain;

sys/dev/pci/drm/i915/i915_gem.c

703

unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);

sys/dev/pci/drm/i915/i915_gem.c

762

if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {

sys/dev/pci/drm/i915/i915_gem.c

905

u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_gem.c

96

u64 pinned;

sys/dev/pci/drm/i915/i915_gem.h

59

u64 size, u64 alignment, u64 flags);

sys/dev/pci/drm/i915/i915_gem.h

64

u64 size, u64 alignment, u64 flags);

sys/dev/pci/drm/i915/i915_gem_evict.c

150

u64 min_size, u64 alignment,

sys/dev/pci/drm/i915/i915_gem_evict.c

152

u64 start, u64 end,

sys/dev/pci/drm/i915/i915_gem_evict.c

335

u64 start = target->start;

sys/dev/pci/drm/i915/i915_gem_evict.c

336

u64 end = start + target->size;

sys/dev/pci/drm/i915/i915_gem_evict.h

18

u64 min_size, u64 alignment,

sys/dev/pci/drm/i915/i915_gem_evict.h

20

u64 start, u64 end,

sys/dev/pci/drm/i915/i915_gem_gtt.c

105

u64 size, u64 offset, unsigned long color,

sys/dev/pci/drm/i915/i915_gem_gtt.c

135

static u64 random_offset(u64 start, u64 end, u64 len, u64 align)

sys/dev/pci/drm/i915/i915_gem_gtt.c

137

u64 range, addr;

sys/dev/pci/drm/i915/i915_gem_gtt.c

144

if (sizeof(unsigned long) == sizeof(u64)) {

sys/dev/pci/drm/i915/i915_gem_gtt.c

198

u64 size, u64 alignment, unsigned long color,

sys/dev/pci/drm/i915/i915_gem_gtt.c

199

u64 start, u64 end, unsigned int flags)

sys/dev/pci/drm/i915/i915_gem_gtt.c

202

u64 offset;

sys/dev/pci/drm/i915/i915_gem_gtt.h

31

u64 size, u64 offset, unsigned long color,

sys/dev/pci/drm/i915/i915_gem_gtt.h

37

u64 size, u64 alignment, unsigned long color,

sys/dev/pci/drm/i915/i915_gem_gtt.h

38

u64 start, u64 end, unsigned int flags);

sys/dev/pci/drm/i915/i915_gpu_error.c

1200

const u64 slot = ggtt->error_capture.start;

sys/dev/pci/drm/i915/i915_gpu_error.c

1378

ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;

sys/dev/pci/drm/i915/i915_gpu_error.c

1379

ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;

sys/dev/pci/drm/i915/i915_gpu_error.c

584

u64 start = batch->gtt_offset;

sys/dev/pci/drm/i915/i915_gpu_error.c

585

u64 end = start + batch->gtt_size;

sys/dev/pci/drm/i915/i915_gpu_error.h

104

u64 total_runtime;

sys/dev/pci/drm/i915/i915_gpu_error.h

105

u64 avg_runtime;

sys/dev/pci/drm/i915/i915_gpu_error.h

122

u64 pdp[4];

sys/dev/pci/drm/i915/i915_gpu_error.h

169

u64 fence[I915_MAX_NUM_FENCES];

sys/dev/pci/drm/i915/i915_gpu_error.h

39

u64 gtt_offset;

sys/dev/pci/drm/i915/i915_gpu_error.h

40

u64 gtt_size;

sys/dev/pci/drm/i915/i915_gpu_error.h

83

u64 bbaddr;

sys/dev/pci/drm/i915/i915_gpu_error.h

84

u64 acthd;

sys/dev/pci/drm/i915/i915_gpu_error.h

86

u64 faddr;

sys/dev/pci/drm/i915/i915_gtt_view_types.h

32

u64 offset;

sys/dev/pci/drm/i915/i915_hwmon.c

175

u64 tau4, out;

sys/dev/pci/drm/i915/i915_hwmon.c

190

tau4 = (u64)((1 << x_w) | x) << y;

sys/dev/pci/drm/i915/i915_hwmon.c

205

u64 tau4, r, max_win;

sys/dev/pci/drm/i915/i915_hwmon.c

226

tau4 = (u64)((1 << x_w) | x) << y;

sys/dev/pci/drm/i915/i915_hwmon.c

233

val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);

sys/dev/pci/drm/i915/i915_hwmon.c

412

u64 r, min, max;

sys/dev/pci/drm/i915/i915_hwmon.c

436

*val = clamp_t(u64, *val, min, max);

sys/dev/pci/drm/i915/i915_hwmon.c

486

nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);

sys/dev/pci/drm/i915/i915_hwmon.c

52

u64 time_prev;

sys/dev/pci/drm/i915/i915_hwmon.c

675

u64 rotations, time_now, time;

sys/dev/pci/drm/i915/i915_hwmon.c

99

static u64

sys/dev/pci/drm/i915/i915_perf.c

1961

const u64 delay_ticks = 0xffffffffffffffff -

sys/dev/pci/drm/i915/i915_perf.c

368

u64 single_context:1;

sys/dev/pci/drm/i915/i915_perf.c

369

u64 hold_preemption:1;

sys/dev/pci/drm/i915/i915_perf.c

370

u64 ctx_handle;

sys/dev/pci/drm/i915/i915_perf.c

383

u64 poll_oa_period;

sys/dev/pci/drm/i915/i915_perf.c

3971

static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)

sys/dev/pci/drm/i915/i915_perf.c

3973

u64 nom = (2ULL << exponent) * NSEC_PER_SEC;

sys/dev/pci/drm/i915/i915_perf.c

4007

u64 __user *uprops,

sys/dev/pci/drm/i915/i915_perf.c

4013

u64 __user *uprop = uprops;

sys/dev/pci/drm/i915/i915_perf.c

4041

u64 oa_period, oa_freq_hz;

sys/dev/pci/drm/i915/i915_perf.c

4042

u64 id, value;

sys/dev/pci/drm/i915/i915_perf.c

4114

u64 tmp = NSEC_PER_SEC;

sys/dev/pci/drm/i915/i915_perf.c

468

static u64 oa_report_id(struct i915_perf_stream *stream, void *report)

sys/dev/pci/drm/i915/i915_perf.c

470

return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;

sys/dev/pci/drm/i915/i915_perf.c

473

static u64 oa_report_reason(struct i915_perf_stream *stream, void *report)

sys/dev/pci/drm/i915/i915_perf.c

4815

u64 *arg = data;

sys/dev/pci/drm/i915/i915_perf.c

484

*(u64 *)report = 0;

sys/dev/pci/drm/i915/i915_perf.c

495

static u64 oa_timestamp(struct i915_perf_stream *stream, void *report)

sys/dev/pci/drm/i915/i915_perf.c

498

*((u64 *)report + 1) :

sys/dev/pci/drm/i915/i915_perf.c

505

*(u64 *)&report[2] = 0;

sys/dev/pci/drm/i915/i915_perf.c

782

u64 reason;

sys/dev/pci/drm/i915/i915_perf_types.h

344

u64 poll_oa_period;

sys/dev/pci/drm/i915/i915_pmu.c

1013

u64 config = ___I915_PMU_OTHER(j, events[i].counter);

sys/dev/pci/drm/i915/i915_pmu.c

103

static unsigned int config_bit(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

1049

u64 config = ___I915_PMU_OTHER(j, events[i].counter);

sys/dev/pci/drm/i915/i915_pmu.c

111

static __always_inline u32 config_mask(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

180

static u64 __get_rc6(struct intel_gt *gt)

sys/dev/pci/drm/i915/i915_pmu.c

183

u64 val;

sys/dev/pci/drm/i915/i915_pmu.c

201

static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)

sys/dev/pci/drm/i915/i915_pmu.c

207

store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)

sys/dev/pci/drm/i915/i915_pmu.c

218

static u64 get_rc6(struct intel_gt *gt)

sys/dev/pci/drm/i915/i915_pmu.c

225

u64 val;

sys/dev/pci/drm/i915/i915_pmu.c

24

#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)

sys/dev/pci/drm/i915/i915_pmu.c

269

u64 val = __get_rc6(gt);

sys/dev/pci/drm/i915/i915_pmu.c

41

static u8 engine_config_sample(u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

569

config_status(struct drm_i915_private *i915, u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

61

static bool is_engine_config(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

657

static u64 __i915_pmu_event_read(struct perf_event *event)

sys/dev/pci/drm/i915/i915_pmu.c

66

static unsigned int config_gt_id(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

661

u64 val = 0;

sys/dev/pci/drm/i915/i915_pmu.c

684

const u64 config = config_counter(event->attr.config);

sys/dev/pci/drm/i915/i915_pmu.c

71

static u64 config_counter(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

718

u64 prev, new;

sys/dev/pci/drm/i915/i915_pmu.c

76

static unsigned int other_bit(const u64 config)

sys/dev/pci/drm/i915/i915_pmu.c

954

add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)

sys/dev/pci/drm/i915/i915_pmu.h

55

u64 cur;

sys/dev/pci/drm/i915/i915_ptr_util.h

49

typecheck(u64, x); \

sys/dev/pci/drm/i915/i915_pvinfo.h

62

u64 magic; /* VGT_MAGIC */

sys/dev/pci/drm/i915/i915_query.c

179

u64 user_regs_ptr,

sys/dev/pci/drm/i915/i915_query.c

197

u64 user_regs_ptr,

sys/dev/pci/drm/i915/i915_query.c

238

u64 config_id;

sys/dev/pci/drm/i915/i915_query.c

354

return sizeof(struct drm_i915_query_perf_config) + sizeof(u64) * count;

sys/dev/pci/drm/i915/i915_query.c

378

u64 *oa_config_ids = NULL;

sys/dev/pci/drm/i915/i915_query.c

398

u64 *ids;

sys/dev/pci/drm/i915/i915_reg_defs.h

87

#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))

sys/dev/pci/drm/i915/i915_scatterlist.c

119

u64 len;

sys/dev/pci/drm/i915/i915_scatterlist.c

133

len = min_t(u64, block_size, max_segment - sg->length);

sys/dev/pci/drm/i915/i915_scatterlist.c

164

u64 region_start,

sys/dev/pci/drm/i915/i915_scatterlist.c

168

const u64 size = res->size;

sys/dev/pci/drm/i915/i915_scatterlist.c

203

u64 block_size, offset;

sys/dev/pci/drm/i915/i915_scatterlist.c

205

block_size = min_t(u64, size, drm_buddy_block_size(mm, block));

sys/dev/pci/drm/i915/i915_scatterlist.c

209

u64 len;

sys/dev/pci/drm/i915/i915_scatterlist.c

223

len = min_t(u64, block_size, max_segment - sg->length);

sys/dev/pci/drm/i915/i915_scatterlist.c

81

u64 region_start,

sys/dev/pci/drm/i915/i915_scatterlist.c

86

u64 block_size, offset, prev_end;

sys/dev/pci/drm/i915/i915_scatterlist.h

240

u64 region_start,

sys/dev/pci/drm/i915/i915_scatterlist.h

244

u64 region_start,

sys/dev/pci/drm/i915/i915_syncmap.c

109

__sync_branch_idx(const struct i915_syncmap *p, u64 id)

sys/dev/pci/drm/i915/i915_syncmap.c

115

__sync_leaf_idx(const struct i915_syncmap *p, u64 id)

sys/dev/pci/drm/i915/i915_syncmap.c

121

static inline u64 __sync_branch_prefix(const struct i915_syncmap *p, u64 id)

sys/dev/pci/drm/i915/i915_syncmap.c

126

static inline u64 __sync_leaf_prefix(const struct i915_syncmap *p, u64 id)

sys/dev/pci/drm/i915/i915_syncmap.c

151

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

196

__sync_alloc_leaf(struct i915_syncmap *parent, u64 id)

sys/dev/pci/drm/i915/i915_syncmap.c

211

static inline void __sync_set_seqno(struct i915_syncmap *p, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

227

static noinline int __sync_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

350

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno)

sys/dev/pci/drm/i915/i915_syncmap.c

74

u64 prefix;

sys/dev/pci/drm/i915/i915_syncmap.h

34

int i915_syncmap_set(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/pci/drm/i915/i915_syncmap.h

35

bool i915_syncmap_is_later(struct i915_syncmap **root, u64 id, u32 seqno);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

233

(u64)bman->visible_avail << PAGE_SHIFT >> 20);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

235

(u64)bman->visible_size << PAGE_SHIFT >> 20);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

237

(u64)bman->visible_reserved << PAGE_SHIFT >> 20);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

25

u64 default_page_size;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

285

u64 size, u64 visible_size, u64 default_page_size,

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

286

u64 chunk_size)

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

371

u64 start, u64 size)

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

405

u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man)

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

422

u64 *avail, u64 *visible_avail)

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

43

u64 min_page_size;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

434

u64 size)

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

44

u64 size;

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

92

err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

93

(u64)lpfn << PAGE_SHIFT,

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.c

94

(u64)n_pages << PAGE_SHIFT,

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

54

u64 size, u64 visible_size,

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

55

u64 default_page_size, u64 chunk_size);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

60

u64 start, u64 size);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

62

u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

65

u64 *avail, u64 *avail_visible);

sys/dev/pci/drm/i915/i915_ttm_buddy_manager.h

69

u64 size);

sys/dev/pci/drm/i915/i915_user_extensions.c

26

u64 next;

sys/dev/pci/drm/i915/i915_utils.h

98

static inline bool is_power_of_2_u64(u64 n)

sys/dev/pci/drm/i915/i915_vgpu.c

66

u64 magic;

sys/dev/pci/drm/i915/i915_vma.c

1443

u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_vma.c

1632

int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_vma.c

193

GEM_BUG_ON(range_overflows_t(u64,

sys/dev/pci/drm/i915/i915_vma.c

1940

u64 vma_offset;

sys/dev/pci/drm/i915/i915_vma.c

698

u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_vma.c

799

u64 size, u64 alignment, u64 flags)

sys/dev/pci/drm/i915/i915_vma.c

802

u64 start, end;

sys/dev/pci/drm/i915/i915_vma.c

838

end = min_t(u64, end, i915_vm_to_ggtt(vma->vm)->mappable_end);

sys/dev/pci/drm/i915/i915_vma.c

840

end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE);

sys/dev/pci/drm/i915/i915_vma.c

863

u64 offset = flags & PIN_OFFSET_MASK;

sys/dev/pci/drm/i915/i915_vma.c

901

u64 page_alignment =

sys/dev/pci/drm/i915/i915_vma.h

133

static inline u64 __i915_vma_size(const struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

148

static inline u64 i915_vma_size(const struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

155

static inline u64 __i915_vma_offset(const struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

171

static inline u64 i915_vma_offset(const struct i915_vma *vma)

sys/dev/pci/drm/i915/i915_vma.h

264

u64 size, u64 alignment, u64 flags);

sys/dev/pci/drm/i915/i915_vma.h

294

u64 size, u64 alignment, u64 flags);

sys/dev/pci/drm/i915/i915_vma.h

297

i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags);

sys/dev/pci/drm/i915/i915_vma_resource.c

343

u64 *start,

sys/dev/pci/drm/i915/i915_vma_resource.c

344

u64 *end)

sys/dev/pci/drm/i915/i915_vma_resource.c

366

u64 offset,

sys/dev/pci/drm/i915/i915_vma_resource.c

367

u64 size,

sys/dev/pci/drm/i915/i915_vma_resource.c

371

u64 last = offset + size - 1;

sys/dev/pci/drm/i915/i915_vma_resource.c

41

u64, __subtree_last,

sys/dev/pci/drm/i915/i915_vma_resource.c

451

u64 offset,

sys/dev/pci/drm/i915/i915_vma_resource.c

452

u64 size,

sys/dev/pci/drm/i915/i915_vma_resource.c

457

u64 last = offset + size - 1;

sys/dev/pci/drm/i915/i915_vma_resource.h

108

u64 __subtree_last;

sys/dev/pci/drm/i915/i915_vma_resource.h

126

u64 start;

sys/dev/pci/drm/i915/i915_vma_resource.h

127

u64 node_size;

sys/dev/pci/drm/i915/i915_vma_resource.h

128

u64 vma_size;

sys/dev/pci/drm/i915/i915_vma_resource.h

211

u64 start,

sys/dev/pci/drm/i915/i915_vma_resource.h

212

u64 node_size,

sys/dev/pci/drm/i915/i915_vma_resource.h

213

u64 size,

sys/dev/pci/drm/i915/i915_vma_resource.h

244

u64 first,

sys/dev/pci/drm/i915/i915_vma_resource.h

245

u64 last,

sys/dev/pci/drm/i915/i915_vma_resource.h

250

u64 first,

sys/dev/pci/drm/i915/i915_vma_resource.h

251

u64 last,

sys/dev/pci/drm/i915/i915_vma_types.h

103

BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));

sys/dev/pci/drm/i915/i915_vma_types.h

152

u64 size;

sys/dev/pci/drm/i915/i915_wait_util.h

65

u64 base; \

sys/dev/pci/drm/i915/i915_wait_util.h

73

u64 now = local_clock(); \

sys/dev/pci/drm/i915/intel_memory_region.c

314

u64 *avail, u64 *visible_avail)

sys/dev/pci/drm/i915/intel_memory_region.c

396

u64 region_size, io_size;

sys/dev/pci/drm/i915/intel_memory_region.h

126

u64 *avail, u64 *visible_avail);

sys/dev/pci/drm/i915/intel_uncore.h

108

u64 (*mmio_readq)(struct intel_uncore *uncore,

sys/dev/pci/drm/i915/intel_uncore.h

458

static inline u64

sys/dev/pci/drm/i915/intel_uncore.h

485

return (u64)upper << 32 | lower;

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd_interface_43.h

32

u64 huc_base_address;

sys/dev/pci/drm/i915/pxp/intel_pxp_debugfs.c

39

static int pxp_terminate_get(void *data, u64 *val)

sys/dev/pci/drm/i915/pxp/intel_pxp_debugfs.c

45

static int pxp_terminate_set(void *data, u64 val)

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

170

u64 gsc_session_retry = 0;

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

57

u64 *gsc_msg_handle_retry)

sys/dev/pci/drm/i915/pxp/intel_pxp_types.h

48

u64 host_session_handle; /* used by firmware to link commands to sessions */

sys/dev/pci/drm/i915/selftests/i915_gem.c

46

const u64 slot = ggtt->error_capture.start;

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

236

u64 *start,

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

237

u64 *end)

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

377

const u64 PRETEND_GGTT_SIZE = 16ull << 20;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1005

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1083

u64 addr, u64 size, unsigned long flags)

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1088

u64 expected_vma_size, expected_node_size;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1148

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1155

u64 hole_size = hole_end - hole_start;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

116

fake_dma_object(struct drm_i915_private *i915, u64 size)

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1161

u64 min_alignment = i915_vm_min_alignment(vm, mr->type);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1162

u64 size = min_alignment;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1163

u64 addr = round_down(hole_start + (hole_size / 2), min_alignment);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1195

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1281

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1285

u64 hole_start, hole_end, last = 0;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1381

u64 offset = tmp.start + n * PAGE_SIZE;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1398

u64 offset = tmp.start + order[n] * PAGE_SIZE;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1409

u64 offset = tmp.start + order[n] * PAGE_SIZE;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1458

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1461

const u64 limit = totalram_pages() << PAGE_SHIFT;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1507

static int reserve_gtt_with_resource(struct i915_vma *vma, u64 offset)

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1540

u64 total;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

158

u64 size, last, limit;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1643

u64 offset;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1720

u64 size;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1721

u64 alignment;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1722

u64 start, end;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1733

-(u64)I915_GTT_PAGE_SIZE, 0,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1737

-(u64)2*I915_GTT_PAGE_SIZE, 2*I915_GTT_PAGE_SIZE,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1747

u64 total;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

1837

u64 offset;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

245

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

263

u64 hole_size, aligned_size;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

312

u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

371

u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

410

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

413

const u64 hole_size = hole_end - hole_start;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

418

min_t(u64, ULONG_MAX - 1, (hole_size / 2) >> ilog2(min_alignment));

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

433

const u64 full_size = npages << PAGE_SHIFT;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

436

u64 offset;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

456

u64 offset;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

460

u64 aligned_size = round_up(obj->base.size,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

500

u64 aligned_size = round_up(obj->base.size,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

539

u64 aligned_size = round_up(obj->base.size,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

579

u64 aligned_size = round_up(obj->base.size,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

636

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

639

const u64 hole_size = hole_end - hole_start;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

641

min_t(u64, ULONG_MAX - 1, hole_size >> PAGE_SHIFT);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

644

u64 size;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

657

u64 addr;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

719

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

749

u64 step = BIT_ULL(pot);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

750

u64 addr;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

794

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

813

u64 hole_size, aligned_size;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

858

u64 addr = hole_start + order[n] * BIT_ULL(aligned_size);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

905

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

914

u64 addr;

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

921

u64 size = BIT_ULL(order++);

sys/dev/pci/drm/i915/selftests/i915_gem_gtt.c

983

u64 hole_start, u64 hole_end,

sys/dev/pci/drm/i915/selftests/i915_perf.c

203

u64 expected;

sys/dev/pci/drm/i915/selftests/i915_random.c

34

u64 i915_prandom_u64_state(struct rnd_state *rnd)

sys/dev/pci/drm/i915/selftests/i915_random.c

36

u64 x;

sys/dev/pci/drm/i915/selftests/i915_random.c

92

u64 igt_random_offset(struct rnd_state *state,

sys/dev/pci/drm/i915/selftests/i915_random.c

93

u64 start, u64 end,

sys/dev/pci/drm/i915/selftests/i915_random.c

94

u64 len, u64 align)

sys/dev/pci/drm/i915/selftests/i915_random.c

96

u64 range, addr;

sys/dev/pci/drm/i915/selftests/i915_random.h

45

u64 i915_prandom_u64_state(struct rnd_state *rnd);

sys/dev/pci/drm/i915/selftests/i915_random.h

61

u64 igt_random_offset(struct rnd_state *state,

sys/dev/pci/drm/i915/selftests/i915_random.h

62

u64 start, u64 end,

sys/dev/pci/drm/i915/selftests/i915_random.h

63

u64 len, u64 align);

sys/dev/pci/drm/i915/selftests/i915_request.c

1920

u64 runtime;

sys/dev/pci/drm/i915/selftests/i915_request.c

1938

u64 sum;

sys/dev/pci/drm/i915/selftests/i915_request.c

1952

static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)

sys/dev/pci/drm/i915/selftests/i915_request.c

1954

u64 ns = intel_gt_clock_interval_to_ns(engine->gt, cycles);

sys/dev/pci/drm/i915/selftests/i915_request.c

2907

u64 busy, dt, now;

sys/dev/pci/drm/i915/selftests/i915_request.c

3264

u64 busy = 100 * ktime_to_ns(p->busy);

sys/dev/pci/drm/i915/selftests/i915_request.c

3265

u64 dt = ktime_to_ns(p->time);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

163

static int check_one(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

217

u64 context = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

238

static int check_leaf(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

297

u64 context = BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

346

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

363

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

385

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

414

u64 context = i915_prandom_u64_state(&prng) & ~MASK;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

469

u64 context = idx * BIT_ULL(order) + idx;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

562

u64 context = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

582

u64 context = i915_prandom_u64_state(&ctx);

sys/dev/pci/drm/i915/selftests/i915_vma.c

220

u64 size;

sys/dev/pci/drm/i915/selftests/i915_vma.c

221

u64 flags;

sys/dev/pci/drm/i915/selftests/i915_vma.c

749

u64 size,

sys/dev/pci/drm/i915/selftests/igt_mmap.c

13

u64 offset,

sys/dev/pci/drm/i915/selftests/igt_mmap.h

16

u64 offset,

sys/dev/pci/drm/i915/selftests/igt_spinner.c

112

static unsigned int seqno_offset(u64 fence)

sys/dev/pci/drm/i915/selftests/igt_spinner.c

117

static u64 hws_address(const struct i915_vma *hws,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1019

sizeof(u64),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1023

PAGE_SIZE - sizeof(u64),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

109

u64 size,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1154

create_region_for_mapping(struct intel_memory_region *mr, u64 size, u32 type,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1208

u64 size, u32 src_type, u32 dst_type)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

164

u64 allocated, cur_avail;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

183

u64 start = order[i] * chunk_size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

184

u64 size = i915_prandom_u32_max_state(chunk_size, &prng);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

246

u64 target;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

282

target = max_t(u64, PAGE_SIZE, target);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

377

u64 size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

458

u64 size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

525

static u64 igt_object_mappable_total(struct drm_i915_gem_object *obj)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

532

u64 total;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

536

u64 start = drm_buddy_block_offset(block);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

537

u64 end = start + drm_buddy_block_size(mm, block);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

540

total += min_t(u64, end, resource_size(&mr->io)) - start;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

551

u64 mappable_theft_total;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

552

u64 io_size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

553

u64 total;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

554

u64 ps;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

555

u64 rem;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

556

u64 size;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

567

total = max_t(u64, total, SZ_1G);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

571

io_size = max_t(u64, io_size, SZ_256M); /* 256M seems to be the common lower limit */

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

604

(u64)mappable_theft_total >> 20,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

605

(u64)io_size >> 20,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

606

(u64)total >> 20);

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

18

u64 timeslice;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

19

u64 preempt_timeout;

sys/dev/pci/drm/i915/selftests/librapl.c

20

u64 librapl_energy_uJ(void)

sys/dev/pci/drm/i915/selftests/librapl.h

15

u64 librapl_energy_uJ(void);

sys/dev/pci/drm/i915/selftests/mock_gtt.c

29

u64 offset,

sys/dev/pci/drm/i915/selftests/mock_gtt.c

61

u64 start, u64 length)

sys/dev/pci/drm/i915/soc/intel_gmch.c

67

u64 mchbar_addr;

sys/dev/pci/drm/i915/soc/intel_gmch.c

73

mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

sys/dev/pci/drm/include/drm/amd/isp.h

42

void **buf_obj, u64 *buf_addr);

sys/dev/pci/drm/include/drm/amd/isp.h

46

int isp_kernel_buffer_alloc(struct device *dev, u64 size,

sys/dev/pci/drm/include/drm/amd/isp.h

47

void **buf_obj, u64 *gpu_addr, void **cpu_addr);

sys/dev/pci/drm/include/drm/amd/isp.h

49

void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr);

sys/dev/pci/drm/include/drm/display/drm_hdcp_helper.h

20

void drm_hdcp_update_content_protection(struct drm_connector *connector, u64 val);

sys/dev/pci/drm/include/drm/display/drm_hdmi_audio_helper.h

17

u64 i2s_formats,

sys/dev/pci/drm/include/drm/drm_atomic.h

180

u64 last_vblank_count;

sys/dev/pci/drm/include/drm/drm_bridge.h

1116

u64 hdmi_audio_i2s_formats;

sys/dev/pci/drm/include/drm/drm_buddy.h

134

static inline u64

sys/dev/pci/drm/include/drm/drm_buddy.h

141

int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size);

sys/dev/pci/drm/include/drm/drm_buddy.h

149

u64 start, u64 end, u64 size,

sys/dev/pci/drm/include/drm/drm_buddy.h

150

u64 min_page_size,

sys/dev/pci/drm/include/drm/drm_buddy.h

155

u64 *start,

sys/dev/pci/drm/include/drm/drm_buddy.h

156

u64 new_size,

sys/dev/pci/drm/include/drm/drm_buddy.h

34

u64 header;

sys/dev/pci/drm/include/drm/drm_buddy.h

86

u64 chunk_size;

sys/dev/pci/drm/include/drm/drm_buddy.h

87

u64 size;

sys/dev/pci/drm/include/drm/drm_buddy.h

88

u64 avail;

sys/dev/pci/drm/include/drm/drm_buddy.h

89

u64 clear_avail;

sys/dev/pci/drm/include/drm/drm_buddy.h

92

static inline u64

sys/dev/pci/drm/include/drm/drm_color_mgmt.h

53

u64 drm_color_ctm_s31_32_to_qm_n(u64 user_input, u32 m, u32 n);

sys/dev/pci/drm/include/drm/drm_connector.h

2165

u64 epoch_counter;

sys/dev/pci/drm/include/drm/drm_drv.h

455

const char *region_name, u64 size);

sys/dev/pci/drm/include/drm/drm_file.h

285

u64 client_id;

sys/dev/pci/drm/include/drm/drm_file.h

513

u64 shared;

sys/dev/pci/drm/include/drm/drm_file.h

514

u64 private;

sys/dev/pci/drm/include/drm/drm_file.h

515

u64 resident;

sys/dev/pci/drm/include/drm/drm_file.h

516

u64 purgeable;

sys/dev/pci/drm/include/drm/drm_file.h

517

u64 active;

sys/dev/pci/drm/include/drm/drm_file.h

527

u64 sz);

sys/dev/pci/drm/include/drm/drm_fixed.h

161

u64 a_abs = a_neg ? -a : a;

sys/dev/pci/drm/include/drm/drm_fixed.h

162

u64 b_abs = b_neg ? -b : b;

sys/dev/pci/drm/include/drm/drm_fixed.h

163

u64 rem;

sys/dev/pci/drm/include/drm/drm_fixed.h

166

u64 res_abs = div64_u64_rem(a_abs, b_abs, &rem);

sys/dev/pci/drm/include/drm/drm_fixed.h

184

u64 summand = (rem << 1) >= b_abs;

sys/dev/pci/drm/include/drm/drm_fixed.h

199

u64 count = 1;

sys/dev/pci/drm/include/drm/drm_fixed.h

41

#define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12)

sys/dev/pci/drm/include/drm/drm_fixed.h

66

u64 tmp = ((u64)A.full << 13);

sys/dev/pci/drm/include/drm/drm_fourcc.h

311

u32 pixel_format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_gem.h

597

u32 handle, u64 *offset);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

102

u64 range;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1095

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1099

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

112

u64 offset;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1241

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1248

u64 req_addr, u64 req_range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1273

u64 *start_addr, u64 *range)

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1275

const u64 va_start = op->prev ?

sys/dev/pci/drm/include/drm/drm_gpuvm.h

1278

const u64 va_end = op->next ?

sys/dev/pci/drm/include/drm/drm_gpuvm.h

146

u64 __subtree_last;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

157

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

159

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

160

struct drm_gpuva *drm_gpuva_find_prev(struct drm_gpuvm *gpuvm, u64 start);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

161

struct drm_gpuva *drm_gpuva_find_next(struct drm_gpuvm *gpuvm, u64 end);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

246

u64 mm_start;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

251

u64 mm_range;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

340

u64 start_offset, u64 range,

sys/dev/pci/drm/include/drm/drm_gpuvm.h

341

u64 reserve_offset, u64 reserve_range,

sys/dev/pci/drm/include/drm/drm_gpuvm.h

363

bool drm_gpuvm_range_valid(struct drm_gpuvm *gpuvm, u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

364

bool drm_gpuvm_interval_empty(struct drm_gpuvm *gpuvm, u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

576

u64 addr, u64 range,

sys/dev/pci/drm/include/drm/drm_gpuvm.h

586

u64 addr, u64 range);

sys/dev/pci/drm/include/drm/drm_gpuvm.h

852

u64 addr;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

857

u64 range;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

867

u64 offset;

sys/dev/pci/drm/include/drm/drm_gpuvm.h

97

u64 addr;

sys/dev/pci/drm/include/drm/drm_mm.h

161

u64 start;

sys/dev/pci/drm/include/drm/drm_mm.h

163

u64 size;

sys/dev/pci/drm/include/drm/drm_mm.h

171

u64 __subtree_last;

sys/dev/pci/drm/include/drm/drm_mm.h

172

u64 hole_size;

sys/dev/pci/drm/include/drm/drm_mm.h

201

u64 *start, u64 *end);

sys/dev/pci/drm/include/drm/drm_mm.h

230

u64 size;

sys/dev/pci/drm/include/drm/drm_mm.h

231

u64 alignment;

sys/dev/pci/drm/include/drm/drm_mm.h

232

u64 remainder_mask;

sys/dev/pci/drm/include/drm/drm_mm.h

234

u64 range_start;

sys/dev/pci/drm/include/drm/drm_mm.h

235

u64 range_end;

sys/dev/pci/drm/include/drm/drm_mm.h

237

u64 hit_start;

sys/dev/pci/drm/include/drm/drm_mm.h

238

u64 hit_end;

sys/dev/pci/drm/include/drm/drm_mm.h

297

static inline u64 __drm_mm_hole_node_start(const struct drm_mm_node *hole_node)

sys/dev/pci/drm/include/drm/drm_mm.h

313

static inline u64 drm_mm_hole_node_start(const struct drm_mm_node *hole_node)

sys/dev/pci/drm/include/drm/drm_mm.h

319

static inline u64 __drm_mm_hole_node_end(const struct drm_mm_node *hole_node)

sys/dev/pci/drm/include/drm/drm_mm.h

335

static inline u64 drm_mm_hole_node_end(const struct drm_mm_node *hole_node)

sys/dev/pci/drm/include/drm/drm_mm.h

408

u64 size,

sys/dev/pci/drm/include/drm/drm_mm.h

409

u64 alignment,

sys/dev/pci/drm/include/drm/drm_mm.h

411

u64 start,

sys/dev/pci/drm/include/drm/drm_mm.h

412

u64 end,

sys/dev/pci/drm/include/drm/drm_mm.h

434

u64 size, u64 alignment,

sys/dev/pci/drm/include/drm/drm_mm.h

459

u64 size)

sys/dev/pci/drm/include/drm/drm_mm.h

465

void drm_mm_init(struct drm_mm *mm, u64 start, u64 size);

sys/dev/pci/drm/include/drm/drm_mm.h

482

__drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last);

sys/dev/pci/drm/include/drm/drm_mm.h

508

u64 size, u64 alignment, unsigned long color,

sys/dev/pci/drm/include/drm/drm_mm.h

509

u64 start, u64 end,

sys/dev/pci/drm/include/drm/drm_mm.h

533

u64 size,

sys/dev/pci/drm/include/drm/drm_mm.h

534

u64 alignment,

sys/dev/pci/drm/include/drm/drm_mode_config.h

99

const struct drm_format_info *(*get_format_info)(u32 pixel_format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_pagemap.h

245

u64 timeslice_expiration;

sys/dev/pci/drm/include/drm/drm_pagemap.h

40

u64 proto : 54;

sys/dev/pci/drm/include/drm/drm_pagemap.h

41

u64 order : 8;

sys/dev/pci/drm/include/drm/drm_pagemap.h

42

u64 dir : 2;

sys/dev/pci/drm/include/drm/drm_plane.h

567

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_plane.h

993

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_plane.h

995

u32 format, u64 modifier);

sys/dev/pci/drm/include/drm/drm_syncobj.h

127

u32 handle, u64 point, u64 flags,

sys/dev/pci/drm/include/drm/drm_vblank.h

262

u64 drm_crtc_vblank_count(struct drm_crtc *crtc);

sys/dev/pci/drm/include/drm/drm_vblank.h

263

u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,

sys/dev/pci/drm/include/drm/drm_vblank.h

271

u64 *seq,

sys/dev/pci/drm/include/drm/drm_vblank.h

284

u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);

sys/dev/pci/drm/include/drm/drm_vblank.h

54

u64 sequence;

sys/dev/pci/drm/include/drm/drm_vblank_work.h

41

u64 count;

sys/dev/pci/drm/include/drm/drm_vblank_work.h

66

u64 count, bool nextonmiss);

sys/dev/pci/drm/include/drm/gpu_scheduler.h

662

u64 drm_client_id);

sys/dev/pci/drm/include/drm/intel/intel-gtt.h

15

void intel_gmch_gtt_get(u64 *, phys_addr_t *, resource_size_t *);

sys/dev/pci/drm/include/drm/ttm/ttm_backup.h

68

u64 ttm_backup_bytes_avail(void);

sys/dev/pci/drm/include/linux/bits.h

61

((u64)(GENMASK_ULL(__high, __low) + \

sys/dev/pci/drm/include/linux/dma-fence-array.h

41

u64, unsigned, bool);

sys/dev/pci/drm/include/linux/io.h

129

static inline u64

sys/dev/pci/drm/include/linux/io.h

155

iowrite64(u64 val, volatile void __iomem *addr)

sys/dev/pci/drm/include/linux/io.h

73

static inline u64

sys/dev/pci/drm/include/linux/io.h

99

iowrite64(u64 val, volatile void __iomem *addr)

sys/dev/pci/drm/radeon/ci_dpm.c

1049

u64 tmp64;

sys/dev/pci/drm/radeon/ci_dpm.c

1060

tmp64 = (u64)duty * 100;

sys/dev/pci/drm/radeon/ci_dpm.c

1075

u64 tmp64;

sys/dev/pci/drm/radeon/ci_dpm.c

1092

tmp64 = (u64)speed * duty100;

sys/dev/pci/drm/radeon/ci_dpm.c

936

u64 tmp64;

sys/dev/pci/drm/radeon/ci_dpm.c

950

tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;

sys/dev/pci/drm/radeon/cik.c

3544

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/cik.c

3585

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/cik.c

4051

u64 rb_addr;

sys/dev/pci/drm/radeon/cik.c

4513

u64 hqd_gpu_addr;

sys/dev/pci/drm/radeon/cik.c

4514

u64 mqd_gpu_addr;

sys/dev/pci/drm/radeon/cik.c

4515

u64 eop_gpu_addr;

sys/dev/pci/drm/radeon/cik.c

4516

u64 wb_gpu_addr;

sys/dev/pci/drm/radeon/cik.c

5621

u64 tmp = RREG32(MC_VM_FB_OFFSET);

sys/dev/pci/drm/radeon/cik.c

9144

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/pci/drm/radeon/cik.c

9261

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/cik.c

9263

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/cik_sdma.c

203

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/cik_sdma.c

232

u64 addr = semaphore->gpu_addr;

sys/dev/pci/drm/radeon/cik_sdma.c

651

u64 gpu_addr;

sys/dev/pci/drm/radeon/cik_sdma.c

708

u64 gpu_addr;

sys/dev/pci/drm/radeon/evergreen.c

1416

void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base,

sys/dev/pci/drm/radeon/evergreen.c

2173

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/evergreen.c

2175

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/evergreen.c

4158

u64 reg_list_mc_addr;

sys/dev/pci/drm/radeon/evergreen_cs.c

1822

((u64)(tmp & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

1868

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

1903

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

1931

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2034

u64 size = pkt->opcode == PACKET3_DRAW_INDIRECT ? 16 : 20;

sys/dev/pci/drm/radeon/evergreen_cs.c

2104

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2116

u64 offset, tmp;

sys/dev/pci/drm/radeon/evergreen_cs.c

2157

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2195

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2251

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2273

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2295

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2494

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2501

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2513

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2520

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2533

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2545

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/evergreen_cs.c

2566

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2574

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2593

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2601

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2654

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2667

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2679

offset += ((u64)(radeon_get_ib_value(p, idx + 1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/evergreen_cs.c

2700

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2708

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2727

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2735

offset += ((u64)(radeon_get_ib_value(p, idx + 6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2895

u64 src_offset, dst_offset, dst2_offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

2929

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2961

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2963

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2990

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2996

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3020

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3022

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3062

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3064

dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3066

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3106

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3168

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3201

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3207

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3255

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3289

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/pci/drm/radeon/evergreen_cs.c

400

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

438

offset = (u64)track->cb_color_bo_offset[id] << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

445

offset += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

453

u64 tmp, nby, bsize, size, min = 0;

sys/dev/pci/drm/radeon/evergreen_cs.c

460

tmp = (u64)track->cb_color_bo_offset[id] << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

472

tmp += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

483

(u64)track->cb_color_bo_offset[id] << 8, mslice,

sys/dev/pci/drm/radeon/evergreen_cs.c

567

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

613

offset = (u64)track->db_s_read_offset << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

619

offset += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

624

(u64)track->db_s_read_offset << 8, mslice,

sys/dev/pci/drm/radeon/evergreen_cs.c

632

offset = (u64)track->db_s_write_offset << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

638

offset += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

643

(u64)track->db_s_write_offset << 8, mslice,

sys/dev/pci/drm/radeon/evergreen_cs.c

664

u64 offset;

sys/dev/pci/drm/radeon/evergreen_cs.c

711

offset = (u64)track->db_z_read_offset << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

717

offset += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

722

(u64)track->db_z_read_offset << 8, mslice,

sys/dev/pci/drm/radeon/evergreen_cs.c

727

offset = (u64)track->db_z_write_offset << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

733

offset += (u64)surf.layer_size * mslice;

sys/dev/pci/drm/radeon/evergreen_cs.c

738

(u64)track->db_z_write_offset << 8, mslice,

sys/dev/pci/drm/radeon/evergreen_cs.c

951

u64 offset = (u64)track->vgt_strmout_bo_offset[i] +

sys/dev/pci/drm/radeon/evergreen_cs.c

952

(u64)track->vgt_strmout_size[i];

sys/dev/pci/drm/radeon/evergreen_dma.c

44

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/ni.c

1380

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/ni.c

2484

u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);

sys/dev/pci/drm/radeon/ni_dpm.c

1395

u64 tmp, n, d;

sys/dev/pci/drm/radeon/ni_dpm.c

1420

n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);

sys/dev/pci/drm/radeon/ni_dpm.c

1421

d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);

sys/dev/pci/drm/radeon/ni_dpm.c

2011

u64 tmp;

sys/dev/pci/drm/radeon/ni_dpm.c

2025

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;

sys/dev/pci/drm/radeon/r100.c

164

void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/radeon/r100.c

2803

u64 config_aper_size;

sys/dev/pci/drm/radeon/r100.c

2858

u64 base;

sys/dev/pci/drm/radeon/r300.c

477

u64 base;

sys/dev/pci/drm/radeon/r600.c

1391

u64 size_bf, size_af;

sys/dev/pci/drm/radeon/r600.c

1422

u64 base = 0;

sys/dev/pci/drm/radeon/r600.c

2878

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/r600_cs.c

1216

track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1247

track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1283

track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1310

track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1477

u64 base_offset,

sys/dev/pci/drm/radeon/r600_cs.c

1478

u64 mip_offset,

sys/dev/pci/drm/radeon/r600_cs.c

1486

u64 base_align;

sys/dev/pci/drm/radeon/r600_cs.c

1680

((u64)(tmp & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1721

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1773

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1785

u64 offset, tmp;

sys/dev/pci/drm/radeon/r600_cs.c

1809

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1839

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1885

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1907

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

2099

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2112

offset = (u64)radeon_get_ib_value(p, idx+1) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

2146

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2153

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2166

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2173

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2187

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2199

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/r600_cs.c

2220

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2228

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2244

u64 offset;

sys/dev/pci/drm/radeon/r600_cs.c

2252

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2392

u64 src_offset, dst_offset;

sys/dev/pci/drm/radeon/r600_cs.c

2422

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2455

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2461

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2473

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2475

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2484

src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2486

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;

sys/dev/pci/drm/radeon/r600_cs.c

2517

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/pci/drm/radeon/r600_cs.c

252

u64 *base_align)

sys/dev/pci/drm/radeon/r600_cs.c

354

u64 base_offset, base_align;

sys/dev/pci/drm/radeon/r600_cs.c

49

u64 cb_color_bo_mc[8];

sys/dev/pci/drm/radeon/r600_cs.c

50

u64 cb_color_bo_offset[8];

sys/dev/pci/drm/radeon/r600_cs.c

52

u64 cb_color_frag_offset[8];

sys/dev/pci/drm/radeon/r600_cs.c

524

u64 base_offset, base_align;

sys/dev/pci/drm/radeon/r600_cs.c

54

u64 cb_color_tile_offset[8];

sys/dev/pci/drm/radeon/r600_cs.c

66

u64 vgt_strmout_bo_mc[4]; /* unused */

sys/dev/pci/drm/radeon/r600_cs.c

723

u64 offset = (u64)track->vgt_strmout_bo_offset[i] +

sys/dev/pci/drm/radeon/r600_cs.c

724

(u64)track->vgt_strmout_size[i];

sys/dev/pci/drm/radeon/r600_cs.c

76

u64 db_bo_mc;

sys/dev/pci/drm/radeon/r600_cs.c

82

u64 htile_offset;

sys/dev/pci/drm/radeon/r600_dma.c

236

u64 gpu_addr;

sys/dev/pci/drm/radeon/r600_dma.c

290

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/r600_dma.c

317

u64 addr = semaphore->gpu_addr;

sys/dev/pci/drm/radeon/r600_dma.c

343

u64 gpu_addr;

sys/dev/pci/drm/radeon/r600_dpm.c

520

u64 mask)

sys/dev/pci/drm/radeon/r600_dpm.c

528

enum r600_power_level index, u64 pins)

sys/dev/pci/drm/radeon/r600_dpm.c

542

u64 mask)

sys/dev/pci/drm/radeon/r600_dpm.h

191

u64 mask);

sys/dev/pci/drm/radeon/r600_dpm.h

193

enum r600_power_level index, u64 pins);

sys/dev/pci/drm/radeon/r600_dpm.h

195

u64 mask);

sys/dev/pci/drm/radeon/radeon.h

1999

void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);

sys/dev/pci/drm/radeon/radeon.h

2251

u64 gpu_addr;

sys/dev/pci/drm/radeon/radeon.h

2412

u64 fence_context;

sys/dev/pci/drm/radeon/radeon.h

2483

u64 vram_pin_size;

sys/dev/pci/drm/radeon/radeon.h

2484

u64 gart_pin_size;

sys/dev/pci/drm/radeon/radeon.h

2857

extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);

sys/dev/pci/drm/radeon/radeon.h

2862

extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);

sys/dev/pci/drm/radeon/radeon.h

651

u64 mc_vram_size;

sys/dev/pci/drm/radeon/radeon.h

652

u64 visible_vram_size;

sys/dev/pci/drm/radeon/radeon.h

653

u64 gtt_size;

sys/dev/pci/drm/radeon/radeon.h

654

u64 gtt_start;

sys/dev/pci/drm/radeon/radeon.h

655

u64 gtt_end;

sys/dev/pci/drm/radeon/radeon.h

656

u64 vram_start;

sys/dev/pci/drm/radeon/radeon.h

657

u64 vram_end;

sys/dev/pci/drm/radeon/radeon.h

659

u64 real_vram_size;

sys/dev/pci/drm/radeon/radeon.h

663

u64 gtt_base_align;

sys/dev/pci/drm/radeon/radeon.h

664

u64 mc_mask;

sys/dev/pci/drm/radeon/radeon.h

809

u64 next_rptr_gpu_addr;

sys/dev/pci/drm/radeon/radeon.h

824

u64 last_semaphore_signal_addr;

sys/dev/pci/drm/radeon/radeon.h

825

u64 last_semaphore_wait_addr;

sys/dev/pci/drm/radeon/radeon.h

837

u64 hpd_eop_gpu_addr;

sys/dev/pci/drm/radeon/radeon.h

923

u64 vram_base_offset;

sys/dev/pci/drm/radeon/radeon_asic.h

141

u64 crtc_base, bool async);

sys/dev/pci/drm/radeon/radeon_asic.h

253

u64 crtc_base, bool async);

sys/dev/pci/drm/radeon/radeon_asic.h

465

void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,

sys/dev/pci/drm/radeon/radeon_asic.h

536

u64 crtc_base, bool async);

sys/dev/pci/drm/radeon/radeon_cs.c

273

u64 size;

sys/dev/pci/drm/radeon/radeon_cs.c

890

(u64)relocs_chunk->kdata[idx + 3] << 32;

sys/dev/pci/drm/radeon/radeon_device.c

578

void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)

sys/dev/pci/drm/radeon/radeon_device.c

616

u64 size_af, size_bf;

sys/dev/pci/drm/radeon/radeon_fence.c

137

u64 seq;

sys/dev/pci/drm/radeon/radeon_fence.c

169

u64 seq;

sys/dev/pci/drm/radeon/radeon_fence.c

340

u64 seq, unsigned int ring)

sys/dev/pci/drm/radeon/radeon_fence.c

358

u64 seq = fence->seq;

sys/dev/pci/drm/radeon/radeon_fence.c

442

static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)

sys/dev/pci/drm/radeon/radeon_fence.c

471

u64 *target_seq, bool intr,

sys/dev/pci/drm/radeon/radeon_fence.c

929

static int radeon_debugfs_gpu_reset(void *data, u64 *val)

sys/dev/pci/drm/radeon/radeon_gem.c

393

args->vram_size = (u64)man->size << PAGE_SHIFT;

sys/dev/pci/drm/radeon/radeon_gem.c

938

args->size = (u64)args->pitch * args->height;

sys/dev/pci/drm/radeon/radeon_object.c

272

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,

sys/dev/pci/drm/radeon/radeon_object.c

273

u64 *gpu_addr)

sys/dev/pci/drm/radeon/radeon_object.c

287

u64 domain_start;

sys/dev/pci/drm/radeon/radeon_object.c

331

int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)

sys/dev/pci/drm/radeon/radeon_object.c

433

static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_object.c

435

u64 real_vram_size = rdev->mc.real_vram_size;

sys/dev/pci/drm/radeon/radeon_object.c

438

u64 vram_usage = ttm_resource_manager_usage(man);

sys/dev/pci/drm/radeon/radeon_object.c

479

u64 half_vram = real_vram_size >> 1;

sys/dev/pci/drm/radeon/radeon_object.c

480

u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;

sys/dev/pci/drm/radeon/radeon_object.c

481

u64 bytes_moved_threshold = half_free_vram >> 1;

sys/dev/pci/drm/radeon/radeon_object.c

491

u64 bytes_moved = 0, initial_bytes_moved;

sys/dev/pci/drm/radeon/radeon_object.c

492

u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);

sys/dev/pci/drm/radeon/radeon_object.h

131

static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)

sys/dev/pci/drm/radeon/radeon_object.h

146

extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);

sys/dev/pci/drm/radeon/radeon_object.h

148

u64 max_offset, u64 *gpu_addr);

sys/dev/pci/drm/radeon/radeon_object.h

91

static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)

sys/dev/pci/drm/radeon/radeon_object.h

94

u64 start = 0;

sys/dev/pci/drm/radeon/radeon_trace.h

111

__field(u64, pd_addr)

sys/dev/pci/drm/radeon/radeon_trace.h

69

__field(u64, soffset)

sys/dev/pci/drm/radeon/radeon_trace.h

70

__field(u64, eoffset)

sys/dev/pci/drm/radeon/radeon_trace.h

88

__field(u64, pe)

sys/dev/pci/drm/radeon/radeon_trace.h

89

__field(u64, addr)

sys/dev/pci/drm/radeon/radeon_ttm.c

154

old_start = (u64)old_mem->start << PAGE_SHIFT;

sys/dev/pci/drm/radeon/radeon_ttm.c

155

new_start = (u64)new_mem->start << PAGE_SHIFT;

sys/dev/pci/drm/radeon/radeon_ttm.c

322

u64 offset;

sys/dev/pci/drm/radeon/radeon_ttm.c

351

unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;

sys/dev/pci/drm/radeon/radeon_ttm.c

373

(u64)ttm->num_pages << PAGE_SHIFT,

sys/dev/pci/drm/radeon/radeon_ttm.c

801

void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)

sys/dev/pci/drm/radeon/radeon_vm.c

946

addr = (u64)mem->start << PAGE_SHIFT;

sys/dev/pci/drm/radeon/rs400.c

283

u64 base;

sys/dev/pci/drm/radeon/rs600.c

119

void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/radeon/rs600.c

881

u64 base;

sys/dev/pci/drm/radeon/rs690.c

152

u64 base;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

937

static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

940

u64 master_mask = 0;

sys/dev/pci/drm/radeon/rv730_dpm.c

48

u64 tmp;

sys/dev/pci/drm/radeon/rv730_dpm.c

67

tmp = (u64) engine_clock * reference_divider * post_divider * 16384;

sys/dev/pci/drm/radeon/rv740_dpm.c

129

u64 tmp;

sys/dev/pci/drm/radeon/rv740_dpm.c

142

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/pci/drm/radeon/rv770.c

1605

u64 size_bf, size_af;

sys/dev/pci/drm/radeon/rv770.c

800

void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)

sys/dev/pci/drm/radeon/rv770_dpm.c

501

u64 tmp;

sys/dev/pci/drm/radeon/rv770_dpm.c

519

tmp = (u64) engine_clock * reference_divider * post_divider * 16384;

sys/dev/pci/drm/radeon/si.c

2211

tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);

sys/dev/pci/drm/radeon/si.c

2291

active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,

sys/dev/pci/drm/radeon/si.c

2293

line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,

sys/dev/pci/drm/radeon/si.c

3354

u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

sys/dev/pci/drm/radeon/si_dpm.c

2192

u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;

sys/dev/pci/drm/radeon/si_dpm.c

2193

u64 prev_vddc = (u64)prev_std_vddc;

sys/dev/pci/drm/radeon/si_dpm.c

2194

u64 curr_vddc = (u64)curr_std_vddc;

sys/dev/pci/drm/radeon/si_dpm.c

2195

u64 pwr_efficiency_ratio, n, d;

sys/dev/pci/drm/radeon/si_dpm.c

2200

n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);

sys/dev/pci/drm/radeon/si_dpm.c

2204

if (pwr_efficiency_ratio > (u64)0xFFFF)

sys/dev/pci/drm/radeon/si_dpm.c

4739

u64 tmp;

sys/dev/pci/drm/radeon/si_dpm.c

4752

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/pci/drm/radeon/si_dpm.c

5982

u64 tmp64;

sys/dev/pci/drm/radeon/si_dpm.c

5996

tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;

sys/dev/pci/drm/radeon/si_dpm.c

6083

u64 tmp64;

sys/dev/pci/drm/radeon/si_dpm.c

6094

tmp64 = (u64)duty * 100;

sys/dev/pci/drm/radeon/si_dpm.c

6110

u64 tmp64;

sys/dev/pci/drm/radeon/si_dpm.c

6126

tmp64 = (u64)speed * duty100;

sys/dev/pci/drm/radeon/trinity_dpm.c

1590

u64 disp_clk = rdev->clock.default_dispclk / 100;

sys/dev/pci/drm/radeon/trinity_dpm.c

1596

dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

100

__field(u64, fence_context)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

101

__field(u64, fence_seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

116

__field(u64, fence_context)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

117

__field(u64, fence_seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

118

__field(u64, ctx)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

119

__field(u64, seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

137

__field(u64, fence_context)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

138

__field(u64, fence_seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

139

__field(u64, ctx)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

140

__field(u64, seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

65

__field(u64, fence_context)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

66

__field(u64, fence_seqno)

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

67

__field(u64, client_id)

sys/dev/pci/drm/scheduler/sched_fence.c

231

u64 drm_client_id)

sys/dev/pci/drm/scheduler/sched_internal.h

27

void *owner, u64 drm_client_id);

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

34

u64 lpfn, fpfn, alloc_size;

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.h

13

u64 default_page_size;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

115

u64 expected_usage;

sys/dev/pci/drm/ttm/tests/ttm_resource_test.c

233

u64 actual_usage;

sys/dev/pci/drm/ttm/ttm_backup.c

170

u64 ttm_backup_bytes_avail(void)

sys/dev/pci/drm/ttm/ttm_backup.c

179

return (u64)get_nr_swap_pages() << PAGE_SHIFT;

sys/dev/pci/if_mcx.c

3162

mcx_mix_u64(uint32_t xor, uint64_t u64)

sys/dev/pci/if_mcx.c

3164

xor ^= u64 >> 32;

sys/dev/pci/if_mcx.c

3165

xor ^= u64;

usr.sbin/smtpd/mta.c

195

uint64_t u64;

usr.sbin/smtpd/mta.c

311

u64 = *((uint64_t *)imsg->data);

usr.sbin/smtpd/mta.c

312

if (u64)

usr.sbin/smtpd/mta.c

314

(unsigned long long)u64);

usr.sbin/smtpd/mta.c

318

if (u64 && route->id != u64)

usr.sbin/smtpd/mta.c

335

if (u64)