Symbol: tile
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1000
uint32_t *tile, *macrotile;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1002
tile = adev->gfx.config.tile_mode_array;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1019
tile[reg_offset] = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1025
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1029
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1033
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1037
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1041
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1045
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1048
tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1052
tile[7] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1053
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1055
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1058
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1062
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1066
tile[12] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1067
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1070
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1074
tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1078
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1082
tile[17] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1083
tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1087
tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1090
tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1094
tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1098
tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1102
tile[23] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1103
tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1107
tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1111
tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1115
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1118
tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1122
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1126
tile[30] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1186
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1192
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1196
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1200
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1204
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1208
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1212
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1216
tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1220
tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1224
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1226
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1229
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1233
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1237
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1241
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1244
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1248
tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1252
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1256
tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1260
tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1264
tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1267
tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1271
tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1275
tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1279
tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1283
tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1287
tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1291
tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1295
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1298
tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1302
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1306
tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1369
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1378
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1382
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1386
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1390
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1394
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1398
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1401
tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1405
tile[7] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1406
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1408
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1411
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1415
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1419
tile[12] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1420
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1423
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1427
tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1431
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1435
tile[17] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1436
tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1440
tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1443
tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1447
tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1451
tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1455
tile[23] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1456
tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1460
tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1464
tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1468
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1471
tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1475
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1479
tile[30] = (TILE_SPLIT(split_equal_to_row_size));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
1539
WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h
242
#define ISP_TILE_SEL(tile) (1<<tile)
sys/dev/pci/drm/drm_connector.c
2767
char tile[256];
sys/dev/pci/drm/drm_connector.c
2780
snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d",
sys/dev/pci/drm/drm_connector.c
2788
strlen(tile) + 1,
sys/dev/pci/drm/drm_connector.c
2789
tile,
sys/dev/pci/drm/drm_edid.c
7541
const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
sys/dev/pci/drm/drm_edid.c
7555
w = tile->tile_size[0] | tile->tile_size[1] << 8;
sys/dev/pci/drm/drm_edid.c
7556
h = tile->tile_size[2] | tile->tile_size[3] << 8;
sys/dev/pci/drm/drm_edid.c
7558
num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
sys/dev/pci/drm/drm_edid.c
7559
num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
sys/dev/pci/drm/drm_edid.c
7560
tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
sys/dev/pci/drm/drm_edid.c
7561
tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
sys/dev/pci/drm/drm_edid.c
7564
if (tile->tile_cap & 0x80)
sys/dev/pci/drm/drm_edid.c
7577
tile->tile_cap,
sys/dev/pci/drm/drm_edid.c
7581
tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
sys/dev/pci/drm/drm_edid.c
7583
tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
sys/dev/pci/drm/drm_edid.c
7585
tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
sys/dev/pci/drm/i915/display/intel_fb.c
1817
unsigned int stride, tile;
sys/dev/pci/drm/i915/display/intel_fb.c
1826
tile = intel_tile_height(fb, color_plane);
sys/dev/pci/drm/i915/display/intel_fb.c
1828
tile = intel_tile_width_bytes(fb, color_plane);
sys/dev/pci/drm/i915/display/intel_fb.c
1830
vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
108
err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
111
tile->tiling, tile->stride, err);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
115
GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
116
GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
151
offset = tiled_offset(tile, page << PAGE_SHIFT);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
166
tile->tiling ? tile_row_pages(obj) : 0,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
167
vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
186
const struct tile *tile,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
196
err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
199
tile->tiling, tile->stride, err);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
203
GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
204
GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
247
offset = tiled_offset(tile, page << PAGE_SHIFT);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
262
tile->tiling ? tile_row_pages(obj) : 0,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
263
vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
282
__func__, tile->tiling, tile->stride))
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
290
setup_tile_size(struct tile *tile, struct drm_i915_private *i915)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
293
tile->height = 16;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
294
tile->width = 128;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
295
tile->size = 11;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
296
} else if (tile->tiling == I915_TILING_Y &&
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
298
tile->height = 32;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
299
tile->width = 128;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
300
tile->size = 12;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
302
tile->height = 8;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
303
tile->width = 512;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
304
tile->size = 12;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
308
return 8192 / tile->width;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
310
return 128 * I965_FENCE_MAX_PITCH_VAL / tile->width;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
312
return 128 * GEN7_FENCE_MAX_PITCH_VAL / tile->width;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
352
struct tile tile;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
354
tile.height = 1;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
355
tile.width = 1;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
356
tile.size = 0;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
357
tile.stride = 0;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
358
tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
359
tile.tiling = I915_TILING_NONE;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
361
err = check_partial_mappings(obj, &tile, end);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
370
struct tile tile;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
380
tile.tiling = tiling;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
383
tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
386
tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
390
GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
391
if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
392
tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
395
max_pitch = setup_tile_size(&tile, i915);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
398
tile.stride = tile.width * pitch;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
399
err = check_partial_mappings(obj, &tile, end);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
406
tile.stride = tile.width * (pitch - 1);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
407
err = check_partial_mappings(obj, &tile, end);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
415
tile.stride = tile.width * (pitch + 1);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
416
err = check_partial_mappings(obj, &tile, end);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
426
tile.stride = tile.width * pitch;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
427
err = check_partial_mappings(obj, &tile, end);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
44
static u64 tiled_offset(const struct tile *tile, u64 v)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
48
if (tile->tiling == I915_TILING_NONE)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
489
struct tile tile;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
491
tile.tiling =
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
493
switch (tile.tiling) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
495
tile.height = 1;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
496
tile.width = 1;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
497
tile.size = 0;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
498
tile.stride = 0;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
499
tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
503
tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
506
tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
51
y = div64_u64_rem(v, tile->stride, &x);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
510
if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
511
tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
514
if (tile.tiling != I915_TILING_NONE) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
515
unsigned int max_pitch = setup_tile_size(&tile, i915);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
517
tile.stride =
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
519
tile.stride = (1 + tile.stride) * tile.width;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
52
v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
521
tile.stride = rounddown_pow_of_two(tile.stride);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
524
err = check_partial_mapping(obj, &tile, &prng);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
54
if (tile->tiling == I915_TILING_X) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
55
v += y * tile->width;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
56
v += div64_u64_rem(x, tile->width, &x) << tile->size;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
58
} else if (tile->width == 128) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
74
switch (tile->swizzle) {
sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c
93
const struct tile *tile,
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1397
u32 stride, tile;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1404
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1409
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1415
if (tile != info->tile_val)
sys/dev/pci/drm/radeon/cik.c
2322
u32 *tile = rdev->config.cik.tile_mode_array;
sys/dev/pci/drm/radeon/cik.c
2351
tile[reg_offset] = 0;
sys/dev/pci/drm/radeon/cik.c
2357
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2361
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2365
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2369
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2373
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2377
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2380
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2384
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2388
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/cik.c
2390
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2393
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2397
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2401
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2405
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2408
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2412
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2416
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2420
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2423
tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2427
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2431
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2494
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2500
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2504
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2508
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2512
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2516
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2520
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2523
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2527
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2531
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/cik.c
2533
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2536
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2540
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2544
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2548
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2551
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2555
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2559
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2563
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2566
tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2570
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2574
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2637
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2644
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2648
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2652
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2656
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2660
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2664
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2667
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2671
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2675
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/cik.c
2677
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2680
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2684
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2688
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2692
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2695
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2699
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2703
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2707
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2710
tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2714
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2718
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2724
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2728
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2732
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2736
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2740
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2744
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2747
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2751
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2755
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/cik.c
2757
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2760
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2764
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2768
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2772
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2775
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2779
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2783
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2787
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2790
tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2794
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2798
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2862
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/cik.c
2868
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2872
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2876
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2880
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2884
tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2888
tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2891
tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2895
tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2899
tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/cik.c
2901
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2904
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2908
tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2912
tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2916
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2919
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2923
tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2927
tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2931
tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2934
tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2938
tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
2942
tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/cik.c
3005
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/si.c
2471
u32 *tile = rdev->config.si.tile_mode_array;
sys/dev/pci/drm/radeon/si.c
2490
tile[reg_offset] = 0;
sys/dev/pci/drm/radeon/si.c
2496
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2505
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2514
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2523
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2532
tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2541
tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2550
tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2559
tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2568
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/si.c
2577
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2586
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2595
tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2604
tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2613
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2622
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2631
tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2640
tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2649
tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2658
tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2667
tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2676
tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2685
tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2694
tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2704
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
sys/dev/pci/drm/radeon/si.c
2711
tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2720
tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2729
tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2738
tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2747
tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2756
tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2765
tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2774
tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2783
tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
sys/dev/pci/drm/radeon/si.c
2792
tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2801
tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2810
tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2819
tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2828
tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2837
tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2846
tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2855
tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2864
tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2873
tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2882
tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2891
tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2900
tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2909
tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
sys/dev/pci/drm/radeon/si.c
2919
WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);