sys/dev/pci/drm/i915/display/icl_dsi.c

1396

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/icl_dsi.c

1398

ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

sys/dev/pci/drm/i915/display/icl_dsi.c

535

intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);

sys/dev/pci/drm/i915/display/icl_dsi.c

537

ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

sys/dev/pci/drm/i915/display/intel_ddi.c

1548

intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);

sys/dev/pci/drm/i915/display/intel_ddi.c

1549

intel_de_posting_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

193

return DDI_BUF_CTL(port);

sys/dev/pci/drm/i915/display/intel_ddi.c

2563

reg = DDI_BUF_CTL(port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3065

reg = DDI_BUF_CTL(port);

sys/dev/pci/drm/i915/display/intel_ddi.c

3089

intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);

sys/dev/pci/drm/i915/display/intel_ddi.c

3090

intel_de_posting_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

3101

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_ddi.c

4643

dig_port->dp.output_reg = DDI_BUF_CTL(port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4846

dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);

sys/dev/pci/drm/i915/display/intel_ddi.c

4891

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_ddi.c

5032

return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5331

ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

818

tmp = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_display.c

7743

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_fdi.c

903

intel_de_write(display, DDI_BUF_CTL(PORT_E),

sys/dev/pci/drm/i915/display/intel_fdi.c

907

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

950

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_fdi.c

951

intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

985

intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);

sys/dev/pci/drm/i915/display/intel_tc.c

1575

return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &

sys/dev/pci/drm/i915/display/intel_tc.c

877

intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,

sys/dev/pci/drm/i915/display/intel_tc.c

891

val = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/gvt/display.c

231

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=

sys/dev/pci/drm/i915/gvt/display.c

234

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

sys/dev/pci/drm/i915/gvt/display.c

294

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=

sys/dev/pci/drm/i915/gvt/display.c

296

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=

sys/dev/pci/drm/i915/gvt/display.c

324

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=

sys/dev/pci/drm/i915/gvt/display.c

326

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=

sys/dev/pci/drm/i915/gvt/display.c

355

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=

sys/dev/pci/drm/i915/gvt/display.c

357

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=

sys/dev/pci/drm/i915/gvt/display.c

437

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

438

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

sys/dev/pci/drm/i915/gvt/display.c

463

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

464

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

sys/dev/pci/drm/i915/gvt/display.c

489

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

490

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

sys/dev/pci/drm/i915/gvt/display.c

509

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

sys/dev/pci/drm/i915/gvt/handlers.c

2370

MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2371

MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2372

MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2373

MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

2374

MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);

sys/dev/pci/drm/i915/gvt/handlers.c

817

if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))

sys/dev/pci/drm/i915/gvt/handlers.c

836

u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

529

MMIO_D(DDI_BUF_CTL(PORT_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

530

MMIO_D(DDI_BUF_CTL(PORT_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

531

MMIO_D(DDI_BUF_CTL(PORT_C));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

532

MMIO_D(DDI_BUF_CTL(PORT_D));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

533

MMIO_D(DDI_BUF_CTL(PORT_E));