sts
sts(inst.float_detail.fb, &sfb, p);
sts(inst.float_detail.fb, &sfb, p);
sts(inst.float_detail.fa, &sfa, p);
sts = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS);
printf(": iid %d revision %d wdstatus %b\n", iid, rev, sts, WDSTSBITS);
sts |= WDOVF_CLEAR;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS, sts);
uint8_t sts, rev, iid;
sts.l pr, @-r14 /* tf_pr */ ;\
sts.l mach, @-r14 /* tf_mach*/ ;\
sts.l macl, @-r14 /* tf_macl*/ ;\
uint16_t sts, en;
sts = acpi_read_pmreg(sc, ACPIREG_GPE_STS, idx>>3);
if (en & sts) {
dnprintf(10, "GPE block: %.2x %.2x %.2x\n", idx, sts,
acpi_write_pmreg(sc, ACPIREG_GPE_EN, idx>>3, en & ~sts);
if (!(en & sts & (1L << jdx)))
sts = acpi_read_pmreg(sc, ACPIREG_PM1_STS, 0);
if (sts & en) {
dnprintf(10,"GEN interrupt: %.4x\n", sts & en);
sts &= en;
if (sts & ACPI_PM1_PWRBTN_STS) {
sts &= ~ACPI_PM1_PWRBTN_STS;
if (sts & ACPI_PM1_SLPBTN_STS) {
sts &= ~ACPI_PM1_SLPBTN_STS;
if (sts & ACPI_PM1_RTC_STS) {
sts &= ~ACPI_PM1_RTC_STS;
if (sts) {
sc->sc_dev.dv_xname, en, sts);
acpi_write_pmreg(sc, ACPIREG_PM1_EN, 0, en & ~sts);
acpi_write_pmreg(sc, ACPIREG_PM1_STS, 0, sts);
int i, sts;
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
if (sts & GSTS_RTPS)
int i, sts;
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
if (sts & GSTS_WBFS)
uint64_t cmd, iva, sts;
sts = iommu_read_8(iommu, DMAR_IOTLB_REG(iommu));
if ((sts & IOTLB_IVT) == 0)
if (sts & IOTLB_IVT)
int sts;
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
if (sts & GSTS_QIES)
if (!(sts & GSTS_QIES)) {
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
if ((sts & GSTS_QIES) == 0)
if (sts & GSTS_QIES)
uint32_t sts;
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
} while (n++ < 5 && !(sts & GSTS_TES));
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
} while (n++ < 5 && (sts & GSTS_TES));
uint32_t sts;
sts = iommu_read_4(iommu, DMAR_FECTL_REG);
iommu_write_4(iommu, DMAR_FECTL_REG, sts & ~FECTL_IM);
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
if (sts & GSTS_TES)
if (sts & GSTS_QIES)
if (sts & GSTS_IRES)
uint32_t sts;
sts = iommu_read_4(iommu, DMAR_FECTL_REG);
sts = iommu_read_4(iommu, DMAR_FSTS_REG);
if (!(sts & FSTS_PPF)) {
fri = (sts >> FSTS_FRI_SHIFT) & FSTS_FRI_MASK;
int i, j, sts, cmd;
sts = iommu_read_4(iommu, DMAR_GSTS_REG);
sts & GSTS_TES ? "enabled" : "disabled",
sts & GSTS_QIES ? "qi" : "ccmd",
sts & GSTS_IRES ? "ir" : "",
cmd, sts);
uint32_t sts;
sc->sc_addr + PON_RT_STS, &sts, sizeof(sts));
(sts & PON_PMK8350_KPDPWR_N_SET) == 0)
sc->sc_last_sts = sts;
uint32_t did, sts;
sts = bus_space_read_4(sc->sc.iot, sc->sc_otg_ioh, OTG_STS);
if (sts & OTG_STS_XHCI_READY)
int sts, v;
sts = smic_wait(sc, SMIC_TX_DATA_RDY | SMIC_BUSY, SMIC_TX_DATA_RDY,
if (sts < 0)
return (sts);
int sts;
sts = smic_wait(sc, SMIC_RX_DATA_RDY | SMIC_BUSY, SMIC_RX_DATA_RDY,
if (sts >= 0) {
return (sts);
int sts, idx;
sts = smic_write_cmd_data(sc, SMS_CC_START_TRANSFER, &sc->sc_buf[0]);
ErrStat(sts != SMS_SC_WRITE_START, "wstart");
sts = smic_write_cmd_data(sc, SMS_CC_NEXT_TRANSFER,
ErrStat(sts != SMS_SC_WRITE_NEXT, "write");
sts = smic_write_cmd_data(sc, SMS_CC_END_TRANSFER, &sc->sc_buf[idx]);
if (sts != SMS_SC_WRITE_END) {
dbg_printf(50, "smic_sendmsg %d/%d = %.2x\n", idx, c->c_txlen, sts);
int sts, idx;
sts = smic_wait(sc, SMIC_RX_DATA_RDY, SMIC_RX_DATA_RDY, "smic_recvmsg");
if (sts < 0)
sts = smic_write_cmd_data(sc, SMS_CC_START_RECEIVE, NULL);
ErrStat(sts != SMS_SC_READ_START, "rstart");
sts = smic_read_data(sc, &sc->sc_buf[idx++]);
if (sts != SMS_SC_READ_START && sts != SMS_SC_READ_NEXT)
ErrStat(sts != SMS_SC_READ_END, "rend");
sts = smic_write_cmd_data(sc, SMS_CC_END_RECEIVE, NULL);
if (sts != SMS_SC_READY) {
dbg_printf(50, "smic_recvmsg %d/%d = %.2x\n", idx, c->c_maxrxlen, sts);
int sts;
sts = kcs_wait(sc, KCS_IBF | KCS_OBF, KCS_OBF, "read_data");
if (sts != KCS_READ_STATE)
return (sts);
return (sts);
int idx, sts;
sts = kcs_write_cmd(sc, KCS_WRITE_START);
sts = kcs_write_cmd(sc, KCS_WRITE_END);
if (sts != KCS_WRITE_STATE)
sts = kcs_write_data(sc, sc->sc_buf[idx]);
if (sts != KCS_READ_STATE) {
dbg_printf(1, "kcs sendmsg = %d/%d <%.2x>\n", idx, c->c_txlen, sts);
int idx, sts;
sts = kcs_read_data(sc, &sc->sc_buf[idx]);
if (sts != KCS_READ_STATE)
sts = kcs_wait(sc, KCS_IBF, 0, "recv");
if (sts != KCS_IDLE_STATE) {
dbg_printf(1, "kcs recvmsg = %d/%d <%.2x>\n", idx, c->c_maxrxlen, sts);
uint32_t sts;
sts = READ2(sc, chan->port + ALI_OFF_SR);
WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
if (sts & ALI_SR_DMA_INT_FIFO) {
if (sts & AUICH_BCIS)
sts + (AUICH_BCIS | AUICH_FIFOE));
uint16_t sts;
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS));
uint16_t sts, osts;
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
sc->sc_dev.dv_xname, wait_us, sts,
if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI))
if (sts != osts) {
sc->sc_dev.dv_xname, wait_us, sts,
osts = sts;
sc->sc_dev.dv_xname, wait_us, sts,
sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ));
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ);
uint32_t sts;
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE))
if (sts & AUICH_DCH)
int ret = 0, sts, gsts;
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS));
if (sts & AUICH_FIFOE) {
if (sts & AUICH_BCIS)
AUICH_PCMO + sc->sc_sts_reg, sts &
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS));
if (sts & AUICH_FIFOE) {
if (sts & AUICH_BCIS)
AUICH_PCMI + sc->sc_sts_reg, sts &
sts = bus_space_read_2(sc->iot, sc->aud_ioh,
("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS));
if (sts & AUICH_FIFOE) {
uint8_t sts;
sts = STR_READ_1(this, STS);
sts |= HDA_SD_STS_DESE | HDA_SD_STS_FIFOE | HDA_SD_STS_BCIS;
STR_WRITE_1(this, STS, sts);
u_int8_t sts;
sts = STR_READ_1(this, STS);
STR_WRITE_1(this, STS, sts |
if (sts & (HDA_SD_STS_DESE | HDA_SD_STS_FIFOE))
this->number, sts, HDA_SD_STS_BITS));
if (sts & HDA_SD_STS_BCIS) {
volatile struct myx_status *sts = sc->sc_sts;
sc->sc_linkdown = sts->ms_linkdown;
sleep_setup(sts, PWAIT, "myxdown");
volatile struct myx_status *sts = sc->sc_sts;
valid = sts->ms_isvalid;
sts->ms_isvalid = 0;
data = sts->ms_txdonecnt;
} while (sts->ms_isvalid);
if (sts->ms_statusupdated) {
sc->sc_linkdown != sts->ms_linkdown) {
wakeup(sts);
data = sts->ms_linkstate;
volatile struct myx_status *sts = sc->sc_sts;
bemtoh32((uint32_t *)((uint8_t *)sts + mc->mc_offset));
bemtoh32(&sts->ms_rdmatags_available);
u_int32_t sts;
sts = sc->sc_sts->ms_linkstate;
myx_link_state(sc, sts);
myx_link_state(struct myx_softc *sc, u_int32_t sts)
if (betoh32(sts) == MYXSTS_LINKUP)
u_int8_t sts;
sts = nviic_read(nc, NVI_SMB_STS);
if (sts & NVI_SMB_STS_STATUS)
u_int pos, sts, fifo_avail, chunk;
sts = cfxga_read_1(sc, CFREG_BITBLT_CONTROL);
if ((sts & BITBLT_FIFO_NOT_EMPTY) == 0)
else if ((sts & BITBLT_FIFO_HALF_FULL) == 0)
u_int8_t sts, ctrl;
sts = FBC_READ(sc, CG3_FBC_STAT);
(sts & (FBC_STAT_RES | FBC_STAT_ID)))) {
int s, sts;
sts = udav_csr_read1(sc, UDAV_NSR) & UDAV_NSR_LINKST;
if (!sts)
sts = (mii->mii_media_status & IFM_ACTIVE &&
if (!sc->sc_link && sts) {
strstatus(int sts)
switch (sts) {
struct timespec ts = {TIMO, 0}, sts = {0, 0};
if (kevent(kq, ev, nchanges, NULL, 0, &sts) == -1)
sts = ts;
if ((rv = kevent(kq, NULL, 0, ev, 1, &sts)) == -1)
bool_t sts = 0;
if ((sts = svc_register(transp, prog, 1,
if (!sts) {