sys/dev/pci/drm/radeon/evergreen_cs.c

1153

track->db_depth_control = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1171

track->db_z_info = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1199

track->db_s_info = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1203

track->db_depth_view = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1207

track->db_depth_size = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1211

track->db_depth_slice = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1221

track->db_z_read_offset = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1233

track->db_z_write_offset = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1245

track->db_s_read_offset = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1257

track->db_s_write_offset = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1263

track->vgt_strmout_config = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1267

track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1281

track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/evergreen_cs.c

1292

track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;

sys/dev/pci/drm/radeon/evergreen_cs.c

1305

track->cb_target_mask = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1309

track->cb_shader_mask = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1318

tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;

sys/dev/pci/drm/radeon/evergreen_cs.c

1327

tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;

sys/dev/pci/drm/radeon/evergreen_cs.c

1339

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1347

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1359

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1377

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1399

track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1407

track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1419

track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1428

track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1535

track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1546

track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1563

track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1579

track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1591

track->htile_offset = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1598

track->htile_surface = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1740

track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;

sys/dev/pci/drm/radeon/evergreen_cs.c

1788

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

1802

tmp = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/evergreen_cs.c

1868

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

1903

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

1930

radeon_get_ib_value(p, idx+1) +

sys/dev/pci/drm/radeon/evergreen_cs.c

1931

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2103

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2104

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2121

command = radeon_get_ib_value(p, idx+4);

sys/dev/pci/drm/radeon/evergreen_cs.c

2123

info = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2156

tmp = radeon_get_ib_value(p, idx) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2157

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2194

tmp = radeon_get_ib_value(p, idx+2) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2195

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2226

if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||

sys/dev/pci/drm/radeon/evergreen_cs.c

2227

radeon_get_ib_value(p, idx + 2) != 0) {

sys/dev/pci/drm/radeon/evergreen_cs.c

2250

(radeon_get_ib_value(p, idx+1) & 0xfffffff8) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2251

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2272

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2273

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2294

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/pci/drm/radeon/evergreen_cs.c

2295

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/evergreen_cs.c

2353

switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {

sys/dev/pci/drm/radeon/evergreen_cs.c

2417

offset = radeon_get_ib_value(p, idx+1+(i*8)+0);

sys/dev/pci/drm/radeon/evergreen_cs.c

2418

size = radeon_get_ib_value(p, idx+1+(i*8)+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2500

offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2501

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2519

offset = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/evergreen_cs.c

2520

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2544

offset = radeon_get_ib_value(p, idx+0);

sys/dev/pci/drm/radeon/evergreen_cs.c

2545

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/evergreen_cs.c

2573

offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2574

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2585

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/pci/drm/radeon/evergreen_cs.c

2600

offset = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/evergreen_cs.c

2601

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2612

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/pci/drm/radeon/evergreen_cs.c

2650

offset = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2654

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2678

offset = radeon_get_ib_value(p, idx + 0);

sys/dev/pci/drm/radeon/evergreen_cs.c

2679

offset += ((u64)(radeon_get_ib_value(p, idx + 1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/evergreen_cs.c

2707

offset = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2708

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2719

reg = radeon_get_ib_value(p, idx + 1) << 2;

sys/dev/pci/drm/radeon/evergreen_cs.c

2734

offset = radeon_get_ib_value(p, idx + 5);

sys/dev/pci/drm/radeon/evergreen_cs.c

2735

offset += ((u64)(radeon_get_ib_value(p, idx + 6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2746

reg = radeon_get_ib_value(p, idx + 5) << 2;

sys/dev/pci/drm/radeon/evergreen_cs.c

2905

header = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/evergreen_cs.c

2920

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2928

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2929

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2960

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

2961

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2962

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2963

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2983

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

2985

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

2989

dst_offset = radeon_get_ib_value(p, idx + 7);

sys/dev/pci/drm/radeon/evergreen_cs.c

2990

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

2995

src_offset = radeon_get_ib_value(p, idx+7);

sys/dev/pci/drm/radeon/evergreen_cs.c

2996

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3000

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3019

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

3020

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3021

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3022

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3061

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3062

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3063

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

3064

dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3065

src_offset = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/evergreen_cs.c

3066

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3092

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

3101

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3103

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

3105

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3106

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3136

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

3154

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

3163

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3165

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

3167

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3168

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3194

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

3196

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3200

dst_offset = radeon_get_ib_value(p, idx+7);

sys/dev/pci/drm/radeon/evergreen_cs.c

3201

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3206

src_offset = radeon_get_ib_value(p, idx+7);

sys/dev/pci/drm/radeon/evergreen_cs.c

3207

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3211

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3241

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/pci/drm/radeon/evergreen_cs.c

3250

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3252

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/evergreen_cs.c

3254

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/pci/drm/radeon/evergreen_cs.c

3255

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/pci/drm/radeon/evergreen_cs.c

3288

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/evergreen_cs.c

3289

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/pci/drm/radeon/evergreen_cs.c

765

texdw[0] = radeon_get_ib_value(p, idx + 0);

sys/dev/pci/drm/radeon/evergreen_cs.c

766

texdw[1] = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/evergreen_cs.c

767

texdw[2] = radeon_get_ib_value(p, idx + 2);

sys/dev/pci/drm/radeon/evergreen_cs.c

768

texdw[3] = radeon_get_ib_value(p, idx + 3);

sys/dev/pci/drm/radeon/evergreen_cs.c

769

texdw[4] = radeon_get_ib_value(p, idx + 4);

sys/dev/pci/drm/radeon/evergreen_cs.c

770

texdw[5] = radeon_get_ib_value(p, idx + 5);

sys/dev/pci/drm/radeon/evergreen_cs.c

771

texdw[6] = radeon_get_ib_value(p, idx + 6);

sys/dev/pci/drm/radeon/evergreen_cs.c

772

texdw[7] = radeon_get_ib_value(p, idx + 7);

sys/dev/pci/drm/radeon/r100.c

1307

value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

1343

c = radeon_get_ib_value(p, idx++) & 0x1F;

sys/dev/pci/drm/radeon/r100.c

1359

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

1360

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1372

ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1385

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

1386

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1477

if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {

sys/dev/pci/drm/radeon/r100.c

1491

header = radeon_get_ib_value(p, h_idx);

sys/dev/pci/drm/radeon/r100.c

1492

crtc_id = radeon_get_ib_value(p, h_idx + 5);

sys/dev/pci/drm/radeon/r100.c

1596

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

1928

value = radeon_get_ib_value(p, idx + 2);

sys/dev/pci/drm/radeon/r100.c

1964

ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1978

ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r100.c

1980

track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));

sys/dev/pci/drm/radeon/r100.c

1985

track->max_indx = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r100.c

1987

track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/r100.c

1994

if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {

sys/dev/pci/drm/radeon/r100.c

1998

track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));

sys/dev/pci/drm/radeon/r100.c

1999

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r100.c

2007

if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {

sys/dev/pci/drm/radeon/r100.c

2011

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

2019

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

2026

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r100.c

2033

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r100.c

2040

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r200.c

161

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r300.c

1198

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/pci/drm/radeon/r300.c

1209

if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {

sys/dev/pci/drm/radeon/r300.c

1213

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r300.c

1224

if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {

sys/dev/pci/drm/radeon/r300.c

1228

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r300.c

1236

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r300.c

1243

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r300.c

1250

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r300.c

1257

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r300.c

641

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1028

track->sq_config = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1031

track->db_depth_control = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1043

track->db_depth_info = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1054

track->db_depth_info = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1059

track->db_depth_view = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1063

track->db_depth_size = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1068

track->vgt_strmout_en = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1072

track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1086

track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1098

track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;

sys/dev/pci/drm/radeon/r600_cs.c

1111

track->cb_target_mask = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1115

track->cb_shader_mask = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1118

tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));

sys/dev/pci/drm/radeon/r600_cs.c

1124

tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));

sys/dev/pci/drm/radeon/r600_cs.c

1144

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1154

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1167

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1179

track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1263

track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1283

track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1297

track->db_offset = radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1310

track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1316

track->htile_surface = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1392

track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;

sys/dev/pci/drm/radeon/r600_cs.c

1499

word0 = radeon_get_ib_value(p, idx + 0);

sys/dev/pci/drm/radeon/r600_cs.c

1506

word1 = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r600_cs.c

1507

word2 = radeon_get_ib_value(p, idx + 2) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1508

word3 = radeon_get_ib_value(p, idx + 3) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

1509

word4 = radeon_get_ib_value(p, idx + 4);

sys/dev/pci/drm/radeon/r600_cs.c

1510

word5 = radeon_get_ib_value(p, idx + 5);

sys/dev/pci/drm/radeon/r600_cs.c

1646

idx_value = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

1660

tmp = radeon_get_ib_value(p, idx + 1);

sys/dev/pci/drm/radeon/r600_cs.c

1721

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1772

(radeon_get_ib_value(p, idx+1) & 0xfffffff0) +

sys/dev/pci/drm/radeon/r600_cs.c

1773

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1790

command = radeon_get_ib_value(p, idx+4);

sys/dev/pci/drm/radeon/r600_cs.c

1808

tmp = radeon_get_ib_value(p, idx) +

sys/dev/pci/drm/radeon/r600_cs.c

1809

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1838

tmp = radeon_get_ib_value(p, idx+2) +

sys/dev/pci/drm/radeon/r600_cs.c

1839

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1860

if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||

sys/dev/pci/drm/radeon/r600_cs.c

1861

radeon_get_ib_value(p, idx + 2) != 0) {

sys/dev/pci/drm/radeon/r600_cs.c

1884

(radeon_get_ib_value(p, idx+1) & 0xfffffff8) +

sys/dev/pci/drm/radeon/r600_cs.c

1885

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1906

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/pci/drm/radeon/r600_cs.c

1907

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/pci/drm/radeon/r600_cs.c

1962

switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {

sys/dev/pci/drm/radeon/r600_cs.c

1988

base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),

sys/dev/pci/drm/radeon/r600_cs.c

1989

mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),

sys/dev/pci/drm/radeon/r600_cs.c

2005

offset = radeon_get_ib_value(p, idx+1+(i*7)+0);

sys/dev/pci/drm/radeon/r600_cs.c

2006

size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;

sys/dev/pci/drm/radeon/r600_cs.c

2112

offset = (u64)radeon_get_ib_value(p, idx+1) << 8;

sys/dev/pci/drm/radeon/r600_cs.c

2152

offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2153

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2172

offset = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/r600_cs.c

2173

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2198

offset = radeon_get_ib_value(p, idx+0);

sys/dev/pci/drm/radeon/r600_cs.c

2199

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/pci/drm/radeon/r600_cs.c

2227

offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2228

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2239

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/pci/drm/radeon/r600_cs.c

2251

offset = radeon_get_ib_value(p, idx+3);

sys/dev/pci/drm/radeon/r600_cs.c

2252

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2263

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/pci/drm/radeon/r600_cs.c

2402

header = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/r600_cs.c

2415

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2421

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2422

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2446

idx_value = radeon_get_ib_value(p, idx + 2);

sys/dev/pci/drm/radeon/r600_cs.c

2450

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2454

dst_offset = radeon_get_ib_value(p, idx+5);

sys/dev/pci/drm/radeon/r600_cs.c

2455

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2460

src_offset = radeon_get_ib_value(p, idx+5);

sys/dev/pci/drm/radeon/r600_cs.c

2461

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2465

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2472

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/r600_cs.c

2473

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2474

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2475

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2483

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/pci/drm/radeon/r600_cs.c

2484

src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/pci/drm/radeon/r600_cs.c

2485

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2486

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;

sys/dev/pci/drm/radeon/r600_cs.c

2516

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/pci/drm/radeon/r600_cs.c

2517

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/pci/drm/radeon/r600_cs.c

853

wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);

sys/dev/pci/drm/radeon/r600_cs.c

869

if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {

sys/dev/pci/drm/radeon/r600_cs.c

874

if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {

sys/dev/pci/drm/radeon/r600_cs.c

888

header = radeon_get_ib_value(p, h_idx);

sys/dev/pci/drm/radeon/r600_cs.c

889

crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);

sys/dev/pci/drm/radeon/radeon_cs.c

760

header = radeon_get_ib_value(p, idx);

sys/dev/pci/drm/radeon/radeon_cs.c

796

printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));

sys/dev/pci/drm/radeon/radeon_cs.c

798

printk("\t0x%08x\n", radeon_get_ib_value(p, i));

sys/dev/pci/drm/radeon/radeon_cs.c

879

idx = radeon_get_ib_value(p, p3reloc.idx + 1);

sys/dev/pci/drm/radeon/radeon_uvd.c

572

offset = radeon_get_ib_value(p, data0);

sys/dev/pci/drm/radeon/radeon_uvd.c

573

idx = radeon_get_ib_value(p, data1);

sys/dev/pci/drm/radeon/radeon_uvd.c

588

cmd = radeon_get_ib_value(p, p->idx) >> 1;

sys/dev/pci/drm/radeon/radeon_vce.c

508

offset = radeon_get_ib_value(p, lo);

sys/dev/pci/drm/radeon/radeon_vce.c

509

idx = radeon_get_ib_value(p, hi);

sys/dev/pci/drm/radeon/radeon_vce.c

595

uint32_t len = radeon_get_ib_value(p, p->idx);

sys/dev/pci/drm/radeon/radeon_vce.c

596

uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);

sys/dev/pci/drm/radeon/radeon_vce.c

612

handle = radeon_get_ib_value(p, p->idx + 2);

sys/dev/pci/drm/radeon/radeon_vce.c

631

*size = radeon_get_ib_value(p, p->idx + 8) *

sys/dev/pci/drm/radeon/radeon_vce.c

632

radeon_get_ib_value(p, p->idx + 10) *

sys/dev/pci/drm/radeon/radeon_vce.c

668

tmp = radeon_get_ib_value(p, p->idx + 4);