Symbol: pixel_format
regress/sys/dev/video/videotest.c
254
fsizes.pixel_format = pixelformat;
sys/dev/fdt/rkdrm.c
493
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1208
if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c
1212
&mode_cmd->pixel_format, mode_cmd->modifier[0]);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
95
const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
97
return amdgpu_lookup_format_info(pixel_format, modifier);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h
61
const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
703
static enum pixel_format convert_pixel_format_to_dalsurface(
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
706
enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
66
static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, const enum pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
68
if (pixel_format < PIXEL_FORMAT_INVALID)
sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c
69
*spl_pixel_format = (enum spl_pixel_format)pixel_format;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
166
const enum surface_pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
146
s->pixel_format,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
165
s->pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
425
plane->pixel_format = dml2_444_32;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
510
plane->pixel_format = dml2_420_8;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
514
plane->pixel_format = dml2_420_10;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
520
plane->pixel_format = dml2_444_64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
524
plane->pixel_format = dml2_444_16;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
527
plane->pixel_format = dml2_444_8;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
530
plane->pixel_format = dml2_rgbe_alpha;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
533
plane->pixel_format = dml2_444_32;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
894
dml21_is_plane1_enabled(pln_prog->plane_descriptor->pixel_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
291
enum dml2_source_format_class pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
312
enum dml2_source_format_class pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10500
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10514
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1053
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10686
s->SurfaceParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10798
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10957
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11052
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11139
CheckGlobalPrefetchAdmissibility_params->pixel_format = s->pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11206
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11507
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11627
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11911
* (display_cfg->stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12219
enum dml2_source_format_class source_format = display_cfg->plane_descriptors[plane_idx].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12384
l->source_format = display_cfg->plane_descriptors[l->plane_idx].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12860
plane_descriptor->pixel_format == dml2_420_8 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12861
plane_descriptor->pixel_format == dml2_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12862
plane_descriptor->pixel_format == dml2_420_12;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3755
if (p->display_cfg->plane_descriptors[k].pixel_format == dml2_420_10) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3765
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format) || p->display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6006
if (p->pixel_format[i] == dml2_420_10) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6017
DML_LOG_VERBOSE("DML::%s: i=%u pixel_format = %d\n", __func__, i, p->pixel_format[i]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6028
if (p->pixel_format[i] == dml2_422_planar_8 || p->pixel_format[i] == dml2_422_planar_10 || p->pixel_format[i] == dml2_422_planar_12) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6843
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6914
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7390
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7438
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7701
CheckGlobalPrefetchAdmissibility_params->pixel_format = s->pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7776
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8009
&& (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8022
|| (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8044
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8094
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8151
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8166
} else if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // horz video
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8168
} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // vert video
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8170
} else if (display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { // rgbe + alpha
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8178
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8237
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8267
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8294
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8566
CalculateWriteBackDISPCLK(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8898
s->SurfParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
892
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9159
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9326
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1140
enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1231
enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1995
enum dml2_source_format_class *pixel_format;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
285
uint32_t pixel_format;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
298
pixel_format = 0;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
328
pixel_format = 1;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
331
pixel_format = 3;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
336
pixel_format = 8;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
340
pixel_format = 10;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
344
pixel_format = 65;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
350
pixel_format = 64;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
356
pixel_format = 67;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
362
pixel_format = 66;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
368
pixel_format = 26; /* ARGB16161616_UNORM */
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
371
pixel_format = 24;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
374
pixel_format = 25;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
384
CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
105
static bool dpp1_dscl_is_video_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
114
static bool dpp1_dscl_is_420_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
106
uint32_t pixel_format = 0;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
131
pixel_format = 1;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
134
pixel_format = 3;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
139
pixel_format = 8;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
143
pixel_format = 10;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
148
pixel_format = 65;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
154
pixel_format = 64;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
160
pixel_format = 67;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
166
pixel_format = 66;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
172
pixel_format = 26; /* ARGB16161616_UNORM */
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
175
pixel_format = 24;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
178
pixel_format = 25;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
181
pixel_format = 12;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
186
pixel_format = 112;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
190
pixel_format = 113;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
194
pixel_format = 114;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
200
pixel_format = 115;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
206
pixel_format = 118;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
210
pixel_format = 119;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
228
CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
101
pixel_format = 64;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
107
pixel_format = 67;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
113
pixel_format = 66;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
118
pixel_format = 22;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
121
pixel_format = 24;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
124
pixel_format = 25;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
127
pixel_format = 12;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
132
pixel_format = 112;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
136
pixel_format = 113;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
140
pixel_format = 114;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
146
pixel_format = 115;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
152
pixel_format = 118;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
156
pixel_format = 119;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
174
CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
53
uint32_t pixel_format = 0;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
78
pixel_format = 1;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
81
pixel_format = 3;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
86
pixel_format = 8;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
90
pixel_format = 10;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
95
pixel_format = 65;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
213
uint32_t pixel_format = 0;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
240
pixel_format = 1;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
243
pixel_format = 3;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
248
pixel_format = 8;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
252
pixel_format = 10;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
257
pixel_format = 65;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
263
pixel_format = 64;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
269
pixel_format = 67;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
275
pixel_format = 66;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
281
pixel_format = 26; /* ARGB16161616_UNORM */
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
284
pixel_format = 24;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
287
pixel_format = 25;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
290
pixel_format = 12;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
295
pixel_format = 112;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
299
pixel_format = 113;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
303
pixel_format = 114;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
309
pixel_format = 115;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
315
pixel_format = 116;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
319
pixel_format = 116;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
323
pixel_format = 118;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
327
pixel_format = 119;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
345
CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
102
pixel_format = 10;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
106
pixel_format = 65;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
111
pixel_format = 64;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
116
pixel_format = 67;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
121
pixel_format = 66;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
127
pixel_format = 26; /* ARGB16161616_UNORM */
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
130
pixel_format = 24;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
133
pixel_format = 25;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
136
pixel_format = 12;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
141
pixel_format = 112;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
145
pixel_format = 113;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
149
pixel_format = 114;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
155
pixel_format = 115;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
161
pixel_format = 116;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
165
pixel_format = 116;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
169
pixel_format = 118;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
173
pixel_format = 119;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
191
CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
64
uint32_t pixel_format = 0;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
90
pixel_format = 1;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
93
pixel_format = 3;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
98
pixel_format = 8;
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
106
static bool dpp401_dscl_is_420_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
97
static bool dpp401_dscl_is_video_format(enum pixel_format format)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
397
dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
422
if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
427
dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
428
dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
429
dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
430
dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
446
dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
447
dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
448
dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
591
INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
629
if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
636
SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
637
CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
639
NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
640
NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
549
enum dsc_pixel_format pixel_format;
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
212
INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
250
if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
257
SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
258
CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
260
NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
261
NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
1042
SURFACE_PIXEL_FORMAT, &s->pixel_format);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
144
const enum surface_pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
697
uint32_t pixel_format;
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
767
const enum surface_pixel_format pixel_format);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
1273
SURFACE_PIXEL_FORMAT, &s->pixel_format);
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
314
const enum surface_pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
322
const enum surface_pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
285
const enum surface_pixel_format pixel_format);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
585
const enum surface_pixel_format pixel_format)
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
965
SURFACE_PIXEL_FORMAT, &s->pixel_format);
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
282
const enum surface_pixel_format pixel_format);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
311
s->pixel_format,
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
194
enum pixel_format surface_pixel_format;
sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h
163
enum pixel_format format;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
761
enum spl_pixel_format pixel_format = spl_in->basic_in.format;
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
772
if (!spl_is_subsampled_format(pixel_format)) {
sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c
773
if (spl_is_video_format(pixel_format))
sys/dev/pci/drm/drm_client.c
360
fb_req.pixel_format = format;
sys/dev/pci/drm/drm_fourcc.c
429
u32 pixel_format, u64 modifier)
sys/dev/pci/drm/drm_fourcc.c
434
info = dev->mode_config.funcs->get_format_info(pixel_format,
sys/dev/pci/drm/drm_fourcc.c
438
info = drm_format_info(pixel_format);
sys/dev/pci/drm/drm_framebuffer.c
127
r.pixel_format = drm_driver_legacy_fb_format(dev, or->bpp, or->depth);
sys/dev/pci/drm/drm_framebuffer.c
128
if (r.pixel_format == DRM_FORMAT_INVALID) {
sys/dev/pci/drm/drm_framebuffer.c
217
if (r->pixel_format != DRM_FORMAT_NV12 ||
sys/dev/pci/drm/drm_framebuffer.c
292
if (!__drm_format_info(r->pixel_format)) {
sys/dev/pci/drm/drm_framebuffer.c
294
&r->pixel_format);
sys/dev/pci/drm/drm_framebuffer.c
299
info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]);
sys/dev/pci/drm/drm_framebuffer.c
610
r->pixel_format = fb->format->format;
sys/dev/pci/drm/drm_ioc32.c
294
u32 pixel_format;
sys/dev/pci/drm/drm_plane.c
1198
.pixel_format = DRM_FORMAT_ARGB8888,
sys/dev/pci/drm/i915/display/i9xx_plane.c
1171
int fourcc, pixel_format;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1207
pixel_format = val & DISP_FORMAT_MASK;
sys/dev/pci/drm/i915/display/i9xx_plane.c
1208
fourcc = i9xx_format_to_fourcc(pixel_format);
sys/dev/pci/drm/i915/display/i9xx_plane.c
757
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.c
760
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/i9xx_plane.c
769
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.c
772
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/i9xx_plane.c
784
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.c
787
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/i9xx_plane.c
799
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.c
810
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.h
21
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/i9xx_plane.h
38
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/icl_dsi.c
1511
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/icl_dsi.c
1693
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
sys/dev/pci/drm/i915/display/icl_dsi.c
354
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/icl_dsi.c
751
switch (intel_dsi->pixel_format) {
sys/dev/pci/drm/i915/display/icl_dsi.c
753
MISSING_CASE(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/icl_dsi.c
895
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/icl_dsi.c
920
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/icl_dsi.c
942
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
sys/dev/pci/drm/i915/display/intel_cursor.c
185
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/intel_cursor.c
346
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/intel_display.c
609
u32 pixel_format, u64 modifier)
sys/dev/pci/drm/i915/display/intel_display.c
629
return plane->max_stride(plane, pixel_format, modifier,
sys/dev/pci/drm/i915/display/intel_display.h
404
u32 pixel_format, u64 modifier);
sys/dev/pci/drm/i915/display/intel_display_types.h
1517
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/intel_dsi.c
35
int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/intel_dsi.h
77
enum mipi_dsi_pixel_format pixel_format;
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
739
drm_printf(&p, "Pixel Format %d\n", intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
785
intel_dsi->pixel_format =
sys/dev/pci/drm/i915/display/intel_fb.c
1978
u32 pixel_format, u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
1988
return intel_plane_fb_max_stride(display->drm, pixel_format, modifier);
sys/dev/pci/drm/i915/display/intel_fb.c
2242
mode_cmd->pixel_format,
sys/dev/pci/drm/i915/display/intel_fb.c
2246
&mode_cmd->pixel_format, mode_cmd->modifier[0]);
sys/dev/pci/drm/i915/display/intel_fb.c
2250
max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format,
sys/dev/pci/drm/i915/display/intel_fb.c
435
intel_fb_get_format_info(u32 pixel_format, u64 modifier)
sys/dev/pci/drm/i915/display/intel_fb.c
442
return lookup_format_info(md->formats, md->format_count, pixel_format);
sys/dev/pci/drm/i915/display/intel_fb.h
50
intel_fb_get_format_info(u32 pixel_format, u64 modifier);
sys/dev/pci/drm/i915/display/intel_fbdev.c
229
mode_cmd->pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sys/dev/pci/drm/i915/display/intel_fbdev_fb.c
54
mode_cmd->pixel_format,
sys/dev/pci/drm/i915/display/intel_plane_initial.c
284
mode_cmd.pixel_format = fb->format->format;
sys/dev/pci/drm/i915/display/intel_sprite.c
961
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/intel_sprite.c
964
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/intel_sprite.c
976
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/intel_sprite.c
979
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1000
MISSING_CASE(pixel_format);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3014
int fourcc, pixel_format;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3045
pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3047
pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3058
fourcc = skl_format_to_fourcc(pixel_format,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
475
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
480
const struct drm_format_info *info = drm_format_info(pixel_format);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
491
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
497
return plane_max_stride(plane, pixel_format,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
504
u32 pixel_format, u64 modifier,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
510
return plane_max_stride(plane, pixel_format,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
944
static u32 skl_plane_ctl_format(u32 pixel_format)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
946
switch (pixel_format) {
sys/dev/pci/drm/i915/display/vlv_dsi.c
1221
unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1311
unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1367
val |= pixel_format_to_reg(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi.c
298
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
sys/dev/pci/drm/i915/display/vlv_dsi.c
654
if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
123
int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
182
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
351
int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
sys/dev/pci/drm/i915/display/vlv_dsi_pll.c
495
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
sys/dev/pci/drm/i915/gvt/fb_decoder.c
57
static const struct pixel_format bdw_pixel_formats[] = {
sys/dev/pci/drm/i915/gvt/fb_decoder.c
70
static const struct pixel_format skl_pixel_formats[] = {
sys/dev/pci/drm/include/drm/drm_fourcc.h
311
u32 pixel_format, u64 modifier);
sys/dev/pci/drm/include/drm/drm_mode_config.h
99
const struct drm_format_info *(*get_format_info)(u32 pixel_format, u64 modifier);
sys/dev/pci/drm/include/uapi/drm/drm_mode.h
714
__u32 pixel_format;
sys/dev/pci/drm/radeon/radeon_fbdev.c
230
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sys/dev/pci/drm/radeon/radeon_fbdev.c
233
format_info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd.pixel_format,
sys/dev/pv/viogpu.c
686
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sys/dev/usb/utvfu.c
536
if (fsizes->pixel_format != V4L2_PIX_FMT_YUYV)
sys/dev/usb/uvideo.c
3718
if (sc->sc_fmtgrp[idx].pixelformat == fsizes->pixel_format) {
sys/dev/usb/uvideo.c
3748
if (sc->sc_fmtgrp[idx].pixelformat == fivals->pixel_format) {
sys/sys/videoio.h
4564
u_int32_t pixel_format; /* Pixel format */
sys/sys/videoio.h
4592
u_int32_t pixel_format; /* Pixel format */