sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10400

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10425

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10426

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1292

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1296

pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1297

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1298

pipe_ctx->stream->link == link)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1305

if (pipe_ctx && pipe_ctx->stream_res.tg &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1306

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1307

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1562

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1572

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1573

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1574

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1575

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1576

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1580

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1641

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1674

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1675

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1676

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1677

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1678

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1682

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1748

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1758

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1759

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1760

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1761

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1762

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1766

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1821

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1858

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1859

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1860

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1861

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1862

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1866

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1890

pipe_ctx->stream->timing.h_addressable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1932

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1942

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1943

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1944

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1945

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1946

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1950

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2009

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2042

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2043

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2044

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2045

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2046

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2050

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2074

pipe_ctx->stream->timing.v_addressable,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2112

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2122

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2123

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2124

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2125

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2126

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2130

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2186

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2219

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2220

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2221

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2222

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2223

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2227

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2287

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2297

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2298

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2299

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2300

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2301

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2305

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2341

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2351

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2352

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2353

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2354

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2355

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2359

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2410

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2420

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2421

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2422

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2423

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2424

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2428

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2479

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2489

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2490

if (pipe_ctx->stream &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2491

pipe_ctx->stream->link == aconnector->dc_link &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2492

pipe_ctx->stream->sink &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2493

pipe_ctx->stream->sink == aconnector->dc_sink)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2497

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1222

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1223

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1236

pipe_ctx = &pipes[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1241

if (pipe_ctx == NULL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1302

&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1304

&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1307

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1308

pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1311

pipe_ctx->stream->timing.display_color_depth = requestColorDepth;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1312

pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1314

dc_link_update_dsc_config(pipe_ctx);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1319

*aconnector->timing_requested = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1325

pipe_ctx->stream->test_pattern.type = test_pattern;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1326

pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

53

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

55

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

57

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

62

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

64

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

66

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

71

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

73

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

75

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

sys/dev/pci/drm/amd/display/dc/basics/dc_common.c

77

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

sys/dev/pci/drm/amd/display/dc/basics/dc_common.h

33

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/basics/dc_common.h

35

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/basics/dc_common.h

37

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2786

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3009

static bool all_displays_in_sync(const struct pipe_ctx pipe[],

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3012

const struct pipe_ctx *active_pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

3044

const struct pipe_ctx pipe[],

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

171

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

173

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

177

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

180

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

181

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

186

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

187

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

188

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

138

const struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

141

if (stream == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

142

pipe_ctx = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

146

ASSERT(pipe_ctx != NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

153

cfg->signal = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

154

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

164

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

166

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

117

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

153

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

156

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

160

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

174

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

184

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

186

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

191

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

202

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

120

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

120

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

218

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

219

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

220

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

106

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

90

static bool should_disable_otg(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

109

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

110

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

111

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

279

if (pipe_ctx->stream_res.tg &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

280

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

281

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

283

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

323

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

325

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

372

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

375

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

379

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

393

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

426

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

428

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

433

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

444

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

490

static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

514

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

518

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

520

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

521

pipe_ctx_list[active_pipe_count] = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

572

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

199

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

200

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

203

struct pipe_ctx *pipe = safe_to_lower

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

204

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

205

: &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

263

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

267

if (pipe_ctx->stream_res.tg &&

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

268

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

269

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

271

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

291

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

293

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

300

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

317

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

395

static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

418

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

422

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

424

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

425

pipe_ctx_list[active_pipe_count] = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

474

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

530

struct pipe_ctx *otg_master;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

565

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

567

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

569

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

574

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1213

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1214

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1217

if (stream == pipe_ctx->stream) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1218

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1219

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1220

dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1226

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1229

memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1230

sizeof(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1235

memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1238

get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1240

get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1242

get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1244

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1246

get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1250

dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1254

get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1256

get_subvp_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1258

get_mclk_switch_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1260

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1262

get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1273

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1285

pipe_ctx = dc_stream_get_pipe_ctx(stream_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1286

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1288

dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1302

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1317

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1325

dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1329

if ((context->res_ctx.pipe_ctx[i].top_pipe) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1330

(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))

sys/dev/pci/drm/amd/display/dc/core/dc.c

1331

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=

sys/dev/pci/drm/amd/display/dc/core/dc.c

1332

dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1334

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=

sys/dev/pci/drm/amd/display/dc/core/dc.c

1335

dc->current_state->res_ctx.pipe_ctx[i].top_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1347

if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1348

!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1349

struct pipe_ctx *old_pipe, *new_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1351

old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1352

new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1360

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1430

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1432

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1593

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

sys/dev/pci/drm/amd/display/dc/core/dc.c

1596

if (!ctx->res_ctx.pipe_ctx[i].stream ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

1597

!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1599

if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1601

multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1619

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

sys/dev/pci/drm/amd/display/dc/core/dc.c

1622

if (!ctx->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

1623

|| ctx->res_ctx.pipe_ctx[i].top_pipe

sys/dev/pci/drm/amd/display/dc/core/dc.c

1624

|| ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1627

unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1633

struct pipe_ctx *pipe_set[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1988

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1991

return (pipe_ctx->stream && pipe_ctx->stream == stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1996

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1999

return (pipe_ctx->plane_state == plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2009

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2015

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2018

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2045

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2075

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2083

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2093

resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2114

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2124

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2142

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2256

pipe = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2345

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2393

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2482

if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2484

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2504

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2507

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2565

if (context->res_ctx.pipe_ctx[i].stream == NULL ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2566

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2567

context->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2568

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2638

const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2640

if (plane_state == pipe_ctx->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3555

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3557

if (pipe_ctx->plane_state != surface)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3560

resource_build_scaling_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3597

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3599

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3602

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3612

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3613

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3615

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3617

pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3624

pipe_ctx->stream->dmdata_address.quad_part != 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3625

dc->hwss.set_dmdata_attributes(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3634

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3635

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3636

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3637

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3659

dc->link_srv->update_dsc_config(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3663

dc->link_srv->increase_mst_payload(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3666

dc->link_srv->reduce_mst_payload(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3690

resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3695

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3697

if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3698

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3705

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3707

} else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space

sys/dev/pci/drm/amd/display/dc/core/dc.c

3708

&& !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3713

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3716

if (stream_update->abm_level && pipe_ctx->stream_res.abm) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3720

if (pipe_ctx->stream_res.tg->funcs->is_blanked)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3721

if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3726

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3728

pipe_ctx->stream_res.abm->funcs->set_abm_level(

sys/dev/pci/drm/amd/display/dc/core/dc.c

3729

pipe_ctx->stream_res.abm, stream->abm_level);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3792

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3794

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3796

if (pipe_ctx->plane_state != plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3847

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3849

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3851

if (pipe_ctx->plane_state != plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3919

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3921

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3924

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3928

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3929

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3950

struct pipe_ctx *top_pipe_to_program = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3990

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4005

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4007

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4009

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4012

pipe_ctx->plane_state->triplebuffer_flips = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4015

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4017

pipe_ctx->plane_state->triplebuffer_flips = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4069

struct pipe_ctx *top_pipe_to_program = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4091

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4123

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4132

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4141

struct pipe_ctx *mpcc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4142

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4239

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4243

pipe_ctx->stream && pipe_ctx->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4248

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4249

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

425

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4259

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4260

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4262

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4264

pipe_ctx->plane_state->triplebuffer_flips = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4267

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4269

pipe_ctx->plane_state->triplebuffer_flips = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4281

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4283

if (!pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4284

!pipe_ctx->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4285

should_update_pipe_for_stream(context, pipe_ctx, stream)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4288

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4296

stream_get_status(context, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4300

dc, pipe_ctx->stream, stream_status->plane_count, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4305

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4307

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4314

ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4318

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4328

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4330

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4336

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4342

&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4343

&context->res_ctx.pipe_ctx[i].dlg_regs,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4344

&context->res_ctx.pipe_ctx[i].ttu_regs);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4356

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4358

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4361

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4365

dc->hwss.set_flip_control_gsl(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4366

pipe_ctx->plane_state->flip_immediate);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4375

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4377

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4380

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4389

dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4395

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4397

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4398

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4481

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4483

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4486

if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

4487

!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

4488

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

4489

pipe_ctx->plane_state->skip_manual_trigger)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4492

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4493

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4566

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4707

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4721

pipe_ctx = &new_context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4723

if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4724

pipe_ctx->plane_state->force_full_update = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

489

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4899

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4909

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4921

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

526

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5586

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5623

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5681

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5685

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5705

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

587

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

592

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6129

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6142

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6184

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6193

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

653

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

658

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

702

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

775

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc.c

781

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

802

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc.c

807

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

809

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

810

pipe_ctx->stream_res.opp->dyn_expansion = option;

sys/dev/pci/drm/amd/display/dc/core/dc.c

811

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/core/dc.c

812

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/core/dc.c

825

struct pipe_ctx *pipes = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc.c

829

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

sys/dev/pci/drm/amd/display/dc/core/dc.c

831

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

865

struct pipe_ctx *pipes;

sys/dev/pci/drm/amd/display/dc/core/dc.c

870

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

871

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

884

struct pipe_ctx *pipes;

sys/dev/pci/drm/amd/display/dc/core/dc.c

889

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

892

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

911

struct pipe_ctx *pipes_affected[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc.c

920

if (dc->current_state->res_ctx.pipe_ctx[j].stream

sys/dev/pci/drm/amd/display/dc/core/dc.c

923

&dc->current_state->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1025

struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1027

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1028

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1033

struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1034

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1035

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1059

struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1060

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1061

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1118

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1123

struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1148

struct pipe_ctx *opp_head;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1156

opp_head = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1168

struct pipe_ctx *otg_master;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1173

otg_master = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1193

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1224

const struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1227

pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1229

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1236

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1237

dc->hwss.wait_for_all_pending_updates(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1240

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

312

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

324

struct pipe_ctx *top_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

333

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

338

switch (pipe_ctx->plane_res.scl_data.format) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

342

if (pipe_ctx->plane_state->layer_index > 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

352

if (pipe_ctx->plane_state->layer_index > 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

371

if (pipe_ctx->plane_state->layer_index > 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

383

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

390

struct pipe_ctx *top_pipe_ctx = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

458

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

464

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

465

if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

466

edp_link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

495

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

499

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

500

switch (pipe_ctx->p_state_type) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

523

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

528

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

529

switch (pipe_ctx->p_state_type) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

567

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

572

if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

585

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

590

if (!pipe_ctx->plane_state->dcc.enable) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

604

uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

605

uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

633

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

638

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

641

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

645

if (!pipe_ctx->has_vactive_margin) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

647

pipe_ctx->p_state_type = P_STATE_V_BLANK;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

651

pipe_ctx->p_state_type = P_STATE_FPO;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

655

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

662

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

667

pipe_ctx->p_state_type = P_STATE_SUB_VP;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

670

if (pipe_ctx->stream == pipe->stream)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

676

if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

677

if (pipe_ctx->stream->allow_freesync == 1) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

679

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

682

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

689

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

694

if (pipe_ctx && pipe_ctx->stream_res.tg &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

695

pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

696

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

697

pipe_ctx->stream_res.tg, params);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

706

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

728

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

732

struct dc_plane_state *plane = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

733

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

735

struct pipe_ctx *current_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

736

struct pipe_ctx *current_mpc_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

746

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

768

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

781

current_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

787

block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

794

block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

810

block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

817

block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

824

block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

829

block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

834

block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

841

block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

849

block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

885

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

905

current_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

914

block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

941

params->pipe_control_lock_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

945

dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

950

params->program_triplebuffer_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

955

params->update_plane_addr_params.pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

959

params->set_input_transfer_func_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

963

dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

976

params->set_output_transfer_func_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

981

params->update_visual_confirm_params.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

147

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

149

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

151

return link->dc->link_srv->update_dsc_config(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1110

plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1111

&pipe_ctx->plane_state->clip_rect);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1114

&pipe_ctx->stream->dst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1116

pipe_ctx, &plane_clip);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1117

odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1124

pipe_ctx->plane_res.scl_data.recout = shift_rec(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1128

&pipe_ctx->plane_res.scl_data.recout,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1129

pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1132

memset(&pipe_ctx->plane_res.scl_data.recout, 0,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1138

static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1140

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1141

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1149

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1150

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1153

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1156

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1161

pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1163

pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1165

pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1166

pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1167

pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1168

pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1170

pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1171

pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1173

if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1174

|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1175

pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1176

pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1178

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1179

pipe_ctx->plane_res.scl_data.ratios.horz, 19);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1180

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1181

pipe_ctx->plane_res.scl_data.ratios.vert, 19);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1182

pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1183

pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1184

pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1185

pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1254

static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1256

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1257

struct scaler_data *data = &pipe_ctx->plane_res.scl_data;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1263

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1271

pipe_ctx, &plane_state->dst_rect);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1410

struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1412

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1443

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1445

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1446

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1447

const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1451

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1468

pipe_ctx->stream->dst.x += timing->h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1469

pipe_ctx->stream->dst.y += timing->v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1472

pipe_ctx->plane_res.scl_data.h_active = odm_slice_src.width;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1473

pipe_ctx->plane_res.scl_data.v_active = odm_slice_src.height;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1474

pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1475

pipe_ctx->plane_state->format);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1478

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1479

struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1480

struct spl_out *spl_out = &pipe_ctx->plane_res.spl_out;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1483

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1485

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1487

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1490

translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1492

calculate_adjust_recout_for_visual_confirm(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1496

spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1500

translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1508

calculate_recout(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1510

calculate_scaling_ratios(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1525

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1527

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1529

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1533

pipe_ctx->plane_res.scl_data.viewport.width = 100;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1534

pipe_ctx->plane_res.scl_data.viewport.height = 100;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1535

pipe_ctx->plane_res.scl_data.viewport_c.width = 100;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1536

pipe_ctx->plane_res.scl_data.viewport_c.height = 100;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1537

if (pipe_ctx->plane_res.xfm != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1538

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1539

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1541

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1542

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1543

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1545

temp = pipe_ctx->plane_res.scl_data.taps;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1547

calculate_inits_and_viewports(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1549

if (pipe_ctx->plane_res.xfm != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1550

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1551

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1553

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1554

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1555

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1560

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1562

if (pipe_ctx->plane_res.xfm != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1563

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1564

pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1565

&pipe_ctx->plane_res.scl_data,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1568

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1569

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1570

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1571

&pipe_ctx->plane_res.scl_data,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1579

if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1580

pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1581

pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1582

pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1583

calculate_inits_and_viewports(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1590

if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1592

(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1593

pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1594

if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1595

pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1596

else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1597

pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1601

if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1602

pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1603

if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1604

pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1611

pipe_ctx->pipe_idx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1612

pipe_ctx->plane_res.scl_data.viewport.height,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1613

pipe_ctx->plane_res.scl_data.viewport.width,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1614

pipe_ctx->plane_res.scl_data.viewport.x,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1615

pipe_ctx->plane_res.scl_data.viewport.y,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1616

pipe_ctx->plane_res.scl_data.recout.height,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1617

pipe_ctx->plane_res.scl_data.recout.width,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1618

pipe_ctx->plane_res.scl_data.recout.x,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1619

pipe_ctx->plane_res.scl_data.recout.y,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1620

pipe_ctx->plane_res.scl_data.h_active,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1621

pipe_ctx->plane_res.scl_data.v_active,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1635

pipe_ctx->stream->dst.x -= timing->h_border_left;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1636

pipe_ctx->stream->dst.y -= timing->v_border_top;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1641

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1643

struct pipe_ctx *test_pipe, *split_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1644

struct rect r1 = pipe_ctx->plane_res.scl_data.recout;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1646

int cur_layer = pipe_ctx->plane_state->layer_index;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1648

reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1657

for (test_pipe = pipe_ctx->top_pipe; test_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1676

for (split_pipe = pipe_ctx->top_pipe; split_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1705

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1706

context->res_ctx.pipe_ctx[i].stream != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1707

if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1714

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1717

const struct pipe_ctx *primary_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1720

struct pipe_ctx *secondary_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1752

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1753

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1764

if (res_ctx->pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1765

secondary_pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1777

const struct pipe_ctx *cur_otg_master)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1779

const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1780

struct pipe_ctx *new_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1784

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1798

const struct pipe_ctx *cur_opp_head)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1800

const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1801

struct pipe_ctx *new_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1809

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1826

const struct pipe_ctx *new_pipe, *cur_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1830

cur_pipe = &cur_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1831

new_pipe = &new_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1849

const struct pipe_ctx *new_pipe, *cur_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1853

cur_pipe = &cur_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1854

new_pipe = &new_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1872

const struct pipe_ctx *new_pipe, *cur_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1876

cur_pipe = &cur_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1877

new_pipe = &new_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1896

const struct pipe_ctx *new_pipe, *cur_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1900

cur_pipe = &cur_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1901

new_pipe = &new_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1919

const struct pipe_ctx *new_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1923

new_pipe = &new_res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1934

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1938

return !pipe_ctx->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1939

!pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1940

pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1942

return !pipe_ctx->top_pipe && pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1944

return pipe_ctx->plane_state && pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1946

return !pipe_ctx->plane_state && !pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1952

struct pipe_ctx *resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1959

if (res_ctx->pipe_ctx[i].stream == stream &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1960

resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1961

return &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1966

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1968

struct pipe_ctx *opp_heads[MAX_PIPES])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1970

struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1991

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1993

struct pipe_ctx *dpp_pipes[MAX_PIPES])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1995

struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2012

struct pipe_ctx *dpp_pipes[MAX_PIPES])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2015

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2018

pipe = &res_ctx->pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2041

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2043

struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2050

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2052

struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2060

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2062

struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2074

int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2076

struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2079

while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2087

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2090

const struct pipe_ctx *other_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2105

int resource_get_odm_slice_count(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2118

int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2122

pipe_ctx = resource_get_opp_head(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2123

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2126

while (pipe_ctx->prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2128

pipe_ctx = pipe_ctx->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2134

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2172

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2174

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2175

bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2176

struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2177

int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2191

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2195

struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2205

opp, pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2220

const struct pipe_ctx *pipe_a, *pipe_b;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2226

pipe_a = &state_a->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2227

pipe_b = &state_b->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2262

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2263

const struct pipe_ctx *otg_master_b)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2265

const struct pipe_ctx *opp_head_a = otg_master_a;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2266

const struct pipe_ctx *opp_head_b = otg_master_b;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2304

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2353

struct pipe_ctx *otg_master, int stream_idx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2355

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2356

struct pipe_ctx *dpp_pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2412

struct pipe_ctx *otg_master;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2449

static struct pipe_ctx *get_tail_pipe(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2450

struct pipe_ctx *head_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2452

struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2462

static struct pipe_ctx *get_last_opp_head(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2463

struct pipe_ctx *opp_head)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2471

static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2472

struct pipe_ctx *dpp_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2482

struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2487

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2491

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2510

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2514

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2529

struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2637

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2653

pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2655

return pipe_ctx->link_res.hpo_dp_link_enc != NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2659

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2668

pipe_ctx->link_res.hpo_dp_link_enc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2762

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2764

if (pipe_ctx && pipe_ctx->link_res.dio_link_enc == pool->link_encoders[old_encoder])

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2765

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[new_encoder];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2772

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2808

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2810

return pipe_ctx->link_res.dio_link_enc != NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2814

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2824

pipe_ctx->link_res.dio_link_enc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2834

if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2852

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2921

static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2925

struct pipe_ctx *opp_head_pipe = otg_master_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2971

struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2977

struct pipe_ctx *sec_pipe, *tail_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2978

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3022

struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3054

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3056

if (pipe_ctx->plane_state == plane_state) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3057

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3058

pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3064

if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3065

pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3071

if (!pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3072

pipe_ctx->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3074

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3113

struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3118

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3119

struct pipe_ctx *new_opp_head;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3120

struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3193

struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3197

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3198

struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3252

struct pipe_ctx *dpp_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3257

struct pipe_ctx *last_dpp_pipe =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3259

struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3260

struct pipe_ctx *new_dpp_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3315

struct pipe_ctx *dpp_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3319

struct pipe_ctx *last_dpp_pipe =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3347

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3384

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3668

if (!res_ctx->pipe_ctx[tg_inst].stream) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3669

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3671

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3674

if (pipe_ctx->stream_res.tg->funcs->get_optc_source)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3675

pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3688

pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3690

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3691

pipe_ctx->plane_res.mi = pool->mis[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3692

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3693

pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3694

pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3695

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3696

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3699

pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3704

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3707

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3711

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3715

pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3718

pipe_ctx->pipe_idx = id_src[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3723

pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3724

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3727

pipe_ctx->stream = stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3732

res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3733

res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3734

res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3735

res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3793

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3832

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3833

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3834

pipe_ctx->pipe_idx = pipe_idx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3835

pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3836

pipe_ctx->plane_res.mi = pool->mis[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3837

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3838

pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3839

pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3840

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3841

pipe_ctx->stream_res.opp = pool->opps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3843

pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3848

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3849

pipe_ctx->stream_res.opp = pool->opps[tg_inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3852

pipe_ctx->stream = stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3868

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3894

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3896

if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3899

pipe_ctx->stream_res.stream_enc =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3903

if (!pipe_ctx->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3908

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3917

&pipe_ctx->link_config.dp_link_settings))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3921

&pipe_ctx->link_config.dp_tunnel_settings);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3924

&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3925

pipe_ctx->stream_res.hpo_dp_stream_enc =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3929

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3934

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3936

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3942

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3947

dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3951

pipe_ctx->stream_res.audio = find_first_free_audio(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3952

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3959

if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3961

pipe_ctx->stream_res.audio, true);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3965

if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3967

pipe_ctx->stream_res.abm = pool->abm;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3969

pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3974

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3975

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3977

pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4282

static void calculate_timing_params_for_dsc_with_padding(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4286

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4289

stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4290

pipe_ctx->dsc_padding_params.dsc_hactive_padding = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4291

pipe_ctx->dsc_padding_params.dsc_htotal_padding = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4294

pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4331

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4333

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4338

calculate_timing_params_for_dsc_with_padding(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4341

pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4342

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4343

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4352

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4358

pipe_ctx->clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4360

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4364

pipe_ctx->clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4398

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4400

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4408

unsigned int vic = pipe_ctx->stream->timing.vic;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4409

unsigned int rid = pipe_ctx->stream->timing.rid;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4410

unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4421

color_space = pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4563

if (pipe_ctx->stream->timing.hdmi_vic != 0)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4569

switch (pipe_ctx->stream->timing.hdmi_vic) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4785

void resource_build_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4788

struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4801

signal = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4803

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4804

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4808

set_avi_info_frame(&info->avi, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4810

set_vendor_info_packet(&info->vendor, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4811

set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4812

set_vtem_info_packet(&info->vtem, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4814

set_spd_info_packet(&info->spd, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4816

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4819

set_vsc_info_packet(&info->vsc, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4821

set_spd_info_packet(&info->spd, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4823

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4825

pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4840

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4843

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4846

if (dc_is_dp_signal(pipe_ctx->stream->signal)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4847

|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4848

pipe_ctx->clock_source = pool->dp_clock_source;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4850

pipe_ctx->clock_source = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4853

pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4855

pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4857

if (pipe_ctx->clock_source == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4858

pipe_ctx->clock_source =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4864

if (pipe_ctx->clock_source == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4869

pipe_ctx->clock_source);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4880

struct pipe_ctx *pipe_ctx_old,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4881

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4886

if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4889

if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4892

if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4895

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4896

&& pipe_ctx_old->stream != pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4899

if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4902

if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4905

if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4912

if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4915

if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4917

if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4922

if (pipe_ctx_old->link_res.dio_link_enc != pipe_ctx->link_res.dio_link_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4930

if (link_enc_prev != pipe_ctx->stream->link_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5259

struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5263

pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5264

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5269

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5270

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5274

pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5288

struct pipe_ctx *pipe_ctx, *pipe_ctx_check;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5290

pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5291

if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5292

!IS_PIPE_SYNCD_VALID(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5293

SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5297

pipe_ctx_check = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5301

struct pipe_ctx *first_pipe = pipe_ctx_check;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5322

struct pipe_ctx *pipe_ctx_reset;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5326

pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5436

struct pipe_ctx *pri_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5437

struct pipe_ctx *sec_pipe,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5441

struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5490

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5492

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5493

if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5494

pipe_ctx->stream_res.hpo_dp_stream_enc =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5496

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5498

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5503

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5507

if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5508

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5512

if (pipe_ctx->stream_res.hpo_dp_stream_enc) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5515

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5517

pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5519

if (pipe_ctx->link_res.hpo_dp_link_enc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5520

remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5523

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5524

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5530

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5532

return &pipe_ctx->plane_res.scl_data.dscl_prog_data;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5582

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5584

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5585

struct pipe_ctx *dpp_pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

659

const struct pipe_ctx *pipe_with_clk_src,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

660

const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

691

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

696

if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

697

return res_ctx->pipe_ctx[i].clock_source;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

810

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

874

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

900

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

903

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

904

int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

905

int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

935

static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

938

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

942

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

945

*dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

946

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

956

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

960

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

967

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

971

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

982

static void calculate_recout(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

152

struct pipe_ctx *cur_pipe = &dst_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

155

cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

158

cur_pipe->bottom_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

161

cur_pipe->prev_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

164

cur_pipe->next_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

408

struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

470

struct pipe_ctx *otg_master_pipe;

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

671

const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

673

return dc_state_get_stream_subvp_type(state, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

925

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

233

struct pipe_ctx *pipe_to_program = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

241

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

243

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

247

pipe_to_program = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

253

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

255

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

257

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

368

struct pipe_ctx *pipe_to_program = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

376

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

378

if (pipe_ctx->stream != stream ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

379

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

380

!pipe_ctx->plane_state ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

381

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

382

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

386

pipe_to_program = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

390

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

392

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

455

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

458

if (stream == pipe_ctx->stream) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

459

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

462

if (pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

463

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

464

pipe_ctx->plane_res.hubp->mpcc_id);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

652

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

654

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

682

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

684

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

688

dc->hwss.send_immediate_sdp_message(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

720

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

722

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

740

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

747

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

764

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

777

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

778

if (pipe_ctx->stream == stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

785

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

789

pipe_ctx->stream->dmdata_address = attr->address;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

793

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

796

pipe_ctx->stream->dmdata_address.quad_part != 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

814

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

819

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

134

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

135

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

137

if (pipe_ctx->plane_state != plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

140

if (pipe_ctx->plane_state && flags.bits.address)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

141

pipe_ctx->plane_state->status.is_flip_pending = false;

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

149

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

150

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

152

if (pipe_ctx->plane_state != plane_state)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

156

dc->hwss.update_pending_status(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

290

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

292

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

296

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

74

struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

76

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

77

pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc.h

2228

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1007

static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1009

if (pipe_ctx->plane_state != NULL) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1010

if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1011

resource_can_pipe_disable_cursor(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1015

if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1016

pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1017

pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1020

if (pipe_ctx->stream->link->replay_settings.config.replay_supported)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1027

struct pipe_ctx *pipe_ctx, uint8_t p_idx,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1030

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1034

pipe_ctx->stream->link, &panel_inst))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1092

struct pipe_ctx *pCtx, uint8_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

412

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

421

struct pipe_ctx *head_pipe,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

429

struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

461

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

480

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

487

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

531

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

536

if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) &&

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

577

struct pipe_ctx *subvp_pipe,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

578

struct pipe_ctx *vblank_pipe,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

657

struct pipe_ctx *vblank_pipe,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

661

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

667

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

713

struct pipe_ctx *subvp_pipes[])

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

778

struct pipe_ctx *subvp_pipe,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

843

struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

878

struct pipe_ctx *subvp_pipes[2];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

890

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

903

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

102

void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

34

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

92

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

119

resource_get_mpc_slice_count(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

124

spl_in->basic_in.mpc_h_slice_index = resource_get_mpc_slice_index(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

128

spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

131

stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

136

pipe_ctx->stream->ctx->dc->debug.max_downscale_src_width;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

137

spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

139

spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

144

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

146

if (pipe_ctx->stream->ctx->dc->debug.force_easf == 1)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

148

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

151

unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

152

unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

184

if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

185

spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

189

if (pipe_ctx->stream->ctx->dc->debug.force_cositing)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

190

spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

197

spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

198

spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

202

(enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

207

spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

208

spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

215

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

218

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

220

populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

222

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

224

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

226

populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

228

populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

76

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in)

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

78

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

79

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

80

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.c

98

populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.h

15

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);

sys/dev/pci/drm/amd/display/dc/dc_spl_translate.h

21

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);

sys/dev/pci/drm/amd/display/dc/dc_state_priv.h

38

const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

596

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_trace.h

26

#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

28

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

29

if (pipe_ctx->plane_state) \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

30

trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

31

pipe_ctx->stream, &pipe_ctx->plane_res, \

sys/dev/pci/drm/amd/display/dc/dc_trace.h

32

pipe_ctx->update_flags.raw); \

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

190

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

192

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

196

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

199

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

200

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

205

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

206

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

207

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

508

const struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

511

if (stream == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

512

pipe_ctx = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

516

ASSERT(pipe_ctx != NULL);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

523

cfg->signal = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

524

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

301

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

306

if (res_ctx->pipe_ctx[i].stream &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

307

res_ctx->pipe_ctx[i].stream->link == link &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

308

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

309

pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

315

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

319

if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

341

copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

347

if (pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

348

copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

351

if (pipe_ctx->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

352

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

382

copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

124

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

130

res_ctx->pipe_ctx[i].stream &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

131

res_ctx->pipe_ctx[i].stream->link &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

132

res_ctx->pipe_ctx[i].stream->link == link &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

133

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

134

pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

140

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

157

if (pipe_ctx->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

158

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

178

copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

435

pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1200

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1235

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

302

const struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

455

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

525

struct pipe_ctx *primary_pipe,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

526

struct pipe_ctx *secondary_pipe)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

710

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

894

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1000

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1042

wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1049

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1051

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1064

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1180

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1182

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1189

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1191

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1192

context->res_ctx.pipe_ctx[i].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1194

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1195

context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1200

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1202

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1204

context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1206

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1207

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1227

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1235

&context->res_ctx.pipe_ctx[i].dlg_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1236

&context->res_ctx.pipe_ctx[i].ttu_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1245

&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1326

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1334

if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1339

res_ctx->pipe_ctx[pipe_cnt].stream,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1340

res_ctx->pipe_ctx[i].stream) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1342

res_ctx->pipe_ctx[pipe_cnt].stream,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1343

res_ctx->pipe_ctx[i].stream))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1350

struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1356

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1371

pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1373

pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1374

if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1382

dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1408

pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1412

pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1413

pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1414

switch (resource_get_odm_slice_count(&res_ctx->pipe_ctx[i])) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1424

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1425

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1426

== res_ctx->pipe_ctx[i].plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1427

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1431

== res_ctx->pipe_ctx[i].plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1439

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1441

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1442

} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1443

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1450

switch (res_ctx->pipe_ctx[i].stream->signal) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1454

if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1472

switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1502

switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1513

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1514

!res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1525

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1526

pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1531

get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1537

if (res_ctx->pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1538

(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1539

dc_state_get_pipe_subvp_type(context, &res_ctx->pipe_ctx[i]) == SUBVP_PHANTOM))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1547

if (!res_ctx->pipe_ctx[i].plane_state) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1588

struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1589

struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1592

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1593

|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1600

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1656

struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1662

split_pipe = res_ctx->pipe_ctx[i].top_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1742

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2252

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2486

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2499

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

998

struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

192

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

205

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

479

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

468

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

538

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

541

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

573

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

574

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

577

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

580

context->res_ctx.pipe_ctx[i].det_buffer_size_kb =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

582

if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

583

context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

584

total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

313

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

326

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

328

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

416

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1049

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1099

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1101

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1102

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1103

pipe_ctx->subvp_index = index++;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1105

pipe_ctx->subvp_index = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1118

struct pipe_ctx *pri_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1146

struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1149

struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1172

struct pipe_ctx *otg_master;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1173

struct pipe_ctx *dpp_pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1225

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1232

pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1605

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1607

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1701

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1703

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1714

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1716

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1717

context->res_ctx.pipe_ctx[i].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1719

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1721

context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1726

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1727

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1729

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1730

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1732

context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1735

context->res_ctx.pipe_ctx[i].has_vactive_margin = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1737

context->res_ctx.pipe_ctx[i].has_vactive_margin = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1741

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1742

(context->res_ctx.pipe_ctx[i].top_pipe == NULL ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1743

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1744

context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1746

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1747

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1749

if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1751

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1755

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1759

if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1761

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1762

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1790

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1791

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1796

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1800

&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1803

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1809

static struct pipe_ctx *dcn32_find_split_pipe(

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1814

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1817

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1818

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1824

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1825

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1826

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1827

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1841

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1842

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1854

struct pipe_ctx *pri_pipe,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1855

struct pipe_ctx *sec_pipe,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1959

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2012

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2013

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2033

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2034

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2035

struct pipe_ctx *hsplit_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2076

struct pipe_ctx *pipe_4to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2119

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2128

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2220

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2221

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2596

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3391

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

343

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3433

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3447

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3449

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3451

refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3452

pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3453

/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3529

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3568

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

468

struct pipe_ctx *ref_pipe,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

475

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

488

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

565

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

644

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

687

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

728

struct pipe_ctx *subvp_pipes[2] = {0};

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

737

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

801

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

802

struct pipe_ctx *drr_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

819

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

836

drr_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

900

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

901

struct pipe_ctx *subvp_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

925

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

947

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

995

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

41

struct pipe_ctx *ref_pipe,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

444

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

458

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

461

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

557

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

587

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

477

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

491

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

494

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

590

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

617

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

102

timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

109

timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

128

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

129

pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

186

struct dc_stream_state *stream, const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

472

struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

474

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

477

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

754

populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

755

populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

87

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

883

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

887

mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

888

mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

890

mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

891

mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

898

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

905

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

910

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

912

pipe_ctx->p_state_type = P_STATE_V_BLANK;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

916

pipe_ctx->p_state_type = P_STATE_SUB_VP;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

920

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

922

pipe_ctx->p_state_type = P_STATE_FPO;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

925

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

93

timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

98

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

99

timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

13

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

25

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

26

void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

102

memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

103

memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

121

struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

147

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

152

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

157

memcpy(&pipe_ctx->global_sync,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

165

struct pipe_ctx *dc_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

186

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

189

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

190

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

191

pipe_ctx->link_res.hpo_dp_link_enc &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

192

dc_is_dp_signal(pipe_ctx->stream->signal));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

201

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

203

if (pipe_ctx->stream && dc_state_get_paired_subvp_stream(context, pipe_ctx->stream) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

204

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

212

void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

217

dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

218

find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

220

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

221

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

222

pipe_ctx->unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

223

pipe_ctx->det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

225

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

226

pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

227

pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

230

pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

231

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

232

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

234

dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

236

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

238

dml21_set_dc_p_state_type(pipe_ctx, stream_prog, sub_vp_enabled);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

441

if (context->res_ctx.pipe_ctx[k].stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

442

context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

443

context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

478

if (context->res_ctx.pipe_ctx[k].stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

479

context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

480

context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

73

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

75

struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

87

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

88

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

11

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

23

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

28

struct pipe_ctx *dc_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

29

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

32

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

36

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

37

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

41

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

315

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

316

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

93

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

94

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

109

static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

114

if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

115

if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

1158

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

116

return &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

123

static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

130

if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

131

state->res_ctx.pipe_ctx[i].stream->stream_id,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

132

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

134

return &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

149

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

160

struct pipe_ctx *mpc_pipe = pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

227

static bool is_plane_using_pipe(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

235

static bool is_pipe_free(const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

267

if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

268

struct pipe_ctx *head_pipe =

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

269

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

270

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

276

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

277

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

278

(existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

279

existing_state->res_ctx.pipe_ctx[i].next_odm_pipe))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

308

struct pipe_ctx *head_pipe =

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

309

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

310

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

316

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

317

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

318

existing_state->res_ctx.pipe_ctx[i].stream_res.tg)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

348

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

365

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

381

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

392

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

414

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

431

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

447

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

458

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

48

struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

52

struct pipe_ctx *prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

538

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

546

pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

557

static struct pipe_ctx *add_plane_to_blend_tree(struct dml2_context *ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

562

struct pipe_ctx *top_pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

568

top_pipe->bottom_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

572

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].top_pipe = top_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

573

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

575

top_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

589

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

603

static struct pipe_ctx *assign_pipes_to_stream(struct dml2_context *ctx, struct dc_state *state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

609

struct pipe_ctx *master_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

637

static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct dc_state *state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

646

struct pipe_ctx *master_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

695

static void free_pipe(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

697

memset(pipe, 0, sizeof(struct pipe_ctx));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

707

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

708

state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

710

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

711

!is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

712

free_pipe(&state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

719

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

723

pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][0]];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

738

struct pipe_ctx *master_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

750

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

759

struct pipe_ctx *master_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

784

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

899

struct pipe_ctx *otg_master = ctx->config.callbacks.get_otg_master_for_stream(&state->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

911

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h

122

struct pipe_ctx temp_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

107

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

129

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

130

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

151

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

192

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

238

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

263

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

316

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

359

struct pipe_ctx *subvp_pipes[2];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

368

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

435

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

449

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

50

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

509

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

510

struct pipe_ctx *subvp_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

534

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

552

if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

554

schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

559

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

651

struct pipe_ctx *ref_pipe,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

659

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

665

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

715

struct pipe_ctx *ref_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

741

struct pipe_ctx *curr_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

794

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

847

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

891

struct pipe_ctx *pipe_ctx = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

893

if (!pipe_ctx->plane_state || !pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

896

ctx->config.svp_pstate.callbacks.build_scaling_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

900

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx, state->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1205

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1270

struct pipe_ctx *current_pipe_context;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1279

current_pipe_context = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1295

struct pipe_ctx *current_pipe_context;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1320

if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1321

current_pipe_context = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1429

struct pipe_ctx *out)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

780

const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

982

struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

984

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

987

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

38

void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

39

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

156

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

158

if (pipe_ctx == NULL || pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

162

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

164

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

165

pipe_ctx->link_res.hpo_dp_link_enc &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

166

dc_is_dp_signal(pipe_ctx->stream->signal));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

174

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

176

if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

240

static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

243

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

247

hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

248

vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

253

pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

254

pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

255

pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

256

pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

258

pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

260

pipe_ctx->pipe_dlg_param.hactive = hactive;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

261

pipe_ctx->pipe_dlg_param.vactive = vactive;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

262

pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

263

pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

264

pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

265

pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

266

pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

267

pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

268

pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

269

pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

270

pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

271

pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

272

pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

273

pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

274

pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

275

pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

276

pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

299

if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

305

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

306

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

307

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

310

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

316

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

321

populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

323

pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

326

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

327

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

329

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

331

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

334

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

335

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

336

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

337

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

341

dml2_update_pipe_ctx_dchub_regs(&s->rq_regs, &s->disp_dlg_regs, &s->disp_ttu_regs, &out_new_hw_state->pipe_ctx[dc_pipe_ctx_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

343

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

347

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

348

(context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

349

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

350

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

353

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

356

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

440

if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

443

(1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

520

if (!display_state->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

522

if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

523

display_state->res_ctx.pipe_ctx[i].stream->stream_id,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

524

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

527

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

179

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

287

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

100

struct pipe_ctx *opp_heads[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

103

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

116

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

142

enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

37

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

74

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

75

void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

90

int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

91

int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

92

int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

93

int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

94

struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

95

struct pipe_ctx *(*get_otg_master_for_stream)(

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

98

int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

90

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1276

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1283

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1291

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

154

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

158

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

49

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1078

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1086

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1089

dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1091

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1093

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1096

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1099

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1107

pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1109

link_hwss->enable_audio_packet(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1111

if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1112

pipe_ctx->stream_res.audio->enabled = true;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1116

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1122

if (!pipe_ctx || !pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1125

dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1127

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1129

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1132

link_hwss->disable_audio_packet(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1134

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1135

pipe_ctx->stream_res.audio->enabled = false;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1149

void dce110_disable_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1151

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1153

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1154

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1156

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1159

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1160

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1165

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1166

pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1167

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1168

pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1169

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1172

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1173

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1174

pipe_ctx->stream_res.hpo_dp_stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1175

} else if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1176

pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1177

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1179

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1181

link_hwss->reset_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1183

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1185

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1186

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1201

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1205

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1210

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1213

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1214

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1221

void dce110_blank_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1223

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1233

link->dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1236

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1238

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1239

pipe_ctx->stream_res.hpo_dp_stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1240

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1241

pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1243

if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1252

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1267

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1269

if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1270

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1294

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1297

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1302

&pipe_ctx->link_config.dp_link_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1304

dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1305

dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1308

&pipe_ctx->link_config.dp_link_settings));

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1329

struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1387

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1390

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1391

audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1393

audio_output->signal = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1427

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1430

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1442

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1445

if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1449

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1455

(pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1456

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1464

pipe_ctx->stream_res.tg->inst + 1);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1470

pipe_ctx->pll_settings.ss_percentage;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1472

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1473

populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1478

const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1483

if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1487

get_surface_visual_confirm_color(pipe_ctx, &color);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1490

pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1493

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1494

pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1495

pipe_ctx->plane_res.scl_data.lb_params.depth,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1496

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1498

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1504

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1507

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1508

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1512

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1513

&pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1517

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1521

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1522

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1523

pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1531

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1532

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1539

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1541

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1542

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1543

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1544

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1545

&pipe_ctx->pll_settings)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1558

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1559

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1566

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1571

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1572

pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1582

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1586

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1590

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1593

link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1597

hws->funcs.disable_stream_gating(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1600

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1603

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1605

link_hwss->setup_audio_output(pipe_ctx, &audio_output,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1606

pipe_ctx->stream_res.audio->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1608

pipe_ctx->stream_res.audio->funcs->az_configure(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1609

pipe_ctx->stream_res.audio,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1610

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1612

&pipe_ctx->stream->audio_info,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1616

if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1617

dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1618

pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1622

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1623

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1625

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1626

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1630

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1631

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1655

if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1658

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1662

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1666

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1675

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1676

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1677

pipe_ctx->stream_res.tg, event_triggers, 2);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1679

if (!dc_is_virtual_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1680

pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1681

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1682

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1684

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1691

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1692

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1695

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1696

dc_is_virtual_signal(pipe_ctx->stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1697

dc->link_srv->set_dsc_enable(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1701

dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1708

if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1709

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1710

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1713

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1719

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1720

pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1721

pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1814

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1816

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1915

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1962

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1963

if (pipe_ctx &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1965

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1969

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1970

&pipe_ctx->pixel_rate_divider.div_factor1,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1971

&pipe_ctx->pixel_rate_divider.div_factor2);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1975

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2055

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2058

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2062

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2063

pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2064

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2072

pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2073

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2096

if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2099

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2100

res_ctx->pipe_ctx[i].plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2108

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2109

res_ctx->pipe_ctx[i].plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2122

static void set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2144

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2147

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2156

static void get_position(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2165

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2168

static void set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2184

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2191

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2192

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2204

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2220

if (res_ctx->pipe_ctx[i].stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2222

pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2225

if (pipe_ctx->pipe_idx != underlay_idx) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2235

if (!pipe_ctx->stream->link)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2239

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2243

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2247

if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2251

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2255

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2274

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2276

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2277

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2278

params.inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2297

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2298

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2299

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2310

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2311

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2317

if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2386

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2388

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2391

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2393

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2395

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2398

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2406

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2407

pipe_ctx->stream_res.audio,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2408

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2412

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2413

pipe_ctx->stream_res.audio,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2414

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2424

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2426

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2429

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2432

if (!dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2435

if (pipe_ctx->stream_res.audio != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2438

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2440

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2441

pipe_ctx->stream_res.audio,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2442

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2479

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2480

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2481

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2483

if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2486

if (pipe_ctx->stream == pipe_ctx_old->stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2487

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2489

pipe_ctx->clock_source, i);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2508

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2509

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2510

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2512

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2515

if (pipe_ctx->stream == pipe_ctx_old->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2516

pipe_ctx->stream->link->link_state_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2520

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2523

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2527

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2551

static void set_default_colors(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2556

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2557

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2559

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2563

pipe_ctx->stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2566

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2568

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2569

pipe_ctx->plane_res.xfm, &default_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2593

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2598

if (pipe_ctx->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2601

ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2603

if (pipe_ctx->bottom_pipe->plane_state->visible) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2604

if (pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2609

} else if (!pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2612

} else if (!pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2615

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2616

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2620

static void program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2628

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2633

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2636

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2639

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2641

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2646

pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2647

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2654

static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2656

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2662

pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2663

pipe_ctx->plane_res.mi);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2666

pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2668

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2669

if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2670

pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2672

!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2726

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2772

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

284

dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

287

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2917

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2919

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2920

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2933

set_default_colors(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2934

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2937

pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2941

pipe_ctx->stream->csc_color_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2943

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2944

(pipe_ctx->plane_res.xfm, &tbl_entry);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2947

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2952

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2955

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2957

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2959

program_scaler(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2970

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2974

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2980

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2981

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2982

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2983

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2985

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2986

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2994

pipe_ctx->pipe_idx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2995

(void *) pipe_ctx->plane_state,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2996

pipe_ctx->plane_state->address.grph.addr.high_part,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2997

pipe_ctx->plane_state->address.grph.addr.low_part,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2998

pipe_ctx->plane_state->src_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2999

pipe_ctx->plane_state->src_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3000

pipe_ctx->plane_state->src_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3001

pipe_ctx->plane_state->src_rect.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3002

pipe_ctx->plane_state->dst_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3003

pipe_ctx->plane_state->dst_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3004

pipe_ctx->plane_state->dst_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3005

pipe_ctx->plane_state->dst_rect.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3006

pipe_ctx->plane_state->clip_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3007

pipe_ctx->plane_state->clip_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3008

pipe_ctx->plane_state->clip_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3009

pipe_ctx->plane_state->clip_rect.height);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3015

pipe_ctx->pipe_idx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3016

pipe_ctx->plane_res.scl_data.viewport.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3017

pipe_ctx->plane_res.scl_data.viewport.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3018

pipe_ctx->plane_res.scl_data.viewport.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3019

pipe_ctx->plane_res.scl_data.viewport.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3020

pipe_ctx->plane_res.scl_data.recout.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3021

pipe_ctx->plane_res.scl_data.recout.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3022

pipe_ctx->plane_res.scl_data.recout.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3023

pipe_ctx->plane_res.scl_data.recout.y);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3041

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3043

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3047

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3048

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3049

pipe_ctx->stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3050

pipe_ctx->stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3051

pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3054

dce110_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3056

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3058

program_surface_visibility(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3072

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3075

int fe_idx = pipe_ctx->plane_res.mi ?

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3076

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3079

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3092

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3098

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3106

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3107

enum dc_color_space color_space = pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3110

tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3114

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3115

pipe_ctx->plane_res.xfm, &tbl_entry);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3119

static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3121

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3122

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3123

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3126

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3127

.viewport = pipe_ctx->plane_res.scl_data.viewport,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3128

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3129

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3130

.rotation = pipe_ctx->plane_state->rotation,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3131

.mirror = pipe_ctx->plane_state->horizontal_mirror

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3147

pos_cpy.x += pipe_ctx->plane_state->src_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3148

pos_cpy.y += pipe_ctx->plane_state->src_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3151

if (pipe_ctx->plane_state->address.type

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3155

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3164

static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3166

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3168

if (pipe_ctx->plane_res.ipp &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3169

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3170

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3171

pipe_ctx->plane_res.ipp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3173

if (pipe_ctx->plane_res.mi &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3174

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3175

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3176

pipe_ctx->plane_res.mi, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3178

if (pipe_ctx->plane_res.xfm &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3179

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3180

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3181

pipe_ctx->plane_res.xfm, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3184

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3189

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3191

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3198

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3219

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3221

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3222

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3226

pipe_ctx->stream->link->panel_cntl->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3232

void dce110_set_pipe(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3234

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3235

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3236

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3279

struct pipe_ctx *pipes =

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3280

link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

607

dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

610

struct transform *xfm = pipe_ctx->plane_res.xfm;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

631

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

636

ASSERT(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

638

if (pipe_ctx->stream_res.stream_enc == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

641

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

642

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

648

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

649

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

650

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

652

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

653

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

654

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

655

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

657

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

658

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

659

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

663

void dce110_enable_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

666

pipe_ctx->stream->link->cur_link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

667

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

668

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

670

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

673

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

675

link_hwss->setup_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

677

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

115

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

119

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

43

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

47

void dce110_enable_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

49

void dce110_disable_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

51

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

54

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

56

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

57

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

59

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

61

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

90

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

92

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

93

void dce110_set_pipe(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

101

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

105

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

124

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

126

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

127

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

128

params.inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

143

static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

148

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

149

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

151

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

155

pipe_ctx->stream->timing.display_color_depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

158

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

160

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

161

pipe_ctx->plane_res.xfm, &default_adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

182

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

188

if (!pipe_ctx->plane_state->visible)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

192

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

197

static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

200

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

202

switch (pipe_ctx->plane_res.scl_data.format) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

233

const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

240

dce60_get_surface_visual_confirm_color(pipe_ctx, &color);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

243

pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

246

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

247

pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

248

pipe_ctx->plane_res.scl_data.lb_params.depth,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

249

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

251

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

257

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

260

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

261

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

265

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

266

&pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

271

struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

273

struct mem_input *mi = pipe_ctx->plane_res.mi;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

274

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

288

dce60_set_default_colors(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

289

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

292

pipe_ctx->stream->output_color_space;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

296

pipe_ctx->stream->csc_color_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

298

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

299

(pipe_ctx->plane_res.xfm, &tbl_entry);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

302

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

307

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

310

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

312

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

314

dce60_program_scaler(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

329

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

349

pipe_ctx->pipe_idx,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

350

(void *) pipe_ctx->plane_state,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

351

pipe_ctx->plane_state->address.grph.addr.high_part,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

352

pipe_ctx->plane_state->address.grph.addr.low_part,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

353

pipe_ctx->plane_state->src_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

354

pipe_ctx->plane_state->src_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

355

pipe_ctx->plane_state->src_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

356

pipe_ctx->plane_state->src_rect.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

357

pipe_ctx->plane_state->dst_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

358

pipe_ctx->plane_state->dst_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

359

pipe_ctx->plane_state->dst_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

360

pipe_ctx->plane_state->dst_rect.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

361

pipe_ctx->plane_state->clip_rect.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

362

pipe_ctx->plane_state->clip_rect.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

363

pipe_ctx->plane_state->clip_rect.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

364

pipe_ctx->plane_state->clip_rect.height);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

370

pipe_ctx->pipe_idx,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

371

pipe_ctx->plane_res.scl_data.viewport.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

372

pipe_ctx->plane_res.scl_data.viewport.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

373

pipe_ctx->plane_res.scl_data.viewport.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

374

pipe_ctx->plane_res.scl_data.viewport.y,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

375

pipe_ctx->plane_res.scl_data.recout.width,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

376

pipe_ctx->plane_res.scl_data.recout.height,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

377

pipe_ctx->plane_res.scl_data.recout.x,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

378

pipe_ctx->plane_res.scl_data.recout.y);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

396

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

398

if (pipe_ctx->stream != stream)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

402

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

403

pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

404

pipe_ctx->stream->timing.h_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

405

pipe_ctx->stream->timing.v_total,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

406

pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

409

dce60_program_front_end_for_pipe(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

411

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

413

dce60_program_surface_visibility(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

55

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

71

if (res_ctx->pipe_ctx[i].stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

73

pipe_ctx = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

75

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

79

if (pipe_ctx->pipe_idx != underlay_idx) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

89

if (!pipe_ctx->stream->link)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

93

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

97

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

101

void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

104

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

110

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

111

!pipe_ctx->stream_res.tg ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

112

!pipe_ctx->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1137

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

115

if (pipe_ctx->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1152

static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1154

struct pipe_ctx *other_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

116

pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1179

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1183

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

119

if (!pipe_ctx->wait_is_required)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1191

if (pipe_ctx->top_pipe != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1199

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1201

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1202

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1203

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1204

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1205

&pipe_ctx->pll_settings)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1218

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1219

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

122

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1221

calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1222

pipe_ctx->pipe_dlg_param.vstartup_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1223

pipe_ctx->pipe_dlg_param.vupdate_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1224

pipe_ctx->pipe_dlg_param.vupdate_width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1225

pipe_ctx->pipe_dlg_param.pstate_keepout,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1226

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1233

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1235

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1236

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1252

if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1253

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1254

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1257

if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1258

!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1259

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1260

hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1261

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1265

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

127

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1283

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1289

if (pipe_ctx->stream_res.stream_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1290

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1294

link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

130

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1301

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1302

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1303

else if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1304

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1306

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1308

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1315

pipe_ctx->stream_res.audio, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1316

pipe_ctx->stream_res.audio = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1324

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1326

if (pipe_ctx->stream_res.abm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1327

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1329

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1331

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1332

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1333

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1334

pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1338

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1344

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1346

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

135

if (frame_count - pipe_ctx->wait_frame_count > 2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1367

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1368

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1369

if (pipe_ctx != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1370

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

138

vblank_start = pipe_ctx->pipe_dlg_param.vblank_start;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1380

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1381

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1382

if (pipe_ctx != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1383

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1390

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1391

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1392

if (pipe_ctx != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1393

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1402

struct pipe_ctx *pipe_ctx =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1403

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1404

if (pipe_ctx != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1405

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1429

TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1442

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1445

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1446

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1450

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1462

if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1463

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1520

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1523

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1524

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1527

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1533

if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1534

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1535

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1542

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1543

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1545

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1546

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1547

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1548

pipe_ctx->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1549

pipe_ctx->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1550

pipe_ctx->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1553

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1558

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1561

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1566

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1586

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

159

pipe_ctx->wait_is_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1592

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1612

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1616

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1629

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1632

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1643

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1650

pipe_ctx->stream != NULL &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1651

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1652

pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

166

pipe_ctx->next_vupdate = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1664

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1669

pipe_ctx->stream_res.tg = tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

167

pipe_ctx->wait_frame_count = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1670

pipe_ctx->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1672

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1673

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

168

pipe_ctx->wait_is_required = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1681

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1684

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1689

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1691

pipe_ctx->stream_res.tg = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1692

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

177

void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

183

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

184

!pipe_ctx->stream_res.tg ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

185

!pipe_ctx->stream_res.stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

188

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

191

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

194

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1955

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1956

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1957

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1965

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1966

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1979

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1981

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1982

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1983

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1985

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1987

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1994

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2006

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2010

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2015

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2017

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2018

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2028

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

203

pipe_ctx->next_vupdate = vupdate_start;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2031

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2034

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

208

pipe_ctx->wait_frame_count = cur_frame;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2109

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

211

pipe_ctx->wait_frame_count = cur_frame + 1 - optc1->max_frame_count;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2112

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

213

pipe_ctx->wait_frame_count = cur_frame + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2149

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

216

pipe_ctx->wait_is_required = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2190

static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2192

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2201

if (!pipe_ctx->stream_res.stream_enc || !pipe_ctx->stream_res.tg)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2204

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2207

dc->hwss.get_position(&pipe_ctx, 1, &position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

223

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2238

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

224

struct pipe_ctx *old_pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

229

old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

230

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

231

tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2353

static bool is_low_refresh_rate(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2362

static uint8_t get_clock_divider(struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

237

if (pipe_ctx->top_pipe ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

238

!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2384

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

239

(!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

241

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

245

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

247

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2477

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2543

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2624

struct pipe_ctx *grouped_pipes[])

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2732

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2744

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2750

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2751

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2755

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2761

if (!pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2762

&& pipe_ctx->plane_state

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2763

&& pipe_ctx->plane_state->flip_int_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2765

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2769

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2777

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2781

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2782

} else if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2787

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2790

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2794

static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2796

if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2797

if (pipe_ctx->top_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2798

struct pipe_ctx *top = pipe_ctx->top_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2812

static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2820

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2827

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2832

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2833

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2846

if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2847

dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2849

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2853

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2854

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2877

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2887

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2891

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2895

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2905

pipe_ctx->stream->output_color_space)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2906

&& pipe_ctx->plane_state->pre_multiplied_alpha);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2907

if (pipe_ctx->plane_state->global_alpha) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2909

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2918

if (pipe_ctx->plane_state->global_alpha)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2919

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2934

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2936

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2958

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2965

static void update_scaler(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2968

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2970

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2971

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2973

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2974

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2979

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2983

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2985

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3038

pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3054

&pipe_ctx->dlg_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3055

&pipe_ctx->ttu_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3056

&pipe_ctx->rq_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3057

&pipe_ctx->pipe_dlg_param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3060

&pipe_ctx->dlg_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3061

&pipe_ctx->ttu_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3064

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3073

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3080

update_scaler(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3088

&pipe_ctx->plane_res.scl_data.viewport,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3089

&pipe_ctx->plane_res.scl_data.viewport_c);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3092

if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3093

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3094

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3097

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3102

dc->hwss.program_gamut_remap(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3105

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3106

pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3107

pipe_ctx->stream->csc_color_matrix.matrix,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3108

pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3133

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3135

if (is_pipe_tree_visible(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3141

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3146

struct stream_resource *stream_res = &pipe_ctx->stream_res;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3147

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3171

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3175

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3183

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3185

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3197

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3198

pipe_ctx->plane_res.dpp, hw_mult);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3203

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3208

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3209

bool blank = !is_pipe_tree_visible(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3211

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3212

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3213

calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3214

pipe_ctx->pipe_dlg_param.vstartup_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3215

pipe_ctx->pipe_dlg_param.vupdate_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3216

pipe_ctx->pipe_dlg_param.vupdate_width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3217

pipe_ctx->pipe_dlg_param.pstate_keepout);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3219

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3220

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3223

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3225

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3228

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3229

dcn10_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3231

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3233

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3235

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3236

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3237

pipe_ctx->plane_state->update_flags.bits.gamma_change)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3246

if (pipe_ctx->plane_state->update_flags.bits.full_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3247

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3253

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3258

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3259

tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3265

if (pipe_ctx->top_pipe ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3266

!pipe_ctx->stream || !pipe_ctx->plane_state ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3277

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3278

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3289

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3291

if (!pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3292

!pipe_ctx->prev_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3293

pipe_ctx->stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3294

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3297

false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3302

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3303

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3306

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3408

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3431

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3434

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3443

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3452

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3455

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3469

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3470

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3516

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3519

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3530

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3531

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3535

pipe_ctx->stream_res.tg->funcs->program_stereo(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3536

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3558

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3567

if (!pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3571

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3574

if (pipe_ctx->stream_res.tg &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3575

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3577

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3597

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3599

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3600

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3602

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3607

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3608

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3618

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3643

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3645

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3646

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3647

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3649

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3650

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3651

.viewport = pipe_ctx->plane_res.scl_data.viewport,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3652

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3653

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3654

.rotation = pipe_ctx->plane_state->rotation,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3655

.mirror = pipe_ctx->plane_state->horizontal_mirror,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3656

.stream = pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3659

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3660

(pipe_ctx->prev_odm_pipe != NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3662

int x_plane = pipe_ctx->plane_state->dst_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3663

int y_plane = pipe_ctx->plane_state->dst_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3666

int clip_x = pipe_ctx->plane_state->clip_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3667

int clip_width = pipe_ctx->plane_state->clip_rect.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3669

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3670

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3671

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3694

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3695

pipe_ctx->plane_state->dst_rect.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3696

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3697

pipe_ctx->plane_state->dst_rect.height;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3699

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3700

pipe_ctx->plane_state->dst_rect.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3701

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3702

pipe_ctx->plane_state->dst_rect.height;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3703

clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3704

pipe_ctx->plane_state->dst_rect.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3705

clip_width = clip_width * pipe_ctx->plane_state->src_rect.width /

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3706

pipe_ctx->plane_state->dst_rect.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3722

x_pos += pipe_ctx->plane_state->src_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3723

y_pos += pipe_ctx->plane_state->src_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3744

if (pipe_ctx->plane_state->address.type

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3748

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3771

pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3772

(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3779

pipe_ctx->plane_res.scl_data.viewport.height;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3781

pipe_ctx->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3801

if (pipe_ctx->bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3803

pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3806

pipe_ctx->top_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3809

if (pipe_ctx->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3811

pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3814

pipe_ctx->prev_odm_pipe->plane_res.scl_data.viewport.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3855

pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.viewport.y) +

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3856

pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3863

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3865

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3868

pipe_ctx->plane_res.hubp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3869

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3870

pipe_ctx->plane_res.dpp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3873

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3875

uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3881

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3896

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3897

pipe_ctx->plane_res.dpp, &opt_attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3918

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3920

const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3941

pipe_ctx->pipe_dlg_param.vstartup_start + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3946

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3950

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3951

int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3962

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3966

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3967

int vline_pos = pipe_ctx->stream->periodic_interrupt.lines_offset;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3969

if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_UPDATE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3975

vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3981

} else if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_SYNC) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3991

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3993

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3997

dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4002

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4004

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4005

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4016

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4020

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4025

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4029

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4032

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4040

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4044

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4045

pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4046

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4127

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4131

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

813

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

815

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

816

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

104

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

109

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

111

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

120

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

122

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

130

struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

135

struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

139

struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

140

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

141

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

144

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

145

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

146

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

152

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

154

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

157

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

159

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

160

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

171

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

183

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

184

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

185

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

188

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

196

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

207

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

214

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

217

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

36

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

39

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

42

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

44

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

55

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

59

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

62

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

67

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

69

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

72

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

76

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

78

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

80

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

81

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1002

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1009

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1014

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1029

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1032

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1033

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1044

if (pipe_ctx->top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1048

else if (pipe_ctx->stream->out_transfer_func.type ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1070

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1072

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1090

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1092

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1116

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1120

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1128

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1129

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1191

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1193

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1195

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1196

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1197

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1199

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1205

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1206

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1210

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1211

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1216

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1220

struct stream_resource *stream_res = &pipe_ctx->stream_res;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1221

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1225

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1235

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1245

odm_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1274

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1282

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1298

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1301

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1308

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1312

void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1318

dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1321

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1324

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1327

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1328

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1377

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1380

if (!pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1381

&& pipe_ctx->plane_state

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1382

&& pipe_ctx->plane_state->flip_int_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1383

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1384

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1393

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1396

struct pipe_ctx *temp_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1493

struct pipe_ctx *old_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1494

struct pipe_ctx *new_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1685

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1686

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1687

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1690

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

if (pipe_ctx->update_flags.bits.dppclk)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1695

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1703

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1704

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1709

&pipe_ctx->hubp_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1710

&pipe_ctx->global_sync,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1711

&pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1715

&pipe_ctx->dlg_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1716

&pipe_ctx->ttu_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1717

&pipe_ctx->rq_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1718

&pipe_ctx->pipe_dlg_param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1722

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1723

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1725

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1729

&pipe_ctx->hubp_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1733

&pipe_ctx->dlg_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1734

&pipe_ctx->ttu_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1738

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1739

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1765

if (pipe_ctx->update_flags.bits.mpcc

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

|| pipe_ctx->update_flags.bits.plane_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1770

hws->funcs.update_mpcc(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1773

if (pipe_ctx->update_flags.bits.scaler ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1777

pipe_ctx->stream->update_flags.bits.scaling) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1778

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1779

ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1781

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1782

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1785

if (pipe_ctx->update_flags.bits.viewport ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1792

&pipe_ctx->plane_res.scl_data.viewport,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1793

&pipe_ctx->plane_res.scl_data.viewport_c);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1798

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1802

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1803

pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1804

dc->hwss.set_cursor_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1805

dc->hwss.set_cursor_position(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1808

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1813

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1814

|| pipe_ctx->update_flags.bits.plane_changed

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1815

|| pipe_ctx->stream->update_flags.bits.gamut_remap

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1817

|| pipe_ctx->stream->update_flags.bits.out_csc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1819

dc->hwss.program_gamut_remap(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1823

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1824

pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1825

pipe_ctx->stream->csc_color_matrix.matrix,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1829

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1830

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1831

pipe_ctx->update_flags.bits.opp_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1842

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1855

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1856

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1858

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1863

params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1864

params.subvp_save_surf_addr.subvp_index = pipe_ctx->subvp_index;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1867

dc->hwss.update_plane_addr(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1870

if (pipe_ctx->update_flags.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1877

static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1879

struct pipe_ctx *other_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1905

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1909

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1910

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1911

dcn20_calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1912

pipe_ctx->pipe_dlg_param.vstartup_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1913

pipe_ctx->pipe_dlg_param.vupdate_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1914

pipe_ctx->pipe_dlg_param.vupdate_width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1915

pipe_ctx->pipe_dlg_param.pstate_keepout);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1917

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1918

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1920

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1921

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1924

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1929

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1935

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1936

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1937

pipe_ctx->update_flags.bits.odm ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1938

pipe_ctx->stream->update_flags.bits.abm_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1939

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1940

!pipe_ctx->plane_state ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1941

!pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1945

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1946

&& !pipe_ctx->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1947

dcn20_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1949

if (pipe_ctx->update_flags.bits.odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1950

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1952

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1954

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1956

dcn20_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1962

if (pipe_ctx->update_flags.bits.det_size) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1972

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1973

pipe_ctx->plane_state->update_flags.raw ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1974

pipe_ctx->stream->update_flags.raw))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1975

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1977

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1978

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1979

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1981

if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1982

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1983

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1984

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1985

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1986

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1992

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1993

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1994

pipe_ctx->stream->update_flags.bits.out_tf)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1995

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2002

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2003

|| pipe_ctx->update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2005

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2006

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2008

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2009

pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2011

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2012

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2013

&pipe_ctx->stream->bit_depth_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2014

&pipe_ctx->stream->clamping);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2018

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2019

if (pipe_ctx->stream_res.abm) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2020

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2021

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2022

pipe_ctx->stream->abm_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2026

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2027

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2033

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2034

pipe_ctx->stream_res.test_pattern_params.test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2035

pipe_ctx->stream_res.test_pattern_params.color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2036

pipe_ctx->stream_res.test_pattern_params.color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2038

pipe_ctx->stream_res.test_pattern_params.width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2039

pipe_ctx->stream_res.test_pattern_params.height,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2040

pipe_ctx->stream_res.test_pattern_params.offset);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2052

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2061

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2073

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2075

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2088

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2089

&context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2095

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2097

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2099

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2101

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2113

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2114

&& !context->res_ctx.pipe_ctx[i].top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2115

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2116

&& context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2117

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2121

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2122

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2132

(context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2133

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i])

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2140

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2143

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2144

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2149

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2162

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

219

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2212

struct pipe_ctx *opp_head)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2255

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2256

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2258

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2262

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2271

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2285

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2286

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

231

if (pipe_ctx->stream_res.gsl_group > 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2311

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

236

pipe_ctx->stream_res.gsl_group = group_idx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2389

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2433

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2473

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2475

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2476

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2477

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2478

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2479

pipe_ctx->dlg_regs.min_dst_y_next_start);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2500

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2502

if (pipe_ctx->plane_state == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2505

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2506

bool blank = !is_pipe_tree_visible(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2508

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2509

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2510

dcn20_calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2511

pipe_ctx->pipe_dlg_param.vstartup_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2512

pipe_ctx->pipe_dlg_param.vupdate_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2513

pipe_ctx->pipe_dlg_param.vupdate_width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2514

pipe_ctx->pipe_dlg_param.pstate_keepout);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2516

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2517

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2519

if (pipe_ctx->prev_odm_pipe == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2520

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2523

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2526

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2527

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2528

&pipe_ctx->dlg_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2529

&pipe_ctx->ttu_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2530

&pipe_ctx->rq_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2531

&pipe_ctx->pipe_dlg_param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

258

group_idx = pipe_ctx->stream_res.gsl_group;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2602

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2604

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2611

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2615

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2616

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

262

pipe_ctx->stream_res.gsl_group = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2626

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2630

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2631

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2633

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2641

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2644

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2648

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2650

pipe_ctx->stream->dmdata_address.quad_part;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2702

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2704

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2705

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2706

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2708

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2710

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2718

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2729

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2733

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2738

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2741

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2743

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2744

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2754

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2757

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2761

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2764

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2766

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2770

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2774

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2778

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2780

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2781

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2782

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2783

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2786

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2787

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2788

pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2789

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2797

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2799

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2800

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2811

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2814

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2815

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2820

if (pipe_ctx->stream_res.stream_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2821

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2831

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2832

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2833

else if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2834

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2837

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2839

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2846

pipe_ctx->stream_res.audio, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2847

pipe_ctx->stream_res.audio = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2855

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2857

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2859

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

286

if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2861

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2862

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2863

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2864

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2866

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

287

pipe_ctx->stream_res.tg->funcs->set_gsl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2871

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2875

&pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2878

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

288

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2880

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2881

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2892

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2893

pipe_ctx->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2894

pipe_ctx->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2895

pipe_ctx->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2896

pipe_ctx->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2898

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

290

if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

291

pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2910

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2911

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2912

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

292

pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2920

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2921

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2933

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2935

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2937

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2941

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2947

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2948

if (pipe_ctx->plane_state->global_alpha) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2950

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2959

if (pipe_ctx->plane_state->global_alpha)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2960

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2970

if (pipe_ctx->plane_state->format

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

298

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2985

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2986

!pipe_ctx->update_flags.bits.mpcc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2988

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

301

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3010

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3013

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3017

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

302

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3020

pipe_ctx->stream->link->cur_link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3022

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3023

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3027

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3028

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3029

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

pipe_ctx->plane_res.hubp, flip_immediate);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3035

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3036

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3041

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3043

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3044

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3045

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3048

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3074

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3075

pipe_ctx->pixel_rate_divider.div_factor1,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3076

pipe_ctx->pixel_rate_divider.div_factor2);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3078

link_hwss->setup_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3080

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3082

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3085

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3087

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3105

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3107

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3108

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3110

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3116

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3117

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3196

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3200

pipe_ctx->stream_res.tg = tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3201

pipe_ctx->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3203

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3204

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3205

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3209

pipe_ctx->stream_res.opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3215

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3216

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3218

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3233

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3235

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3237

pipe_ctx->stream_res.tg = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3238

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3252

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3259

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

394

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

397

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

398

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

399

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

710

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

713

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

714

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

716

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

721

if (pipe_ctx->stream_res.gsl_group != 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

722

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

727

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

736

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

737

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

739

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

740

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

741

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

742

pipe_ctx->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

743

pipe_ctx->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

744

pipe_ctx->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

745

pipe_ctx->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

746

pipe_ctx->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

750

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

752

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

753

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

757

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

760

dcn20_plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

769

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

772

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

774

dcn20_blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

818

static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

820

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

832

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

837

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

847

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

851

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

856

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

857

pipe_ctx->pixel_rate_divider.div_factor1,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

858

pipe_ctx->pixel_rate_divider.div_factor2);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

864

if (pipe_ctx->top_pipe != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

869

opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

873

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

874

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

876

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

877

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

884

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

886

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

887

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

888

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

889

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

890

&pipe_ctx->pll_settings)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

895

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

897

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

904

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

905

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

906

dto_params.timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

920

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

922

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

923

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

925

pipe_ctx->pipe_dlg_param.vready_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

926

pipe_ctx->pipe_dlg_param.vstartup_start,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

927

pipe_ctx->pipe_dlg_param.vupdate_offset,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

928

pipe_ctx->pipe_dlg_param.vupdate_width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

929

pipe_ctx->pipe_dlg_param.pstate_keepout,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

930

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

958

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

961

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

972

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

981

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

982

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

983

pipe_ctx->stream_res.tg, event_triggers, 2);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

993

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

994

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

995

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

112

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

122

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

123

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

124

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

131

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

146

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

155

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

160

struct pipe_ctx *old_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

161

struct pipe_ctx *new_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

164

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

168

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

172

struct pipe_ctx *opp_head);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

34

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

36

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

43

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

44

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

45

bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

47

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

50

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

54

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

55

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

60

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

64

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

68

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

83

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

86

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

87

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

88

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

91

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

98

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

133

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

137

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

145

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

149

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

150

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

160

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

306

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

310

pipe_ctx->stream_res.tg = tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

311

pipe_ctx->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

313

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

314

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

315

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

pipe_ctx->stream_res.opp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

323

res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

324

pipe_ctx->stream_res.opp = res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

341

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

343

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

345

pipe_ctx->stream_res.tg = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

346

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

377

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

380

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

381

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

385

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

411

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

422

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

424

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

426

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

431

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

435

pipe_ctx, &blnd_cfg.black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

438

pipe_ctx, &blnd_cfg.black_color);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

441

dc, pipe_ctx->stream->output_color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

452

if (pipe_ctx->plane_state->global_alpha_value)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

453

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

485

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

486

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

511

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

521

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

527

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

556

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

558

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

560

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq, &attributes->address);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

562

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

563

pipe_ctx->plane_res.hubp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

564

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.dpp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

568

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

57

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

571

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

573

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

574

&pipe_ctx->stream->dmdata_address);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

578

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

580

pipe_ctx->stream->dmdata_address.quad_part;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

59

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

591

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

595

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

60

bool sec_split = pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

600

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

604

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

606

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

609

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

61

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

(pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

66

pipe_ctx->stream->timing.timing_3d_format ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

73

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

31

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

33

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

35

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

37

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

38

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

41

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

129

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

131

if (!pipe_ctx->stream->dpms_off)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

134

pipe_ctx->stream->dpms_off = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

136

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

137

pipe_ctx->stream->dpms_off = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

179

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

181

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

182

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

184

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

188

if (pipe_ctx->stream->abm_level == 0 || pipe_ctx->stream->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

193

dce110_set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

212

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

214

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

215

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

217

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

226

dce110_set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

244

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

247

struct dc_context *dc = pipe_ctx->stream->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

248

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

249

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

250

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

261

dce110_set_backlight_level(pipe_ctx, backlight_level_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

294

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

296

if (pipe_ctx->stream == stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

297

(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

48

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

52

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

53

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

54

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1154

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1176

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1183

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1206

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1208

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1222

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

232

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

234

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

253

static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

256

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

257

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

258

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

314

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

318

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

343

if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

345

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

348

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

354

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

359

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

360

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

365

if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

366

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

370

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

373

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

379

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

380

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

384

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

392

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

395

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

396

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

401

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

403

ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

407

else if (pipe_ctx->stream->out_transfer_func.type ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

603

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

605

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

608

if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

609

wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

830

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

832

if (pipe_ctx == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

835

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

836

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

837

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

841

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

842

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

843

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

844

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

845

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

846

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

851

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

856

ASSERT(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

858

if (pipe_ctx->stream_res.stream_enc == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

861

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

862

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

868

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

869

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

870

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

872

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

873

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

874

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

875

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

877

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

878

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

879

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

883

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

885

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

886

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

888

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

894

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

895

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

100

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

59

bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

63

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

66

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

69

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

71

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

72

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

73

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

86

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

94

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

378

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

383

ASSERT(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

385

if (pipe_ctx->stream_res.stream_enc == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

388

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

389

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

395

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

396

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

397

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

398

else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

399

if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

400

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

401

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

402

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

404

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

405

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

406

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

409

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

410

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

411

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

412

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

414

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

415

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

416

&pipe_ctx->stream_res.encoder_info_frame);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

513

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

519

if (pipe_ctx->stream_res.stream_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

520

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

523

ASSERT(!pipe_ctx->top_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

525

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

527

link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

532

if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

534

dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

539

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

540

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

543

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

545

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

546

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

547

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

548

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

554

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

557

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

559

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

561

link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

566

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

574

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

575

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

576

else if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

577

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

583

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

584

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

587

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

588

dc_is_virtual_signal(pipe_ctx->stream->signal)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

589

dc->link_srv->set_dsc_enable(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

593

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

595

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

602

pipe_ctx->stream_res.audio, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

603

pipe_ctx->stream_res.audio = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

608

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

610

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

622

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

623

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

624

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

632

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

633

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

666

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

680

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

707

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

710

struct dc_context *dc = pipe_ctx->stream->ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

711

struct abm *abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

712

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

713

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

44

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

54

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

61

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

107

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

114

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

127

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

128

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

134

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

135

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

139

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

140

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

149

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

152

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

155

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

172

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

174

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

177

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

178

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

182

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

185

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

186

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

190

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

191

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

203

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

209

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

210

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

212

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

215

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

327

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

329

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

333

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

334

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

336

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

339

} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

345

} else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

369

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

373

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

375

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

377

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

379

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

380

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

384

static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

401

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

408

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

429

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

431

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

438

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

483

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

488

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

489

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

490

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

491

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

492

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

494

&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

495

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

72

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

74

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

75

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

76

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

80

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

90

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

97

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

40

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1013

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1015

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1016

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1017

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1018

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1034

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1044

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1051

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1057

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1062

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1071

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1084

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1085

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1091

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1092

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1096

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1097

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1108

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1111

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1114

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1131

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1133

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1136

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1137

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1139

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1142

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1143

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1147

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1148

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1150

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1156

pipe_ctx->stream->timing.pixel_encoding,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1160

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1161

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1163

dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1166

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1175

if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1180

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1183

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1185

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1190

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1191

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1193

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1210

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1227

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1231

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1233

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1236

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1238

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1239

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1246

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1252

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1255

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1274

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1276

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1283

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1302

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1306

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1309

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1312

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1314

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1318

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1322

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1324

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1325

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1326

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1327

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1328

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1333

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1334

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1335

pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1336

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1343

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1345

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1347

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1350

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1374

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1379

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1380

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1381

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1382

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1383

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1385

&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1386

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1430

struct pipe_ctx *phantom_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1436

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1461

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1542

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1543

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1544

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1555

if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1556

(pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1576

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1577

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1594

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1595

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1596

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1598

if (pipe_ctx->stream == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1601

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1604

if (pipe_ctx->stream == pipe_ctx_old->stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1605

pipe_ctx->stream->link->link_state_valid) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1609

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1612

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1617

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1720

const struct pipe_ctx *cur_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1721

const struct pipe_ctx *new_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1740

const struct pipe_ctx *cur_pipe, *new_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1744

cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1745

new_pipe = &new_ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1822

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1826

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

232

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

354

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

356

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

375

struct pipe_ctx *top_pipe_to_program,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

381

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

385

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

440

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

442

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

443

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

444

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

445

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

477

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

479

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

480

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

481

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

523

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

528

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

554

if (pipe_ctx->stream_res.opp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

555

pipe_ctx->stream_res.opp->ctx &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

557

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

563

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

566

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

567

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

572

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

574

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

578

else if (pipe_ctx->stream->out_transfer_func.type ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

609

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

628

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

629

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

674

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

734

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

102

struct pipe_ctx *phantom_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

104

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

50

bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

54

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

58

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

61

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

74

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

76

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

84

struct pipe_ctx *top_pipe_to_program,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

89

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

92

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1036

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1037

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1125

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1402

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1422

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1425

if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1426

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1427

struct dc *dc = pipe_ctx[i]->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1436

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1444

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1457

pipe_ctx[i]->stream_res.tg->funcs->

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1458

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1462

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1472

if (!pipe_ctx[i])

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1475

if (pipe_ctx[i]->stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1476

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1483

if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1484

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1485

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal(pipe_ctx[i]->stream_res.tg, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1490

static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1502

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1503

struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1504

const struct dc *dc = pipe_ctx->stream->link->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1506

if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1510

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1545

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1547

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1549

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1552

if (should_avoid_empty_tu(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1555

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

327

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

329

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

330

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

331

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

337

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

347

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

354

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

363

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

369

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

370

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

383

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

384

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

390

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

391

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

395

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

396

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

405

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

408

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

411

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

428

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

430

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

433

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

434

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

438

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

441

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

442

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

446

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

447

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

459

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

465

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

466

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

468

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

471

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

638

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

644

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

664

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

668

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

681

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

684

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

695

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

702

pipe_ctx->stream != NULL &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

703

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

704

pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

716

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

721

pipe_ctx->stream_res.tg = tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

722

pipe_ctx->pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

724

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

725

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

726

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

733

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

734

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

736

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

741

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

743

pipe_ctx->stream_res.tg = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

744

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

815

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

818

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

823

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

826

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

831

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

832

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

844

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

848

if (!pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

849

&& pipe_ctx->plane_state

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

850

&& pipe_ctx->plane_state->flip_int_enabled

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

851

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

852

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

858

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

860

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

861

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

865

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

870

if (pipe_ctx->stream_res.gsl_group != 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

871

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

876

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

888

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

889

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

890

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

891

pipe_ctx->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

892

pipe_ctx->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

893

pipe_ctx->plane_state = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

898

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

901

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

902

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

906

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

910

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

919

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

947

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

952

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

955

if (pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

956

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

959

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

961

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

962

update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

964

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

965

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

967

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

971

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

972

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

981

if (pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

982

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

984

if (pipe_ctx->stream_res.hpo_dp_stream_enc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

985

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

100

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

61

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

62

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

64

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

91

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

94

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

97

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1024

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1028

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1029

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

103

if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1030

pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1031

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1032

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1034

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

104

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1073

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1075

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1076

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1077

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1079

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

108

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1080

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1081

.viewport = pipe_ctx->plane_res.scl_data.viewport,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1082

.recout = pipe_ctx->plane_res.scl_data.recout,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1083

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1084

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1085

.rotation = pipe_ctx->plane_state->rotation,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1086

.mirror = pipe_ctx->plane_state->horizontal_mirror,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1087

.stream = pipe_ctx->stream

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1090

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1091

(pipe_ctx->prev_odm_pipe != NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1093

struct pipe_ctx *prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1102

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1103

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1104

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1129

x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1130

pipe_ctx->stream->src.width;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1131

y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1132

pipe_ctx->stream->src.height;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1146

x_pos += pipe_ctx->plane_state->src_rect.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1147

y_pos += pipe_ctx->plane_state->src_rect.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1154

prev_odm_pipe = pipe_ctx->prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1185

pipe_ctx->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1186

(pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1188

bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1190

x_pos = pipe_ctx->plane_res.scl_data.recout.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1200

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

124

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

125

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1252

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

129

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1346

const struct pipe_ctx *top_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1349

const struct pipe_ctx *pipe_ctx = top_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1352

while (pipe_ctx != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1353

if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1354

pipe_ctx->plane_state->dcc.enable &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1355

pipe_ctx->plane_state->flip_immediate &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1356

pipe_ctx->plane_state->update_flags.bits.addr_update) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1362

pipe_ctx = pipe_ctx->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1467

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1469

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1470

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1471

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1472

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1473

pipe_ctx->dlg_regs.min_dst_y_next_start);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1524

struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1527

struct pipe_ctx *old_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1528

struct pipe_ctx *new_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1529

struct pipe_ctx *old_opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1530

struct pipe_ctx *old_otg_master;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1533

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1554

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1563

struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1565

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1607

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1611

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1616

params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1618

params.timing = pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1620

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1622

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1623

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1624

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1625

pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1626

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1627

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1664

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1666

struct pipe_ctx *opp_heads[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1667

struct pipe_ctx *dpp_pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1684

struct pipe_ctx *dpp_pipe = dpp_pipes[dpp_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1701

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1706

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1718

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1728

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1740

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1753

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1761

struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1762

struct pipe_ctx *odm_pipe, *mpc_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1765

for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1777

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1778

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1785

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1786

if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1787

pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1794

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1795

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1797

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1813

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1816

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1817

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1820

if (pipe_ctx->stream_res.stream_enc == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1821

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1831

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1832

dc->link_srv->set_dpms_off(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1833

else if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1834

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1837

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1839

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1846

pipe_ctx->stream_res.audio, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1847

pipe_ctx->stream_res.audio = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1855

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1857

dc->hwss.set_abm_immediate_disable(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1859

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1861

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1862

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1863

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1864

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1866

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1872

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1876

&pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1882

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1890

pipe_ctx->stream = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1891

pipe_ctx->top_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1892

pipe_ctx->bottom_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1893

pipe_ctx->next_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1894

pipe_ctx->prev_odm_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1896

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1908

struct pipe_ctx *pipe_ctx_old =

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1909

&dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1910

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1918

if (!pipe_ctx->stream ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1919

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1932

static unsigned int dcn401_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1934

struct pipe_ctx *other_pipe;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1960

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1964

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1965

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1966

dcn401_calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1967

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1968

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1969

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1970

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1972

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1973

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1975

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1976

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1979

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1984

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1990

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1991

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1992

pipe_ctx->update_flags.bits.odm ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1993

pipe_ctx->stream->update_flags.bits.abm_level)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1994

hws->funcs.blank_pixel_data(dc, pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1995

!pipe_ctx->plane_state ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1996

!pipe_ctx->plane_state->visible);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2000

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2001

&& !pipe_ctx->prev_odm_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2002

dcn401_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2004

if (pipe_ctx->update_flags.bits.odm)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2005

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2007

if (pipe_ctx->update_flags.bits.enable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2009

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2011

dc->hwss.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2017

if (pipe_ctx->update_flags.bits.det_size) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2020

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2023

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2026

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2027

pipe_ctx->plane_state->update_flags.raw ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2028

pipe_ctx->stream->update_flags.raw))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2029

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2031

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2032

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2033

hws->funcs.set_hdr_multiplier(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2035

if (pipe_ctx->plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2036

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2037

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2038

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2039

pipe_ctx->update_flags.bits.enable))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2040

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2046

if (pipe_ctx->update_flags.bits.enable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2047

pipe_ctx->update_flags.bits.plane_changed ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2048

pipe_ctx->stream->update_flags.bits.out_tf)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2049

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2056

if (pipe_ctx->update_flags.bits.enable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2057

|| pipe_ctx->update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2059

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2060

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2062

pipe_ctx->stream->timing.display_color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2063

pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2065

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2066

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2067

&pipe_ctx->stream->bit_depth_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2068

&pipe_ctx->stream->clamping);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2072

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2073

if (pipe_ctx->stream_res.abm) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2074

dc->hwss.set_pipe(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2075

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2076

pipe_ctx->stream->abm_level);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2080

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2081

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2087

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2088

pipe_ctx->stream_res.test_pattern_params.test_pattern,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2089

pipe_ctx->stream_res.test_pattern_params.color_space,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2090

pipe_ctx->stream_res.test_pattern_params.color_depth,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2092

pipe_ctx->stream_res.test_pattern_params.width,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2093

pipe_ctx->stream_res.test_pattern_params.height,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2094

pipe_ctx->stream_res.test_pattern_params.offset);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2106

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2115

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2129

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2131

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2144

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2145

&context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2151

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2153

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2155

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2157

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2169

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2170

&& !context->res_ctx.pipe_ctx[i].top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2171

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2172

&& context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2173

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2178

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2179

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2188

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2189

(context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2190

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2194

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2197

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2200

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2201

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2206

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2244

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2277

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2278

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2280

&dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2283

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2284

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2293

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2307

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2308

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2334

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2415

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2417

if (pipe_ctx->plane_state == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2420

if (pipe_ctx->top_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2421

bool blank = !is_pipe_tree_visible(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2423

pipe_ctx->stream_res.tg->funcs->program_global_sync(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2424

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2425

dcn401_calculate_vready_offset_for_group(pipe_ctx),

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2426

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2427

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2428

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2429

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2431

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2432

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2434

if (pipe_ctx->prev_odm_pipe == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2435

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2438

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2441

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2442

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2443

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2444

&pipe_ctx->hubp_regs,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2445

&pipe_ctx->global_sync,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2446

&pipe_ctx->stream->timing);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2454

struct pipe_ctx *old_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2455

struct pipe_ctx *new_pipe)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

372

static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

380

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

382

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

384

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

385

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

387

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

406

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

410

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

411

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

428

dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

602

void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

604

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

611

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

614

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

615

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

616

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

623

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

628

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

665

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

668

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

669

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

674

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

676

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

680

else if (pipe_ctx->stream->out_transfer_func.type ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

698

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

701

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

718

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

724

struct pipe_ctx *opp_heads[MAX_PIPES],

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

729

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

733

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

735

*opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

758

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

763

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

768

struct pipe_ctx *opp_heads[MAX_PIPES] = {0};

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

777

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

780

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

785

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

792

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

793

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

794

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

795

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

803

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

810

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

812

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

813

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

814

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

815

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

816

&pipe_ctx->pll_settings)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

822

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

826

patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

827

patched_crtc_timing.h_total = patched_crtc_timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

828

patched_crtc_timing.pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

831

pipe_ctx->stream_res.tg->funcs->program_timing(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

832

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

834

(unsigned int)pipe_ctx->global_sync.dcn4x.vready_offset_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

835

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

836

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

837

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

838

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

839

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

852

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

853

pipe_ctx->stream_res.opp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

856

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

859

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

865

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

87

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

871

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

872

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

873

pipe_ctx->stream_res.tg, event_triggers, 2);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

883

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

884

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

885

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

91

unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

910

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

917

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

918

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

92

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

920

pipe_ctx->stream->link->cur_link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

923

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

924

*dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

925

*phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

928

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

929

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

947

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

95

if (pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

950

struct timing_generator *tg = pipe_ctx->stream_res.tg;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

951

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

952

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

953

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

959

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

96

ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

960

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

965

dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &phyd32clk,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

968

if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

969

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

985

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

990

link_hwss->setup_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

992

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

994

dc->hwss.program_dmdata_engine(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

997

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

999

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

100

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

107

struct pipe_ctx *old_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

108

struct pipe_ctx *new_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

34

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

38

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

41

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

44

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

45

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

48

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

51

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

53

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

62

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

67

const struct pipe_ctx *top_pipe_to_program);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

81

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

84

struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

86

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

91

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

98

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

101

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

105

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

110

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

116

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

148

const struct pipe_ctx *top_pipe_to_program;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

224

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

225

void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

236

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

241

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

246

struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

247

void (*update_pending_status)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

249

void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

253

struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

256

void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

258

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

261

void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

263

int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

266

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

270

int group_size, struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

274

struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

277

struct pipe_ctx *grouped_pipes[]);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

279

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

280

void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

282

void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

287

void (*enable_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

288

void (*disable_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

289

void (*blank_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

290

void (*unblank_stream)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

299

void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

301

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

304

void (*update_info_frame)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

305

void (*set_dmdata_attributes)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

306

void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

307

bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

310

void (*set_cursor_position)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

311

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

312

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

315

void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

316

void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

319

void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

35

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

355

void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

356

void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

359

void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

369

bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

372

void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

374

void (*set_pipe)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

412

struct pipe_ctx *top_pipe_to_program,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

422

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

433

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

437

struct pipe_ctx *phantom_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

438

void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

454

const struct pipe_ctx *top_pipe_to_program);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

462

void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

466

void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

469

struct pipe_ctx *old_pipe,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

470

struct pipe_ctx *new_pipe);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

472

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

475

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

478

struct pipe_ctx *opp_head);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

497

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

500

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

504

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

507

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

513

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

516

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

521

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

525

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

529

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

534

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

540

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

543

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

556

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

60

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

65

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

71

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

77

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

82

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

87

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

91

struct pipe_ctx *pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

101

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

107

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

108

bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

115

void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

142

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

147

void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

150

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

154

bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

156

bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

158

bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

161

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

163

void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

168

unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

175

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

178

bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

180

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

183

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

186

void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

187

void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

188

void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

55

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

76

void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

77

void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

82

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

83

void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

85

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

88

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

98

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

139

struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)(

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

143

const struct pipe_ctx *opp_head_pipe);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

145

struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

149

const struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

152

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

216

void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

222

unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

231

struct pipe_ctx *pipes,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

475

struct pipe_ctx *top_pipe;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

476

struct pipe_ctx *bottom_pipe;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

477

struct pipe_ctx *next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

478

struct pipe_ctx *prev_odm_pipe;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

522

struct pipe_ctx pipe_ctx[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

536

struct pipe_ctx temp_pipe;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

35

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

42

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

38

struct pipe_ctx;

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

49

void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

52

void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

77

void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

78

void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

79

void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

83

void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

85

void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

86

void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

157

void (*set_dpms_on)(struct dc_state *state, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

158

void (*set_dpms_off)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

164

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

166

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

167

void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

168

bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

169

bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

199

bool (*dp_is_128b_132b_signal)(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

115

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

117

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

123

void resource_build_info_frame(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

150

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

163

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

286

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

314

struct pipe_ctx *otg_master_pipe,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

378

struct pipe_ctx *resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/inc/resource.h

388

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

390

struct pipe_ctx *opp_heads[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

398

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

400

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

409

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

416

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

423

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

429

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

436

int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

443

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

450

int resource_get_odm_slice_count(const struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

453

int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

456

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

459

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

462

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

476

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

477

const struct pipe_ctx *otg_master_b);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

492

const struct pipe_ctx *cur_otg_master);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

504

const struct pipe_ctx *cur_opp_head);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

565

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

sys/dev/pci/drm/amd/display/dc/inc/resource.h

568

const struct pipe_ctx *primary_pipe);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

588

struct pipe_ctx *pipe_ctx_old,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

589

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

627

struct pipe_ctx *pri_pipe,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

628

struct pipe_ctx *sec_pipe,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

638

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

644

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

654

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

219

tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

195

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

196

struct pipe_ctx *pipe_ctx = &pipes[0];

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

268

for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

481

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

486

enum dc_color_depth color_depth = pipe_ctx->

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

489

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

490

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

496

pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

497

controller_test_pattern = pipe_ctx->stream_res.test_pattern_params.test_pattern;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

507

pipe_ctx->stream->bit_depth_params = params;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

508

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

510

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

516

controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

523

odm_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

545

resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

546

pipe_ctx->stream->bit_depth_params = params;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

547

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

549

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

555

odm_pipe = pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

655

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

656

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

671

pipe_ctx = &pipes[i];

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

676

if (pipe_ctx == NULL)

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

685

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

686

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

69

struct pipe_ctx *pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

692

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

717

dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

729

link->dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

732

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

876

if (!pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

879

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

880

if (should_use_dmub_lock(pipe_ctx->stream->link)) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

885

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

892

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

893

pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

896

pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

898

link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

899

pipe_ctx->stream->output_color_space = color_space;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

900

link_hwss->setup_stream_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

902

if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

904

pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

906

pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

909

pipe_ctx->stream->vsc_infopacket.sb[16] &= 0xf0;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

911

pipe_ctx->stream->vsc_infopacket.sb[16] |= 1;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

913

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

914

link->dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

918

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

919

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

920

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

922

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

924

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

927

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

928

if (should_use_dmub_lock(pipe_ctx->stream->link)) {

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

933

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

940

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

941

pipe_ctx->stream_res.tg);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

958

struct pipe_ctx *pipe;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

973

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

100

pipe_ctx->stream->signal, false);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

103

pipe_ctx->stream_res.stream_enc->id,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

105

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

106

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

107

pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

112

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

114

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

115

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

121

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

136

pipe_ctx->stream_res.audio != NULL);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

249

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

252

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

253

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

254

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

256

&pipe_ctx->stream->audio_info);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

258

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

259

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

261

&pipe_ctx->stream->audio_info,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

265

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

267

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

268

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

269

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

271

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

272

pipe_ctx->stream_res.stream_enc, false);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

274

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

275

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

276

pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

280

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

282

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

283

pipe_ctx->stream_res.stream_enc, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

285

if (pipe_ctx->stream_res.audio) {

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

286

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

287

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

288

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

290

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

291

pipe_ctx->stream_res.stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

294

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

295

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

296

pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

39

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

42

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

49

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

51

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

52

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

55

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

62

pipe_ctx->stream_res.stream_enc->id, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

63

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

64

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

68

pipe_ctx->stream->signal, true);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

74

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

79

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

81

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

82

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

84

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

85

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

35

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

37

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

38

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

39

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

55

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

57

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

58

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

178

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

181

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

182

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

184

&pipe_ctx->stream->audio_info);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

187

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

189

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

190

pipe_ctx->stream_res.hpo_dp_stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

193

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

195

if (pipe_ctx->stream_res.audio)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

196

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

197

pipe_ctx->stream_res.hpo_dp_stream_enc);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

33

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

37

pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

39

pipe_ctx->link_res.hpo_dp_link_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

46

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

51

pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

52

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

56

pipe_ctx->stream->link, link_settings);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

74

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

76

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

77

struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

83

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

85

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

90

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

92

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

93

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

31

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

33

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

36

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

39

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

40

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

41

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

53

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

55

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

56

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1002

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1003

pipe_ctx->stream_res.stream_enc, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1010

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1012

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1015

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1022

link_set_dsc_on_stream(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1026

dp_set_dsc_on_rx(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1027

link_set_dsc_on_stream(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1034

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1036

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1038

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1043

link_set_dsc_on_stream(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1044

link_set_dsc_pps_packet(pipe_ctx, true, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1048

static void enable_stream_features(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1050

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1052

if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1157

static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1162

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1167

kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1330

static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1332

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1338

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1351

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1353

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1368

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1369

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1375

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1380

remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1381

pipe_ctx->stream_res.hpo_dp_stream_enc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1411

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1429

static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1431

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1439

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1455

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1456

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1462

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1494

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

151

struct pipe_ctx *pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1513

pbn = get_pbn_from_timing(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1519

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1521

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1656

static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1659

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1664

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1674

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1677

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1691

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1695

proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1708

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1725

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1728

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1739

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1741

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1748

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1757

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1759

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1777

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1778

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1784

pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1816

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1827

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1829

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1837

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1849

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1850

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1883

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1904

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1906

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

196

const struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1963

static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1965

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1973

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1974

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1985

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1986

unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1990

eng_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1992

if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1993

write_i2c_retimer_setting(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1996

write_i2c_default_retimer_setting(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2001

write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2005

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2021

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2022

link_hwss->setup_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2026

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2027

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2028

pipe_ctx->clock_source->id,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2032

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2037

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2039

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2044

&pipe_ctx->link_config.dp_link_settings;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2079

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2083

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2088

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

209

struct pipe_ctx *pipes[MAX_PIPES])

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2098

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

212

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2126

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2127

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2140

dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

216

pipe = &state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2161

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2163

return enable_link_dp(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2166

static void enable_link_lvds(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2168

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2179

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2180

pipe_ctx->clock_source->id,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2187

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2189

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2211

return enable_link_dp(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2214

static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2216

struct dc_link *link = pipe_ctx->stream->link;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2219

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2221

pipe_ctx->clock_source->id,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2222

&pipe_ctx->link_config.dp_link_settings);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2228

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2231

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2241

disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2243

switch (pipe_ctx->stream->signal) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2245

status = enable_link_dp(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2248

status = enable_link_edp(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

225

static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2251

status = enable_link_dp_mst(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2257

enable_link_hdmi(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2261

enable_link_lvds(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2265

status = enable_link_virtual(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2272

pipe_ctx->stream->link->link_status.link_active = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

232

pipe_ctx->stream->ctx->dc_bios->integrated_info;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2346

void link_set_dpms_off(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2348

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2349

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2351

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2354

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2356

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2358

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2359

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2360

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2363

if (pipe_ctx->stream->sink) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2364

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2365

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2367

pipe_ctx->stream->sink->edid_caps.display_name,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2368

pipe_ctx->stream->signal, link->link_index, link->sink_count);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2372

if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2373

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2374

set_avmute(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2377

dc->hwss.disable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2379

update_psp_stream_config(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2380

dc->hwss.blank_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2382

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2383

deallocate_usb4_bandwidth(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2385

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2386

deallocate_mst_payload(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2387

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2388

dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2389

update_sst_payload(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2391

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2393

enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2404

if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2405

write_i2c_retimer_setting(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2408

write_i2c_default_retimer_setting(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2412

write_i2c_redriver_setting(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2416

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2417

!dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2426

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2427

dc->hwss.disable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2429

dc->hwss.disable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2430

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2432

edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2434

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2435

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2436

link_set_dsc_enable(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2438

if (dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2439

if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2440

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2449

enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2457

struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2459

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2460

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2463

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2465

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2466

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2468

pipe_ctx->stream->apply_edp_fast_boot_optimization;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2470

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2472

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2474

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2475

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2476

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2479

if (pipe_ctx->stream->sink) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2480

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2481

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2483

pipe_ctx->stream->sink->edid_caps.display_name,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2484

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2494

if (!dc_is_virtual_signal(pipe_ctx->stream->signal)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2495

&& !dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2499

pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2502

pipe_ctx->stream->link->link_state_valid = true;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2504

if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2505

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2509

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2512

link_hwss->setup_stream_attribute(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2514

pipe_ctx->stream->apply_edp_fast_boot_optimization = false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2520

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2521

dc->hwss.update_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2523

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2527

if (pipe_ctx->stream->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2528

pipe_ctx->stream->dpms_off = false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2531

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2532

enable_stream_features(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2533

dc->hwss.enable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2536

update_psp_stream_config(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2541

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2543

!pipe_ctx->stream->timing.flags.DSC &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2544

!pipe_ctx->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2545

pipe_ctx->stream->dpms_off = false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2546

update_psp_stream_config(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2558

if (pipe_ctx->stream->dpms_off)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2576

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2577

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2578

dc_is_virtual_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2579

link_set_dsc_enable(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2582

status = enable_link(state, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2586

pipe_ctx->stream->link->link_index,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2595

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2597

disable_link(stream->link, &pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2598

pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2605

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2606

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2614

if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2615

dp_is_128b_132b_signal(pipe_ctx))) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2620

pipe_ctx->stream->signal);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2624

dc->hwss.enable_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2627

if (pipe_ctx->stream->timing.flags.DSC) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2628

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2629

dc_is_virtual_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2630

dp_set_dsc_on_rx(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2631

link_set_dsc_pps_packet(pipe_ctx, true, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2635

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2636

dp_set_hblank_reduction_on_rx(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2638

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2639

allocate_usb4_bandwidth(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2641

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2642

allocate_mst_payload(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2643

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2644

dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2645

update_sst_payload(pipe_ctx, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2652

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2656

dc->hwss.unblank_stream(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2657

&pipe_ctx->stream->link->cur_link_settings);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2662

if (dc_is_dp_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2663

enable_stream_features(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2664

update_psp_stream_config(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2666

dc->hwss.enable_audio_stream(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2668

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2669

set_avmute(pipe_ctx, false);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

322

static bool write_i2c(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

333

cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

341

if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

342

pipe_ctx->stream->link, &cmd))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

349

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

361

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

373

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

395

pipe_ctx->stream->link->ddc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

404

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

423

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

445

pipe_ctx->stream->link->ddc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

454

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

472

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

483

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

494

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

511

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

518

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

526

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

537

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

548

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

559

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

570

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

581

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

596

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

607

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

618

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

634

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

640

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

650

i2c_success = write_i2c(pipe_ctx, slave_address,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

662

static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

664

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

665

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

668

dp_get_panel_mode(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

672

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

673

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

679

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

682

config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

685

config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

686

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

688

pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

691

config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

695

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

696

config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

699

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

700

config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

707

pipe_ctx->stream->link->dc, link_enc->transmitter);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

708

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

714

config.mst_enabled = (pipe_ctx->stream->signal ==

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

716

config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

717

config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

722

config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

727

static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

729

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

731

if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

734

dc->hwss.set_avmute(pipe_ctx, enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

772

static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

774

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

775

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

785

static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

787

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

788

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

802

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

807

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

808

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

809

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

810

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

826

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

835

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

840

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

848

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

849

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

863

if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

864

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

866

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

867

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

876

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

878

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

884

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

885

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

890

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

891

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

892

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

897

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

898

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

899

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

901

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

902

pipe_ctx->stream_res.stream_enc, false, NULL, true);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

907

for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

946

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

948

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

949

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

951

if (!pipe_ctx->stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

971

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

977

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

978

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

979

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

980

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

985

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

986

pipe_ctx->stream_res.stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

995

if (dp_is_128b_132b_signal(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

996

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

997

pipe_ctx->stream_res.hpo_dp_stream_enc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

32

struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

33

void link_set_dpms_off(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

42

struct pipe_ctx *pipes[MAX_PIPES]);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

43

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

44

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

45

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

50

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

51

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

52

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

29

static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

31

struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc;

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

32

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

33

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/link/link_hwss_hpo_frl.c

37

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

36

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

377

if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

378

dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

376

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

379

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

380

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

381

pipe_ctx->link_res.hpo_dp_link_enc &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

382

dc_is_dp_signal(pipe_ctx->stream->signal));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h

68

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

267

struct pipe_ctx *pipes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1622

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1628

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1634

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1648

link_hwss->setup_stream_encoder(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1661

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1663

pipe_ctx->clock_source->id,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1672

edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1677

dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1683

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1689

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1701

&pipe_ctx->link_res,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1755

dp_disable_link_phy(link, &pipe_ctx->link_res, signal);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

35

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1031

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1037

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1188

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1189

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1192

abm = pipe_ctx->stream_res.abm;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1275

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1278

struct link_resource *link_res = &pipe_ctx->link_res;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1279

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

531

static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

535

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

538

if (dc->current_state->res_ctx.pipe_ctx[i].stream) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

539

if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

540

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

546

return pipe_ctx;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

560

struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

565

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

569

if (pipe_ctx->plane_state == NULL)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

578

pipe_ctx,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

800

if (dc->current_state->res_ctx.pipe_ctx[i].stream

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

807

pipe_ctx[i].stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

79

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

405

if (pipe_ctx) {

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

406

if (pipe_ctx->stream)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

828

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

830

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

833

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

835

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

851

stream = context->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1121

static struct pipe_ctx *dce110_acquire_underlay(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1125

const struct pipe_ctx *opp_head_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1132

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1134

if (res_ctx->pipe_ctx[underlay_idx].stream)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1137

pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1138

pipe_ctx->plane_res.mi = pool->mis[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1140

pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1141

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1142

pipe_ctx->pipe_idx = underlay_idx;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1144

pipe_ctx->stream = stream;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1146

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1152

pipe_ctx->stream_res.tg->inst,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1160

pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1167

pipe_ctx->stream->signal,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1170

pipe_ctx->stream_res.tg->funcs->enable_advanced_request(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1171

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1175

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1183

pipe_ctx->stream_res.tg->funcs->set_blank_color(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1184

pipe_ctx->stream_res.tg,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1188

return pipe_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

883

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

886

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

894

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

895

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

917

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

919

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

920

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

921

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

922

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

923

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

924

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

925

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

926

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

929

static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

931

if (pipe_ctx->pipe_idx != underlay_idx)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

933

if (!pipe_ctx->plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

935

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

945

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

947

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

950

if (!is_surface_pixel_format_supported(pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

954

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

958

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

978

context->res_ctx.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.h

41

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

874

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

876

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

879

dce110_resource_build_pipe_hw_param(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

881

resource_build_info_frame(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

901

context->res_ctx.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

965

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

968

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

971

if (dc_is_dp_signal(pipe_ctx->stream->signal)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

972

|| dc_is_virtual_signal(pipe_ctx->stream->signal))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

973

pipe_ctx->clock_source =

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

977

pipe_ctx->clock_source = find_matching_pll(

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

982

if (pipe_ctx->clock_source == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

988

pipe_ctx->clock_source);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1001

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1002

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1029

static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1032

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1034

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1035

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1036

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1037

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1039

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1041

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1042

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1043

build_clamping_params(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1051

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1053

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1056

build_pipe_hw_param(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1079

static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1083

const struct pipe_ctx *opp_head_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1086

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1087

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1266

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1268

return pipe_ctx->pipe_dlg_param.vstartup_start;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

995

const struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

998

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

54

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1216

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1219

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1220

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1223

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1224

struct dc *dc = pipe_ctx->stream->ctx->dc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1227

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1237

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1238

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1254

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1257

if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1264

if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1265

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1267

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1282

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1284

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1285

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1286

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1287

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1288

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1291

static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1293

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1296

pool->funcs->build_pipe_pix_clk_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1298

dcn20_build_pipe_pix_clk_params(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1301

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1303

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1304

&pipe_ctx->stream->bit_depth_params);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1305

build_clamping_params(pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1313

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1315

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1319

status = build_pipe_hw_param(pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1332

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1385

struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1387

if (pipe_ctx->top_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1390

if (pipe_ctx->stream != dc_stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1393

if (pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1396

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1399

if (!pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1414

struct pipe_ctx *pipe_ctx = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1418

if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1419

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1421

if (pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1422

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1426

if (!pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1481

struct pipe_ctx *prev_odm_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1482

struct pipe_ctx *next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1536

struct pipe_ctx *primary_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1537

struct pipe_ctx *secondary_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1540

struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1607

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1611

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1617

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1618

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1649

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1650

struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1652

struct pipe_ctx *odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1655

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1659

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1668

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1672

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1678

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1681

const struct pipe_ctx *primary_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1683

struct pipe_ctx *secondary_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1695

if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1696

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1697

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1698

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1703

dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1704

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1705

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1706

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1719

if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1720

&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1723

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1724

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1744

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1745

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1764

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1765

struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1772

struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1793

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1794

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1836

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1860

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1878

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1897

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1902

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2046

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2047

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2145

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2149

const struct pipe_ctx *opp_head)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2152

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2153

struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2211

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

139

struct pipe_ctx *primary_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

140

struct pipe_ctx *secondary_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

144

struct pipe_ctx *prev_odm_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

145

struct pipe_ctx *next_odm_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

150

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

153

const struct pipe_ctx *primary_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

168

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

61

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

65

const struct pipe_ctx *opp_head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

67

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1003

const struct pipe_ctx *opp_head_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1006

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1007

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

999

static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

822

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

823

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

846

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

847

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1332

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1388

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1392

struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1409

wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1523

struct pipe_ctx *pri_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1524

struct pipe_ctx *sec_pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1582

static struct pipe_ctx *dcn30_find_split_pipe(

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1587

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1590

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1591

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1597

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1598

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1599

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1600

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1614

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1615

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1701

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1702

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1722

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1747

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1748

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1767

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1768

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1769

struct pipe_ctx *hsplit_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1810

struct pipe_ctx *pipe_4to1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1853

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1648

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1658

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1660

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2242

struct pipe_ctx *pipes,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

72

struct pipe_ctx *pipes,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1646

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1650

if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1651

res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1652

(res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1653

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1654

res_ctx->pipe_ctx[i].plane_state->src_rect.height

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1655

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1658

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1671

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1683

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1685

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1747

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1617

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1627

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1629

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1647

struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1691

struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1730

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1873

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1905

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1906

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1920

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1922

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1941

odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2631

const struct pipe_ctx *new_opp_head)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2633

const struct pipe_ctx *cur_opp_head;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2636

cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2664

static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2667

const struct pipe_ctx *primary_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2670

struct pipe_ctx *secondary_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2671

struct pipe_ctx *next_odm_mpo_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2673

struct pipe_ctx *old_primary_pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2696

old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2702

if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2704

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2715

if ((res_ctx->pipe_ctx[i].stream == NULL) &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2717

secondary_pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2726

static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2730

const struct pipe_ctx *head_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2733

struct pipe_ctx *idle_pipe, *pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2749

pipe = &old_ctx->pipe_ctx[head_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2750

if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2751

idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2775

const struct pipe_ctx *new_otg_master)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2777

const struct pipe_ctx *cur_otg_master;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2780

cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2798

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2802

const struct pipe_ctx *opp_head_pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2806

struct pipe_ctx *free_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2816

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2835

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2839

const struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2844

struct pipe_ctx *free_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2847

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

118

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

137

bool dcn32_is_center_timing(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

138

bool dcn32_is_psr_capable(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

144

const struct pipe_ctx *new_opp_head);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

146

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

150

const struct pipe_ctx *opp_head_pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

152

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

156

const struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

159

struct pipe_ctx *pipe,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

171

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

179

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

114

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

136

struct pipe_ctx *top_pipe = pipe->top_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

137

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

159

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

176

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

201

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

212

bool dcn32_is_center_timing(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

233

bool dcn32_is_psr_capable(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

260

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

262

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

265

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

277

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

278

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

340

if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

348

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

350

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

351

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

359

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

360

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

370

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

386

struct pipe_ctx *pipe = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

391

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

394

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

41

struct pipe_ctx *pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

44

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

48

switch (pipe_ctx->stream->cursor_attributes.color_format) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

591

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

618

static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

656

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

67

if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

717

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

755

struct pipe_ctx *pipe = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

760

if (!res_ctx->pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

762

pipe = &res_ctx->pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1693

static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1695

const struct dc_stream_state *stream = pipe_ctx->stream;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1697

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1698

struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1702

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1703

pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1705

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1710

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1711

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1733

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1734

pipe_ctx->clock_source,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1735

&pipe_ctx->stream_res.pix_clk_params,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1736

&pipe_ctx->pll_settings);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1772

static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1774

return pipe_ctx->global_sync.dcn4x.vstartup_lines;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.c

28

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.c

32

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.c

36

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.h

30

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.h

31

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_hwss.h

32

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);