Symbol: mul_u32_u32
sys/dev/pci/drm/apple/parser.c
422
u64 clock = mul_u32_u32(pixels, vert->precise_sync_rate);
sys/dev/pci/drm/display/drm_dp_helper.c
4593
return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
sys/dev/pci/drm/display/drm_dp_helper.c
4652
return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
3610
ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4819
return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
sys/dev/pci/drm/drm_modes.c
1307
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
sys/dev/pci/drm/drm_rect.c
65
tmp = mul_u32_u32(src, dst - *clip);
sys/dev/pci/drm/i915/display/i9xx_wm.c
490
ret = mul_u32_u32(pixel_rate, cpp * latency);
sys/dev/pci/drm/i915/display/intel_audio.c
485
hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
sys/dev/pci/drm/i915/display/intel_audio.c
486
mul_u32_u32(link_clk, cdclk));
sys/dev/pci/drm/i915/display/intel_audio.c
488
tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
sys/dev/pci/drm/i915/display/intel_audio.c
489
mul_u32_u32(link_clk * lanes * 16, fec_coeff));
sys/dev/pci/drm/i915/display/intel_audio.c
490
tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
sys/dev/pci/drm/i915/display/intel_audio.c
491
mul_u32_u32(64 * pixel_clk, 1000000));
sys/dev/pci/drm/i915/display/intel_backlight.c
56
target_val = mul_u32_u32(source_val - source_min,
sys/dev/pci/drm/i915/display/intel_bw.c
879
return DIV_ROUND_UP_ULL(mul_u32_u32(data_rate, 10), 512);
sys/dev/pci/drm/i915/display/intel_color.c
207
result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
sys/dev/pci/drm/i915/display/intel_color.c
812
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16) - 1),
sys/dev/pci/drm/i915/display/intel_crtc.c
488
return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock),
sys/dev/pci/drm/i915/display/intel_crtc.c
499
return DIV_ROUND_UP_ULL(mul_u32_u32(scanlines, adjusted_mode->crtc_htotal * 1000),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2428
vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2754
tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
sys/dev/pci/drm/i915/display/intel_display.c
2509
*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
sys/dev/pci/drm/i915/display/intel_display.c
4053
return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
sys/dev/pci/drm/i915/display/intel_dp.c
456
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
sys/dev/pci/drm/i915/display/intel_dp.c
818
return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
sys/dev/pci/drm/i915/display/intel_dp_mst.c
172
return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
174
mul_u32_u32(adjusted_mode->crtc_clock, 1030000));
sys/dev/pci/drm/i915/display/intel_dp_mst.c
220
m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
521
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
sys/dev/pci/drm/i915/display/intel_dpll.c
368
DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
sys/dev/pci/drm/i915/display/intel_dpll.c
950
m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3100
tmp = mul_u32_u32(dco_khz, 47 * 32);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3104
tmp = mul_u32_u32(dco_khz, 1000);
sys/dev/pci/drm/i915/display/intel_fb.c
1174
if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),
sys/dev/pci/drm/i915/display/intel_fb.c
1792
if (mul_u32_u32(max_size, tile_size) > obj->size) {
sys/dev/pci/drm/i915/display/intel_fb.c
1795
mul_u32_u32(max_size, tile_size), obj->size);
sys/dev/pci/drm/i915/display/intel_fixed.h
122
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
79
tmp = mul_u32_u32(val, mul.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
91
tmp = mul_u32_u32(val.val, mul.val);
sys/dev/pci/drm/i915/display/intel_plane.c
217
return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1944
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
sys/dev/pci/drm/i915/display/intel_sprite.c
592
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),
sys/dev/pci/drm/i915/display/intel_sprite.c
955
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
sys/dev/pci/drm/i915/display/intel_vblank.c
171
return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
sys/dev/pci/drm/i915/display/intel_vrr.c
220
crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
sys/dev/pci/drm/i915/display/intel_vrr.c
222
vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
sys/dev/pci/drm/i915/display/intel_vrr.c
224
adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
sys/dev/pci/drm/i915/display/skl_watermark.c
2201
hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
sys/dev/pci/drm/i915/display/skl_watermark.c
2202
vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
sys/dev/pci/drm/i915/display/skl_watermark.c
2228
u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
sys/dev/pci/drm/i915/display/skl_watermark.c
2229
u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
sys/dev/pci/drm/i915/gem/i915_gem_create.c
203
args->size = mul_u32_u32(args->pitch, args->height);
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
186
div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX),
sys/dev/pci/drm/i915/gt/intel_migrate.c
283
return upper_32_bits(mul_u32_u32(get_random_u32(), max));
sys/dev/pci/drm/i915/gt/intel_region_lmem.c
290
mul_u32_u32(i915->params.lmem_size, SZ_1M));
sys/dev/pci/drm/i915/gt/selftest_migrate.c
878
div64_u64(mul_u32_u32(4 * sz,
sys/dev/pci/drm/i915/gt/selftest_migrate.c
961
div64_u64(mul_u32_u32(4 * sz,
sys/dev/pci/drm/i915/gvt/handlers.c
604
clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
sys/dev/pci/drm/i915/gvt/handlers.c
698
pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
sys/dev/pci/drm/i915/gvt/handlers.c
702
new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
sys/dev/pci/drm/i915/i915_pmu.c
215
pmu->sample[gt_id][sample].cur += mul_u32_u32(val, mul);
sys/dev/pci/drm/i915/selftests/i915_random.h
49
return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));
sys/dev/pci/drm/i915/selftests/i915_request.c
1943
sum = mul_u32_u32(a[2], 2);
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1282
div64_u64(mul_u32_u32(4 * size,
sys/dev/pci/drm/include/drm/drm_color_mgmt.h
46
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(user_input, (1 << bit_precision) - 1),
sys/dev/pci/drm/include/linux/math64.h
84
return (mul_u32_u32(lo, y) >> shift) +
sys/dev/pci/drm/include/linux/math64.h
85
(mul_u32_u32(hi, y) << (32 - shift));