intel_engine_mask_t
intel_engine_mask_t prev_mask;
intel_engine_mask_t current_mask = 0;
intel_engine_mask_t engine_mask;
static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
intel_engine_mask_t tmp, mask = engine->mask;
intel_engine_mask_t tmp, mask = engine->mask;
intel_engine_mask_t mask;
intel_engine_mask_t logical_mask;
intel_engine_mask_t saturated; /* submitting semaphores too late? */
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve)
intel_engine_mask_t mask;
intel_engine_mask_t mask;
intel_engine_mask_t engine_mask)
intel_engine_mask_t engine_mask);
intel_engine_mask_t cslices;
intel_engine_mask_t engine_mask;
intel_engine_mask_t engine_mask;
static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
intel_engine_mask_t stalled_mask,
intel_engine_mask_t awake;
intel_engine_mask_t engine_mask,
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask,
static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask,
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask,
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask,
intel_engine_mask_t tmp;
intel_engine_mask_t mask,
intel_engine_mask_t engine_mask,
static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
static intel_engine_mask_t
wa_14015076503_start(struct intel_gt *gt, intel_engine_mask_t engine_mask, bool first)
wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t engine_mask)
static int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
intel_engine_mask_t reset_mask;
static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
intel_engine_mask_t awake = 0;
static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
intel_engine_mask_t awake;
intel_engine_mask_t engine_mask,
intel_engine_mask_t stalled_mask,
intel_engine_mask_t awake, tmp;
static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask)
intel_engine_mask_t mask,
intel_engine_mask_t awake;
intel_engine_mask_t mask;
intel_engine_mask_t reset_fail_mask;
void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled);
intel_klog_error_capture(guc_to_gt(guc), (intel_engine_mask_t)~0U);
intel_engine_mask_t tmp, mask = ve->mask;
static void __guc_reset_context(struct intel_context *ce, intel_engine_mask_t stalled)
void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)
intel_engine_mask_t tmp, mask = ce->engine->mask;
intel_engine_mask_t tmp, mask = ce->engine->mask;
intel_engine_mask_t tmp, mask = ce->engine->mask;
intel_engine_mask_t tmp, mask = ce->engine->mask;
intel_engine_mask_t tmp, mask = b->engine_mask;
intel_engine_mask_t tmp, mask = b->engine_mask;
intel_engine_mask_t tmp, mask = engine->mask;
intel_engine_mask_t engine_mask;
intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;
intel_engine_mask_t reset_fail_mask;
intel_engine_mask_t tmp, mask = ve->mask;
intel_engine_mask_t mask = gt->info.engine_mask;
void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled);
intel_engine_mask_t rings;
intel_engine_mask_t engine_mask)
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask)
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask)
int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
intel_engine_mask_t engine_mask);
intel_engine_mask_t engine_mask = 0;
intel_engine_mask_t engine_mask)
intel_engine_mask_t tmp;
intel_engine_mask_t engine_mask)
intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask);
intel_engine_mask_t engine_mask,
intel_engine_mask_t engine_mask);
intel_engine_mask_t engine_mask)
intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
intel_engine_mask_t tmp, mask = engine->mask;
intel_engine_mask_t engine_mask,
__i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
intel_engine_mask_t engine_mask, u32 dump_flags)
intel_engine_mask_t engine_mask)
intel_engine_mask_t engine_mask);
intel_engine_mask_t engine_mask)
intel_engine_mask_t engine_mask, u32 dump_flags);
i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
intel_engine_mask_t tmp;
static intel_engine_mask_t
const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
intel_engine_mask_t execution_mask;
intel_engine_mask_t semaphores;
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
intel_engine_mask_t emask;