sys/dev/pci/drm/i915/display/g4x_dp.c

1193

return intel_de_read(display, SDEISR) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1216

return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

1224

return intel_de_read(display, DEISR) & bit;

sys/dev/pci/drm/i915/display/g4x_dp.c

125

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

sys/dev/pci/drm/i915/display/g4x_dp.c

1268

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

175

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

sys/dev/pci/drm/i915/display/g4x_dp.c

186

bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;

sys/dev/pci/drm/i915/display/g4x_dp.c

259

u32 val = intel_de_read(display, TRANS_DP_CTL(p));

sys/dev/pci/drm/i915/display/g4x_dp.c

283

val = intel_de_read(display, dp_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

350

tmp = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_dp.c

355

u32 trans_dp = intel_de_read(display,

sys/dev/pci/drm/i915/display/g4x_dp.c

395

if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

sys/dev/pci/drm/i915/display/g4x_dp.c

421

(intel_de_read(display, intel_dp->output_reg) &

sys/dev/pci/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

160

tmp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

224

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

283

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

331

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

387

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

sys/dev/pci/drm/i915/display/hsw_ips.c

286

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

sys/dev/pci/drm/i915/display/hsw_ips.c

356

if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

22

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

23

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

26

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

29

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

32

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

33

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

36

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

sys/dev/pci/drm/i915/display/i9xx_display_sr.c

74

display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1191

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1212

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1214

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1217

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1220

offset = intel_de_read(display,

sys/dev/pci/drm/i915/display/i9xx_plane.c

1222

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

sys/dev/pci/drm/i915/display/i9xx_plane.c

1225

base = intel_de_read(display, DSPADDR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1231

val = intel_de_read(display, PIPESRC(display, pipe));

sys/dev/pci/drm/i915/display/i9xx_plane.c

1235

val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

574

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

575

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

576

error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

586

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

587

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

597

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

598

error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

741

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_wm.c

166

was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

170

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

174

val = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

183

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

194

was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

2382

fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;

sys/dev/pci/drm/i915/display/i9xx_wm.c

294

dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

295

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

300

dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

301

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

306

dsparb2 = intel_de_read(display, DSPARB2);

sys/dev/pci/drm/i915/display/i9xx_wm.c

307

dsparb3 = intel_de_read(display, DSPARB3);

sys/dev/pci/drm/i915/display/i9xx_wm.c

325

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

341

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3504

hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

358

u32 dsparb = intel_de_read(display, DSPARB(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3670

tmp = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3676

tmp = intel_de_read(display, DSPFW2(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3684

tmp = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3698

tmp = intel_de_read(display, VLV_DDL(pipe));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3710

tmp = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3716

tmp = intel_de_read(display, DSPFW2(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3721

tmp = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

3725

tmp = intel_de_read(display, DSPFW7_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3729

tmp = intel_de_read(display, DSPFW8_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3733

tmp = intel_de_read(display, DSPFW9_CHV);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3737

tmp = intel_de_read(display, DSPHOWM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3749

tmp = intel_de_read(display, DSPFW7);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3753

tmp = intel_de_read(display, DSPHOWM);

sys/dev/pci/drm/i915/display/i9xx_wm.c

3774

wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

3918

wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/i9xx_wm.c

4084

hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4085

hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4086

hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4088

hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4090

hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4091

hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);

sys/dev/pci/drm/i915/display/i9xx_wm.c

4095

hw->partitioning = (intel_de_read(display, WM_MISC) &

sys/dev/pci/drm/i915/display/i9xx_wm.c

4099

hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &

sys/dev/pci/drm/i915/display/i9xx_wm.c

4104

!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);

sys/dev/pci/drm/i915/display/i9xx_wm.c

679

reg = intel_de_read(display, DSPFW1(display));

sys/dev/pci/drm/i915/display/i9xx_wm.c

706

reg = intel_de_read(display, DSPFW3(display));

sys/dev/pci/drm/i915/display/icl_dsi.c

1120

tmp = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/icl_dsi.c

1182

tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1356

tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1552

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

1607

!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

sys/dev/pci/drm/i915/display/icl_dsi.c

1740

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

1760

tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

202

tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

266

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

276

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

314

dss_ctl1 = intel_de_read(display, dss_ctl1_reg);

sys/dev/pci/drm/i915/display/icl_dsi.c

461

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

472

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/icl_dsi.c

492

tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

509

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

520

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/icl_dsi.c

63

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)

sys/dev/pci/drm/i915/display/icl_dsi.c

630

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

646

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

662

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

683

val = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/icl_dsi.c

70

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)

sys/dev/pci/drm/i915/display/icl_dsi.c

714

tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/icl_dsi.c

823

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_alpm.c

513

alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_audio.c

1343

aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);

sys/dev/pci/drm/i915/display/intel_audio.c

260

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

sys/dev/pci/drm/i915/display/intel_audio.c

273

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

sys/dev/pci/drm/i915/display/intel_audio.c

283

eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);

sys/dev/pci/drm/i915/display/intel_audio.c

324

(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);

sys/dev/pci/drm/i915/display/intel_audio.c

361

tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_audio.c

384

tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_audio.c

525

val = intel_de_read(display, AUD_CONFIG_BE);

sys/dev/pci/drm/i915/display/intel_backlight.c

1163

if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {

sys/dev/pci/drm/i915/display/intel_backlight.c

1256

alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;

sys/dev/pci/drm/i915/display/intel_backlight.c

1258

alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;

sys/dev/pci/drm/i915/display/intel_backlight.c

1261

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

1264

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1267

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1311

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

1314

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1325

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1342

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1384

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

1388

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1420

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1423

ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

1452

pwm_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_backlight.c

1457

val = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

1464

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

1506

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

sys/dev/pci/drm/i915/display/intel_backlight.c

1531

pwm_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_backlight.c

1536

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

154

return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

161

return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

170

val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

192

return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

200

return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

222

val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

232

tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

262

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

sys/dev/pci/drm/i915/display/intel_backlight.c

273

tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/pci/drm/i915/display/intel_backlight.c

365

tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

493

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

539

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

548

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

sys/dev/pci/drm/i915/display/intel_backlight.c

588

ctl = intel_de_read(display, BLC_PWM_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

630

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

sys/dev/pci/drm/i915/display/intel_backlight.c

667

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

sys/dev/pci/drm/i915/display/intel_backlight.c

701

val = intel_de_read(display, UTIL_PIN_CTL);

sys/dev/pci/drm/i915/display/intel_backlight.c

717

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_backlight.c

750

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

sys/dev/pci/drm/i915/display/intel_cdclk.c

1025

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1201

cdclk_ctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1246

if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)

sys/dev/pci/drm/i915/display/intel_cdclk.c

1263

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1682

u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1712

val = intel_de_read(display, BXT_DE_PLL_ENABLE);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1730

ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1756

divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

1777

squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

1794

cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

sys/dev/pci/drm/i915/display/intel_cdclk.c

2278

cdctl = intel_de_read(display, CDCLK_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

3447

u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

sys/dev/pci/drm/i915/display/intel_cdclk.c

3475

if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

3539

if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

3565

return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;

sys/dev/pci/drm/i915/display/intel_cdclk.c

374

tmp = intel_de_read(display, display->platform.pineview ||

sys/dev/pci/drm/i915/display/intel_cdclk.c

549

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

554

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

666

intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);

sys/dev/pci/drm/i915/display/intel_cdclk.c

839

u32 lcpll = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

844

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

sys/dev/pci/drm/i915/display/intel_cdclk.c

888

(intel_de_read(display, LCPLL_CTL) &

sys/dev/pci/drm/i915/display/intel_cdclk.c

980

val = intel_de_read(display, LCPLL1_CTL);

sys/dev/pci/drm/i915/display/intel_cdclk.c

987

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_cmtg.c

107

val = intel_de_read(display, TRANS_CMTG_CTL_A);

sys/dev/pci/drm/i915/display/intel_cmtg.c

111

val = intel_de_read(display, TRANS_CMTG_CTL_B);

sys/dev/pci/drm/i915/display/intel_cmtg.c

97

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));

sys/dev/pci/drm/i915/display/intel_color.c

1052

return intel_de_read(display, GAMMA_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1059

return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

1070

tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/intel_color.c

1098

tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_color.c

3469

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

156

return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;

sys/dev/pci/drm/i915/display/intel_combo_phy.c

158

return !(intel_de_read(display, ICL_PHY_MISC(phy)) &

sys/dev/pci/drm/i915/display/intel_combo_phy.c

160

(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);

sys/dev/pci/drm/i915/display/intel_combo_phy.c

337

val = intel_de_read(display, ICL_PHY_MISC(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

351

val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

357

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

62

val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));

sys/dev/pci/drm/i915/display/intel_combo_phy.c

98

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_crt.c

1021

adpa = intel_de_read(display, adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

1035

if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_crt.c

1130

display->fdi.rx_config = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

133

tmp = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

491

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

515

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

548

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

564

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

613

stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));

sys/dev/pci/drm/i915/display/intel_crt.c

710

save_bclrpat = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

712

save_vtotal = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

714

vblank = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

727

u32 transconf = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

755

u32 vsync = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

sys/dev/pci/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

sys/dev/pci/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

sys/dev/pci/drm/i915/display/intel_crt.c

96

val = intel_de_read(display, adpa_reg);

sys/dev/pci/drm/i915/display/intel_crt.c

970

adpa = intel_de_read(display, crt->adpa_reg);

sys/dev/pci/drm/i915/display/intel_cursor.c

335

ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;

sys/dev/pci/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

764

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

765

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

766

error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

775

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cursor.c

776

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

179

if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3114

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3195

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

320

} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3352

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3416

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1080

tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1189

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1244

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1269

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1277

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1581

return !(intel_de_read(display, reg) & clk_off);

sys/dev/pci/drm/i915/display/intel_ddi.c

1590

id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;

sys/dev/pci/drm/i915/display/intel_ddi.c

1733

val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));

sys/dev/pci/drm/i915/display/intel_ddi.c

1828

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1881

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1886

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

sys/dev/pci/drm/i915/display/intel_ddi.c

1899

tmp = intel_de_read(display, DDI_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1987

return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

1997

tmp = intel_de_read(display, DPLL_CTRL2);

sys/dev/pci/drm/i915/display/intel_ddi.c

2038

return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;

sys/dev/pci/drm/i915/display/intel_ddi.c

2048

tmp = intel_de_read(display, PORT_CLK_SEL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

2186

ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));

sys/dev/pci/drm/i915/display/intel_ddi.c

2187

ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));

sys/dev/pci/drm/i915/display/intel_ddi.c

2499

dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_ddi.c

3442

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_ddi.c

3735

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3789

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

3821

temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

sys/dev/pci/drm/i915/display/intel_ddi.c

388

u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

sys/dev/pci/drm/i915/display/intel_ddi.c

3881

return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &

sys/dev/pci/drm/i915/display/intel_ddi.c

3929

u32 ctl2 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

3937

u32 ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

4027

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

4056

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

4061

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

4092

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

4106

ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_ddi.c

4818

return intel_de_read(display, SDEISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4826

return intel_de_read(display, DEISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4834

return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;

sys/dev/pci/drm/i915/display/intel_ddi.c

4891

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_ddi.c

5032

return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5034

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5036

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5038

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;

sys/dev/pci/drm/i915/display/intel_ddi.c

5331

ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

689

ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

770

ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

sys/dev/pci/drm/i915/display/intel_ddi.c

818

tmp = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_ddi.c

823

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

863

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_ddi.c

922

tmp = intel_de_read(display, BXT_PHY_CTL(port));

sys/dev/pci/drm/i915/display/intel_display.c

2550

bool bios_lvds_use_ssc = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2831

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2834

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2846

tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2851

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2857

tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2861

tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2867

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2872

tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

2885

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2889

pipe_config->min_hblank = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

2916

tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

2998

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3033

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3273

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3318

m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3319

m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3320

m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3321

m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;

sys/dev/pci/drm/i915/display/intel_display.c

3322

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

sys/dev/pci/drm/i915/display/intel_display.c

3375

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

3462

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3487

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3516

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3586

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3749

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3855

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3862

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3898

tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));

sys/dev/pci/drm/i915/display/intel_display.c

3902

tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/intel_display.c

3963

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

3979

tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_display.c

3998

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

4005

tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

442

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_display.c

532

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

578

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_display.c

735

tmp = intel_de_read(display, PIPE_CHICKEN(pipe));

sys/dev/pci/drm/i915/display/intel_display.c

7721

if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7724

if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))

sys/dev/pci/drm/i915/display/intel_display.c

7739

intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

sys/dev/pci/drm/i915/display/intel_display.c

7743

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

sys/dev/pci/drm/i915/display/intel_display.c

7792

if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7797

if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))

sys/dev/pci/drm/i915/display/intel_display.c

7801

if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7804

if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7807

if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7810

if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)

sys/dev/pci/drm/i915/display/intel_display.c

7835

if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7837

if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)

sys/dev/pci/drm/i915/display/intel_display.c

7842

if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7844

if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)

sys/dev/pci/drm/i915/display/intel_display.c

7853

if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7855

if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)

sys/dev/pci/drm/i915/display/intel_display.c

7871

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7886

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

sys/dev/pci/drm/i915/display/intel_display.c

7891

if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {

sys/dev/pci/drm/i915/display/intel_display.c

7902

if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))

sys/dev/pci/drm/i915/display/intel_display.c

8321

intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8323

intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8325

intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8327

intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);

sys/dev/pci/drm/i915/display/intel_display.c

8329

intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

101

sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

103

sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

105

sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

107

sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

98

sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;

sys/dev/pci/drm/i915/display/intel_display_device.c

1832

!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {

sys/dev/pci/drm/i915/display/intel_display_device.c

1838

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1839

u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1863

u32 dfsm = intel_de_read(display, SKL_DFSM);

sys/dev/pci/drm/i915/display/intel_display_device.c

1912

u32 cap = intel_de_read(display, XE2LPD_DE_CAP);

sys/dev/pci/drm/i915/display/intel_display_device.c

1928

intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;

sys/dev/pci/drm/i915/display/intel_display_irq.c

1209

u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1261

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1273

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1282

val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1318

*pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1331

*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1349

iir = intel_de_read(display, GEN8_DE_MISC_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1360

iir = intel_de_read(display, GEN11_DE_HPD_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1371

iir = intel_de_read(display, GEN8_DE_PORT_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1428

iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

1511

iir = intel_de_read(display, GEN11_GU_MISC_IIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1535

disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1801

tmp = intel_de_read(display, DPINVGTT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1840

*eir = intel_de_read(display, VLV_EIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

185

old_val = intel_de_read(display, GEN8_DE_PORT_IMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

1852

emr = intel_de_read(display, VLV_EMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

2397

snapshot->derrmr = intel_de_read(display, DERRMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

252

u32 sdeimr = intel_de_read(display, SDEIMR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

463

intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

471

intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

472

intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

473

intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

474

intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

475

intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

484

res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

489

res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_irq.c

494

intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

495

intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

496

intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),

sys/dev/pci/drm/i915/display/intel_display_irq.c

560

pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;

sys/dev/pci/drm/i915/display/intel_display_irq.c

687

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

739

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

775

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

818

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_display_irq.c

856

gtt_fault = intel_de_read(display, ILK_GTT_FAULT);

sys/dev/pci/drm/i915/display/intel_display_irq.c

911

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_irq.c

966

u32 pch_iir = intel_de_read(display, SDEIIR);

sys/dev/pci/drm/i915/display/intel_display_power.c

1081

state = intel_de_read(display, reg) & DBUF_POWER_STATE;

sys/dev/pci/drm/i915/display/intel_display_power.c

1185

u32 val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1213

INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),

sys/dev/pci/drm/i915/display/intel_display_power.c

1216

intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1219

intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1222

intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1225

intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,

sys/dev/pci/drm/i915/display/intel_display_power.c

1228

intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1232

intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1235

intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1238

(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),

sys/dev/pci/drm/i915/display/intel_display_power.c

1241

intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,

sys/dev/pci/drm/i915/display/intel_display_power.c

1257

return intel_de_read(display, D_COMP_HSW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1259

return intel_de_read(display, D_COMP_BDW);

sys/dev/pci/drm/i915/display/intel_display_power.c

1289

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1301

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1338

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1361

val = intel_de_read(display, LCPLL_CTL);

sys/dev/pci/drm/i915/display/intel_display_power.c

1809

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

sys/dev/pci/drm/i915/display/intel_display_power.c

1840

u32 status = intel_de_read(display, DPIO_PHY_STATUS);

sys/dev/pci/drm/i915/display/intel_display_power.c

1877

intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1093

if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1095

if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1109

return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1110

intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1246

u32 val = intel_de_read(display, DPLL(display, pipe));

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1407

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1454

intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1890

return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

1924

return intel_de_read(display, XE2LPD_PICA_PW_CTL) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

311

ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

312

ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

314

ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

315

ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;

sys/dev/pci/drm/i915/display/intel_display_power_well.c

612

val = intel_de_read(display, regs->driver);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

622

val |= intel_de_read(display, regs->bios);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

632

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),

sys/dev/pci/drm/i915/display/intel_display_power_well.c

635

intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

639

intel_de_read(display, HSW_PWR_WELL_CTL2) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

661

intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

689

v = intel_de_read(display, DC_STATE_EN);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

740

val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

788

val = intel_de_read(display, DC_STATE_EN);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

846

(intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

874

(intel_de_read(display, UTIL_PIN_CTL) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

879

(intel_de_read(display, DC_STATE_EN) &

sys/dev/pci/drm/i915/display/intel_display_power_well.c

933

u32 bios_req = intel_de_read(display, regs->bios);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

937

u32 drv_req = intel_de_read(display, regs->driver);

sys/dev/pci/drm/i915/display/intel_display_power_well.c

987

return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&

sys/dev/pci/drm/i915/display/intel_display_power_well.c

988

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);

sys/dev/pci/drm/i915/display/intel_dkl_phy.c

54

val = intel_de_read(display, DKL_REG_MMIO(reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1556

dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);

sys/dev/pci/drm/i915/display/intel_dmc.c

1632

intel_de_read(display, dc3co_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1640

seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1647

intel_de_read(display, dc6_reg));

sys/dev/pci/drm/i915/display/intel_dmc.c

1650

intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

sys/dev/pci/drm/i915/display/intel_dmc.c

1654

intel_de_read(display, DMC_SSP_BASE));

sys/dev/pci/drm/i915/display/intel_dmc.c

1655

seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));

sys/dev/pci/drm/i915/display/intel_dmc.c

1678

tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));

sys/dev/pci/drm/i915/display/intel_dmc.c

1709

int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;

sys/dev/pci/drm/i915/display/intel_dmc.c

660

found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

670

found = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_dp.c

4846

u32 val = intel_de_read(display, reg) & ~dip_enable;

sys/dev/pci/drm/i915/display/intel_dp.c

6751

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

322

const u32 status = intel_de_read(display, ch_ctl);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

435

intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

812

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dp_hdcp.c

834

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

1200

intel_de_read(display, dpll_reg) & port_mask,

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

288

old = intel_de_read(display, reg_single);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

336

val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

362

if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

365

if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

373

if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

522

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

649

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

2182

(intel_de_read(display, DPLL(display, PIPE_B)) &

sys/dev/pci/drm/i915/display/intel_dpll.c

2312

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_dpll.c

403

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll.c

409

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

412

hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

413

hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

482

u32 lvds = intel_de_read(display, LVDS);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1248

if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1445

val = intel_de_read(display, regs[id].ctl);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1449

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1454

hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1455

hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1484

val = intel_de_read(display, regs[id].ctl);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1488

val = intel_de_read(display, DPLL_CTRL1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2093

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2107

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2114

temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2132

temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2141

temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2191

val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2195

hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2198

hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2201

hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2204

hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2207

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2210

hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2213

hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2218

hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2221

hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2224

hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2233

hw_state->pcsdw12 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2235

if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2239

intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3566

val = intel_de_read(display, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3570

hw_state->mg_refclkin_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3575

intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3580

intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3587

hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3588

hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3589

hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3590

hw_state->mg_pll_frac_lock = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3592

hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3594

hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3596

intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3631

val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3703

val = intel_de_read(display, enable_reg);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3708

hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3709

hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3711

hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3712

hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3714

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3716

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3719

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3721

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3724

hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3730

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3732

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3735

hw_state->cfgcr0 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3737

hw_state->cfgcr1 = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3958

val = intel_de_read(display, TRANS_CMTG_CHICKEN);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

542

val = intel_de_read(display, PCH_DPLL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

544

hw_state->fp0 = intel_de_read(display, PCH_FP0(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

545

hw_state->fp1 = intel_de_read(display, PCH_FP1(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

557

val = intel_de_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

763

val = intel_de_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

784

val = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_dvo.c

139

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

154

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

170

tmp = intel_de_read(display, DVO(port));

sys/dev/pci/drm/i915/display/intel_dvo.c

300

dvo_val = intel_de_read(display, DVO(port)) &

sys/dev/pci/drm/i915/display/intel_fbc.c

319

fbc_ctl = intel_de_read(display, FBC_CONTROL);

sys/dev/pci/drm/i915/display/intel_fbc.c

357

return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

362

return intel_de_read(fbc->display, FBC_STATUS) &

sys/dev/pci/drm/i915/display/intel_fbc.c

478

dpfc_ctl = intel_de_read(display, DPFC_CONTROL);

sys/dev/pci/drm/i915/display/intel_fbc.c

487

return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

492

return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;

sys/dev/pci/drm/i915/display/intel_fbc.c

547

dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));

sys/dev/pci/drm/i915/display/intel_fbc.c

556

return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;

sys/dev/pci/drm/i915/display/intel_fbc.c

561

return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;

sys/dev/pci/drm/i915/display/intel_fbc.c

698

return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;

sys/dev/pci/drm/i915/display/intel_fdi.c

1005

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1008

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1021

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

105

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

1061

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1063

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

1079

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

1089

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

sys/dev/pci/drm/i915/display/intel_fdi.c

274

fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;

sys/dev/pci/drm/i915/display/intel_fdi.c

393

temp = intel_de_read(display, SOUTH_CHICKEN1);

sys/dev/pci/drm/i915/display/intel_fdi.c

398

intel_de_read(display, FDI_RX_CTL(PIPE_B)) &

sys/dev/pci/drm/i915/display/intel_fdi.c

401

intel_de_read(display, FDI_RX_CTL(PIPE_C)) &

sys/dev/pci/drm/i915/display/intel_fdi.c

42

cur_state = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_fdi.c

447

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

45

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

458

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

499

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

503

intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

508

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

516

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

532

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

554

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

597

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

607

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

621

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

642

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

661

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

67

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;

sys/dev/pci/drm/i915/display/intel_fdi.c

672

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

693

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

sys/dev/pci/drm/i915/display/intel_fdi.c

734

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

743

intel_de_read(display, FDI_RX_IIR(pipe)));

sys/dev/pci/drm/i915/display/intel_fdi.c

749

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

755

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

763

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

776

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

786

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

790

(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

818

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_fdi.c

822

(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {

sys/dev/pci/drm/i915/display/intel_fdi.c

930

temp = intel_de_read(display, DP_TP_STATUS(PORT_E));

sys/dev/pci/drm/i915/display/intel_fdi.c

95

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

102

if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

128

if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

150

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

180

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

214

u32 serr_int = intel_de_read(display, SERR_INT);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

245

if (old && intel_de_read(display, SERR_INT) &

sys/dev/pci/drm/i915/display/intel_flipq.c

178

return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));

sys/dev/pci/drm/i915/display/intel_flipq.c

221

intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));

sys/dev/pci/drm/i915/display/intel_flipq.c

229

intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),

sys/dev/pci/drm/i915/display/intel_flipq.c

230

intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));

sys/dev/pci/drm/i915/display/intel_flipq.c

240

intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));

sys/dev/pci/drm/i915/display/intel_flipq.c

242

tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_flipq.c

433

pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdcp.c

1146

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));

sys/dev/pci/drm/i915/display/intel_hdcp.c

1883

if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1924

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1937

if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

1963

!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

sys/dev/pci/drm/i915/display/intel_hdcp.c

2172

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));

sys/dev/pci/drm/i915/display/intel_hdcp.c

310

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

318

return intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

380

val = intel_de_read(display, HDCP_KEY_STATUS);

sys/dev/pci/drm/i915/display/intel_hdcp.c

389

if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))

sys/dev/pci/drm/i915/display/intel_hdcp.c

715

if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {

sys/dev/pci/drm/i915/display/intel_hdcp.c

866

an.reg[0] = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

868

an.reg[1] = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdcp.c

907

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

sys/dev/pci/drm/i915/display/intel_hdcp.c

942

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

sys/dev/pci/drm/i915/display/intel_hdmi.c

1025

crtc_state->infoframes.gcp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1060

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1118

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1167

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1223

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1248

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1508

scanline = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1591

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,

sys/dev/pci/drm/i915/display/intel_hdmi.c

219

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

261

*data++ = intel_de_read(display, VIDEO_DIP_DATA);

sys/dev/pci/drm/i915/display/intel_hdmi.c

268

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

sys/dev/pci/drm/i915/display/intel_hdmi.c

289

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

333

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

342

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

364

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

411

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

419

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

438

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

483

*data++ = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

492

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_hdmi.c

516

u32 val = intel_de_read(display, ctl_reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

559

*data++ = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

567

u32 val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hdmi.c

80

intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,

sys/dev/pci/drm/i915/display/intel_hdmi.c

875

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_hdmi.c

89

intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

440

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

453

intel_de_read(display, PORT_HOTPLUG_STAT(display)));

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

494

dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);

sys/dev/pci/drm/i915/display/intel_hotplug_irq.c

533

val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));

sys/dev/pci/drm/i915/display/intel_hti.c

21

display->hti.state = intel_de_read(display, HDPORT_STATE);

sys/dev/pci/drm/i915/display/intel_lpe_audio.c

368

audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));

sys/dev/pci/drm/i915/display/intel_lspcon.c

661

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_lvds.c

131

tmp = intel_de_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

149

tmp = intel_de_read(display, PFIT_CONTROL(display));

sys/dev/pci/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_lvds.c

165

val = intel_de_read(display, PP_ON_DELAYS(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

170

val = intel_de_read(display, PP_OFF_DELAYS(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

174

val = intel_de_read(display, PP_DIVISOR(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

216

val = intel_de_read(display, PP_CONTROL(display, 0));

sys/dev/pci/drm/i915/display/intel_lvds.c

820

val = intel_de_read(display, lvds_encoder->reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

871

lvds = intel_de_read(display, lvds_reg);

sys/dev/pci/drm/i915/display/intel_lvds.c

92

val = intel_de_read(display, lvds_reg);

sys/dev/pci/drm/i915/display/intel_overlay.c

1308

attrs->gamma0 = intel_de_read(display, OGAMC0);

sys/dev/pci/drm/i915/display/intel_overlay.c

1309

attrs->gamma1 = intel_de_read(display, OGAMC1);

sys/dev/pci/drm/i915/display/intel_overlay.c

1310

attrs->gamma2 = intel_de_read(display, OGAMC2);

sys/dev/pci/drm/i915/display/intel_overlay.c

1311

attrs->gamma3 = intel_de_read(display, OGAMC3);

sys/dev/pci/drm/i915/display/intel_overlay.c

1312

attrs->gamma4 = intel_de_read(display, OGAMC4);

sys/dev/pci/drm/i915/display/intel_overlay.c

1313

attrs->gamma5 = intel_de_read(display, OGAMC5);

sys/dev/pci/drm/i915/display/intel_overlay.c

1494

error->dovsta = intel_de_read(display, DOVSTA);

sys/dev/pci/drm/i915/display/intel_overlay.c

1495

error->isr = intel_de_read(display, GEN2_ISR);

sys/dev/pci/drm/i915/display/intel_overlay.c

335

tmp = intel_de_read(display, DOVSTA);

sys/dev/pci/drm/i915/display/intel_overlay.c

475

if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

sys/dev/pci/drm/i915/display/intel_overlay.c

955

u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

962

if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)

sys/dev/pci/drm/i915/display/intel_overlay.c

963

tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_overlay.c

965

tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_pch_display.c

111

val = intel_de_read(display, PCH_TRANSCONF(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

121

u32 val = intel_de_read(display, hdmi_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

140

u32 val = intel_de_read(display, dp_reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

230

intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

232

intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

234

intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

237

intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

239

intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

241

intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

243

intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));

sys/dev/pci/drm/i915/display/intel_pch_display.c

263

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

276

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

277

pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

382

temp = intel_de_read(display, PCH_DPLL_SEL);

sys/dev/pci/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

sys/dev/pci/drm/i915/display/intel_pch_display.c

424

temp = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_pch_display.c

506

if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_display.c

511

tmp = intel_de_read(display, FDI_RX_CTL(pipe));

sys/dev/pci/drm/i915/display/intel_pch_display.c

525

tmp = intel_de_read(display, PCH_DPLL_SEL);

sys/dev/pci/drm/i915/display/intel_pch_display.c

557

val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));

sys/dev/pci/drm/i915/display/intel_pch_display.c

566

pipeconf_val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_pch_display.c

625

if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_display.c

630

tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

244

if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

407

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

408

u32 ctl = intel_de_read(display, SPLL_CTL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

426

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

427

u32 ctl = intel_de_read(display, WRPLL_CTL(id));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

543

temp = intel_de_read(display, PCH_DPLL(pll->info->id));

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

564

val = intel_de_read(display, PCH_DREF_CONTROL);

sys/dev/pci/drm/i915/display/intel_pfit.c

626

ctl = intel_de_read(display, PF_CTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

637

pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

638

size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_pfit.c

667

intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);

sys/dev/pci/drm/i915/display/intel_pfit.c

692

intel_de_read(display, PFIT_CONTROL(display)));

sys/dev/pci/drm/i915/display/intel_pfit.c

715

tmp = intel_de_read(display, PFIT_CONTROL(display));

sys/dev/pci/drm/i915/display/intel_pfit.c

730

intel_de_read(display, PFIT_PGM_RATIOS(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

173

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pipe_crc.c

235

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

417

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

419

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

454

return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &

sys/dev/pci/drm/i915/display/intel_pmdemand.c

586

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

sys/dev/pci/drm/i915/display/intel_pmdemand.c

589

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

sys/dev/pci/drm/i915/display/intel_pps.c

106

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

sys/dev/pci/drm/i915/display/intel_pps.c

120

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

sys/dev/pci/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_pps.c

1403

pp_on = intel_de_read(display, regs.pp_on);

sys/dev/pci/drm/i915/display/intel_pps.c

1404

pp_off = intel_de_read(display, regs.pp_off);

sys/dev/pci/drm/i915/display/intel_pps.c

1415

pp_div = intel_de_read(display, regs.pp_div);

sys/dev/pci/drm/i915/display/intel_pps.c

1684

intel_de_read(display, regs.pp_on),

sys/dev/pci/drm/i915/display/intel_pps.c

1685

intel_de_read(display, regs.pp_off),

sys/dev/pci/drm/i915/display/intel_pps.c

1687

intel_de_read(display, regs.pp_div) :

sys/dev/pci/drm/i915/display/intel_pps.c

1688

(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));

sys/dev/pci/drm/i915/display/intel_pps.c

1854

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

sys/dev/pci/drm/i915/display/intel_pps.c

1882

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

sys/dev/pci/drm/i915/display/intel_pps.c

1890

val = intel_de_read(display, pp_reg);

sys/dev/pci/drm/i915/display/intel_pps.c

283

return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;

sys/dev/pci/drm/i915/display/intel_pps.c

288

return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;

sys/dev/pci/drm/i915/display/intel_pps.c

303

u32 port_sel = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_pps.c

382

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

sys/dev/pci/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

sys/dev/pci/drm/i915/display/intel_pps.c

570

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

sys/dev/pci/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_stat_reg(intel_dp)),

sys/dev/pci/drm/i915/display/intel_pps.c

591

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

sys/dev/pci/drm/i915/display/intel_pps.c

627

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

628

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

630

ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

638

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

639

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

731

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

sys/dev/pci/drm/i915/display/intel_pps.c

787

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

788

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_pps.c

860

intel_de_read(display, pp_stat_reg),

sys/dev/pci/drm/i915/display/intel_pps.c

861

intel_de_read(display, pp_ctrl_reg));

sys/dev/pci/drm/i915/display/intel_psr.c

1098

tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1777

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1786

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

1801

intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

1804

intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);

sys/dev/pci/drm/i915/display/intel_psr.c

1992

val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

2083

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

2088

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

3995

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4011

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4099

val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

4102

psr2_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4108

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_psr.c

4112

val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

4127

val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_psr.c

4151

val = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1626

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1672

val = intel_de_read(display, sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1714

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1849

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1910

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

sys/dev/pci/drm/i915/display/intel_sdvo.c

235

cval = intel_de_read(display, GEN3_SDVOC);

sys/dev/pci/drm/i915/display/intel_sdvo.c

237

bval = intel_de_read(display, GEN3_SDVOB);

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

sys/dev/pci/drm/i915/display/intel_sprite.c

1227

error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1228

error->surf = intel_de_read(display, DVSSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1229

error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

1246

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/pci/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

886

error->surf = intel_de_read(display, SPRSURF(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

887

error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));

sys/dev/pci/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/pci/drm/i915/display/intel_tc.c

1024

pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);

sys/dev/pci/drm/i915/display/intel_tc.c

1025

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

1048

return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;

sys/dev/pci/drm/i915/display/intel_tc.c

1112

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

1156

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

1172

return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;

sys/dev/pci/drm/i915/display/intel_tc.c

1575

return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &

sys/dev/pci/drm/i915/display/intel_tc.c

276

lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

316

val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/intel_tc.c

440

val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

536

fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

537

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

573

val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

592

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

617

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

sys/dev/pci/drm/i915/display/intel_tc.c

781

val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));

sys/dev/pci/drm/i915/display/intel_tc.c

828

cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);

sys/dev/pci/drm/i915/display/intel_tc.c

829

pch_isr = intel_de_read(display, SDEISR);

sys/dev/pci/drm/i915/display/intel_tc.c

858

val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));

sys/dev/pci/drm/i915/display/intel_tc.c

891

val = intel_de_read(display, DDI_BUF_CTL(port));

sys/dev/pci/drm/i915/display/intel_tv.c

1106

tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1107

hctl1 = intel_de_read(display, TV_H_CTL_1);

sys/dev/pci/drm/i915/display/intel_tv.c

1108

hctl3 = intel_de_read(display, TV_H_CTL_3);

sys/dev/pci/drm/i915/display/intel_tv.c

1109

vctl1 = intel_de_read(display, TV_V_CTL_1);

sys/dev/pci/drm/i915/display/intel_tv.c

1110

vctl2 = intel_de_read(display, TV_V_CTL_2);

sys/dev/pci/drm/i915/display/intel_tv.c

1145

tmp = intel_de_read(display, TV_WIN_POS);

sys/dev/pci/drm/i915/display/intel_tv.c

1149

tmp = intel_de_read(display, TV_WIN_SIZE);

sys/dev/pci/drm/i915/display/intel_tv.c

1452

tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1578

intel_de_read(display, TV_DAC) & TV_DAC_SAVE);

sys/dev/pci/drm/i915/display/intel_tv.c

1601

save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1602

save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_tv.c

1635

tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1938

if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)

sys/dev/pci/drm/i915/display/intel_tv.c

1950

save_tv_dac = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1953

tv_dac_on = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

1956

tv_dac_off = intel_de_read(display, TV_DAC);

sys/dev/pci/drm/i915/display/intel_tv.c

919

u32 tmp = intel_de_read(display, TV_CTL);

sys/dev/pci/drm/i915/display/intel_vblank.c

134

return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));

sys/dev/pci/drm/i915/display/intel_vblank.c

487

line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vblank.c

489

line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1021

dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vdsc.c

1022

dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));

sys/dev/pci/drm/i915/display/intel_vdsc.c

876

val = intel_de_read(display, dsc_reg[0]);

sys/dev/pci/drm/i915/display/intel_vdsc.c

879

if (intel_de_read(display, dsc_reg[i]) != val) {

sys/dev/pci/drm/i915/display/intel_vga.c

53

tmp = intel_de_read(display, vga_reg);

sys/dev/pci/drm/i915/display/intel_vrr.c

477

!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));

sys/dev/pci/drm/i915/display/intel_vrr.c

580

return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;

sys/dev/pci/drm/i915/display/intel_vrr.c

725

trans_vrr_ctl = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

749

crtc_state->vrr.flipline = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

751

crtc_state->vrr.vmax = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

753

crtc_state->vrr.vmin = intel_de_read(display,

sys/dev/pci/drm/i915/display/intel_vrr.c

768

intel_de_read(display,

sys/dev/pci/drm/i915/display/skl_scaler.c

919

ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

926

pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_scaler.c

927

size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1662

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1663

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

1664

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

2792

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3042

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3052

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3145

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3148

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3151

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

3155

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_universal_plane.c

935

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/pci/drm/i915/display/skl_watermark.c

108

val = intel_de_read(display, MTL_LATENCY_SAGV);

sys/dev/pci/drm/i915/display/skl_watermark.c

3022

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3024

val = intel_de_read(display, CUR_WM(pipe, level));

sys/dev/pci/drm/i915/display/skl_watermark.c

3030

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3032

val = intel_de_read(display, CUR_WM_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3038

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3040

val = intel_de_read(display, CUR_WM_SAGV(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3045

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

3047

val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

3064

dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

sys/dev/pci/drm/i915/display/skl_watermark.c

3226

val = intel_de_read(display, MTL_LATENCY_LP0_LP1);

sys/dev/pci/drm/i915/display/skl_watermark.c

3230

val = intel_de_read(display, MTL_LATENCY_LP2_LP3);

sys/dev/pci/drm/i915/display/skl_watermark.c

3234

val = intel_de_read(display, MTL_LATENCY_LP4_LP5);

sys/dev/pci/drm/i915/display/skl_watermark.c

681

val = intel_de_read(display, CUR_BUF_CFG(pipe));

sys/dev/pci/drm/i915/display/skl_watermark.c

686

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

690

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

699

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

sys/dev/pci/drm/i915/display/skl_watermark.c

80

if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1035

if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)

sys/dev/pci/drm/i915/display/vlv_dsi.c

1039

fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;

sys/dev/pci/drm/i915/display/vlv_dsi.c

1051

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1054

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1057

intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

1061

hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1067

hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1068

hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1085

vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1086

vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1087

vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

125

u32 val = intel_de_read(display, reg);

sys/dev/pci/drm/i915/display/vlv_dsi.c

1331

tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));

sys/dev/pci/drm/i915/display/vlv_dsi.c

1337

tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

242

if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))

sys/dev/pci/drm/i915/display/vlv_dsi.c

347

u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

363

!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);

sys/dev/pci/drm/i915/display/vlv_dsi.c

387

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

448

val = intel_de_read(display, MIPI_DEVICE_READY(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi.c

638

temp = intel_de_read(display, port_ctrl);

sys/dev/pci/drm/i915/display/vlv_dsi.c

962

bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;

sys/dev/pci/drm/i915/display/vlv_dsi.c

971

enabled = intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

976

u32 tmp = intel_de_read(display,

sys/dev/pci/drm/i915/display/vlv_dsi.c

984

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))

sys/dev/pci/drm/i915/display/vlv_dsi.c

988

u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

278

val = intel_de_read(display, BXT_DSI_PLL_ENABLE);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

292

val = intel_de_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

366

config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

382

temp = intel_de_read(display, MIPI_CTRL(display, port));

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

447

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

sys/dev/pci/drm/i915/display/vlv_dsi_pll.c

588

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);