Symbol: for_each_set_bit
sys/dev/pci/drm/amd/amdgpu/amdgpu_gart.c
426
for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
603
for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c
410
for_each_set_bit(umc_node_inst, &(adev->umc.active_mask),
sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h
50
for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
363
for_each_set_bit(i, adev->vmhubs_mask,
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
355
for_each_set_bit(i, adev->vmhubs_mask,
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
391
for_each_set_bit(i, adev->vmhubs_mask,
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
2229
for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
481
for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
509
for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
972
for_each_set_bit(i, adev->vmhubs_mask,
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
1127
for_each_set_bit(i, p->svms.bitmap_supported, p->n_pdds) {
sys/dev/pci/drm/amd/amdkfd/kfd_process.c
625
for_each_set_bit(i, p->svms.bitmap_supported, p->n_pdds) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1370
for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1493
for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1551
for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1569
for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
1710
for_each_set_bit(idx, ctx->bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
217
for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2340
for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
2530
for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) {
sys/dev/pci/drm/amd/amdkfd/kfd_svm.c
3495
for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) {
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
3790
for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) {
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
737
for_each_set_bit(dep_bit, (unsigned long *)&dep_status, 32)
sys/dev/pci/drm/display/drm_dp_tunnel.c
1651
for_each_set_bit(id, &move_mask, BITS_PER_TYPE(move_mask))
sys/dev/pci/drm/drm_drv.c
656
for_each_set_bit(opt, &method, BITS_PER_TYPE(method)) {
sys/dev/pci/drm/drm_print.c
327
for_each_set_bit(i, &value, nbits) {
sys/dev/pci/drm/i915/display/intel_display_power.c
1179
for_each_set_bit(i, &abox_regs, BITS_PER_TYPE(abox_regs))
sys/dev/pci/drm/i915/display/intel_display_power.c
1644
for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask))
sys/dev/pci/drm/i915/display/intel_display_power.c
1648
for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) {
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
376
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
sys/dev/pci/drm/i915/gem/i915_gem_pages.c
62
for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) {
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
515
for_each_set_bit(bit, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) {
sys/dev/pci/drm/i915/gt/intel_gt_irq.c
159
for_each_set_bit(bit, &intr_dw, 32) {
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
149
for_each_set_bit(i, &fuse, 3)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1374
for_each_set_bit(i, &gt->info.mslice_mask, GEN12_MAX_MSLICES)
sys/dev/pci/drm/i915/gt/selftest_tlb.c
315
for_each_set_bit(bit,
sys/dev/pci/drm/i915/gt/sysfs_engines.c
110
for_each_set_bit(n, &caps, show_unknown ? BITS_PER_LONG : count) {
sys/dev/pci/drm/i915/gvt/display.c
651
for_each_set_bit(event, irq->flip_done_event[pipe],
sys/dev/pci/drm/i915/gvt/gtt.c
1610
for_each_set_bit(index, spt->post_shadow_bitmap,
sys/dev/pci/drm/i915/gvt/interrupt.c
173
for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
sys/dev/pci/drm/i915/gvt/interrupt.c
532
for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
sys/dev/pci/drm/i915/gvt/scheduler.c
1104
for_each_set_bit(event, workload->pending_events,
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
62
for_each_set_bit(i, (unsigned long *)&p->bitmap, KSYNCMAP) {
sys/dev/pci/drm/i915/selftests/i915_syncmap.c
77
for_each_set_bit(i, (unsigned long *)&p->bitmap, KSYNCMAP) {
sys/dev/pci/drm/i915/selftests/intel_uncore.c
315
for_each_set_bit(offset, valid, FW_RANGE) {