lib/libcrypto/dh/dh.h

129

DH *DH_new_method(ENGINE *engine);

lib/libcrypto/dh/dh_lib.c

115

DH_new_method(ENGINE *engine)

lib/libcrypto/dsa/dsa.h

132

DSA * DSA_new_method(ENGINE *engine);

lib/libcrypto/dsa/dsa_lib.c

121

DSA_new_method(ENGINE *engine)

lib/libcrypto/ec/ec.h

286

EC_KEY *EC_KEY_new_method(ENGINE *engine);

lib/libcrypto/ec/ec_key.c

563

EC_KEY_new_method(ENGINE *engine)

lib/libcrypto/engine/engine.h

103

int ENGINE_free(ENGINE *engine);

lib/libcrypto/engine/engine.h

104

int ENGINE_init(ENGINE *engine);

lib/libcrypto/engine/engine.h

105

int ENGINE_finish(ENGINE *engine);

lib/libcrypto/engine/engine.h

108

const char *ENGINE_get_id(const ENGINE *engine);

lib/libcrypto/engine/engine.h

109

const char *ENGINE_get_name(const ENGINE *engine);

lib/libcrypto/engine/engine.h

111

int ENGINE_set_default(ENGINE *engine, unsigned int flags);

lib/libcrypto/engine/engine.h

114

int ENGINE_set_default_RSA(ENGINE *engine);

lib/libcrypto/engine/engine.h

116

int ENGINE_ctrl_cmd(ENGINE *engine, const char *cmd_name, long i, void *p,

lib/libcrypto/engine/engine.h

118

int ENGINE_ctrl_cmd_string(ENGINE *engine, const char *cmd, const char *arg,

lib/libcrypto/engine/engine.h

121

EVP_PKEY *ENGINE_load_private_key(ENGINE *engine, const char *key_id,

lib/libcrypto/engine/engine.h

123

EVP_PKEY *ENGINE_load_public_key(ENGINE *engine, const char *key_id,

lib/libcrypto/engine/engine_stubs.c

104

ENGINE_set_default_RSA(ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

111

ENGINE_ctrl_cmd(ENGINE *engine, const char *cmd_name, long i, void *p,

lib/libcrypto/engine/engine_stubs.c

119

ENGINE_ctrl_cmd_string(ENGINE *engine, const char *cmd, const char *arg,

lib/libcrypto/engine/engine_stubs.c

127

ENGINE_load_private_key(ENGINE *engine, const char *key_id,

lib/libcrypto/engine/engine_stubs.c

135

ENGINE_load_public_key(ENGINE *engine, const char *key_id,

lib/libcrypto/engine/engine_stubs.c

48

ENGINE_free(ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

55

ENGINE_init(ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

62

ENGINE_finish(ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

76

ENGINE_get_id(const ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

83

ENGINE_get_name(const ENGINE *engine)

lib/libcrypto/engine/engine_stubs.c

90

ENGINE_set_default(ENGINE *engine, unsigned int flags)

lib/libcrypto/evp/evp.h

406

EVP_PKEY *EVP_PKEY_new_raw_private_key(int type, ENGINE *engine,

lib/libcrypto/evp/evp.h

408

EVP_PKEY *EVP_PKEY_new_raw_public_key(int type, ENGINE *engine,

lib/libcrypto/evp/evp_cipher.c

133

EVP_CipherInit_ex(EVP_CIPHER_CTX *ctx, const EVP_CIPHER *cipher, ENGINE *engine,

lib/libcrypto/evp/evp_cipher.c

288

EVP_EncryptInit_ex(EVP_CIPHER_CTX *ctx, const EVP_CIPHER *cipher, ENGINE *engine,

lib/libcrypto/evp/evp_cipher.c

477

EVP_DecryptInit_ex(EVP_CIPHER_CTX *ctx, const EVP_CIPHER *cipher, ENGINE *engine,

lib/libcrypto/evp/p_lib.c

186

EVP_PKEY_asn1_find(ENGINE **engine, int pkey_id)

lib/libcrypto/evp/p_lib.c

190

if (engine != NULL)

lib/libcrypto/evp/p_lib.c

191

*engine = NULL;

lib/libcrypto/evp/p_lib.c

203

EVP_PKEY_asn1_find_str(ENGINE **engine, const char *str, int len)

lib/libcrypto/evp/p_lib.c

208

if (engine != NULL)

lib/libcrypto/evp/p_lib.c

209

*engine = NULL;

lib/libcrypto/evp/p_lib.c

480

EVP_PKEY_new_raw_private_key(int type, ENGINE *engine,

lib/libcrypto/evp/p_lib.c

510

EVP_PKEY_new_raw_public_key(int type, ENGINE *engine,

lib/libcrypto/evp/pmeth_lib.c

156

EVP_PKEY_CTX_new(EVP_PKEY *pkey, ENGINE *engine)

lib/libcrypto/evp/pmeth_lib.c

163

EVP_PKEY_CTX_new_id(int nid, ENGINE *engine)

lib/libcrypto/rsa/rsa.h

235

RSA *RSA_new_method(ENGINE *engine);

lib/libcrypto/rsa/rsa_lib.c

129

RSA_new_method(ENGINE *engine)

sbin/dhcp6leased/dhcp6leased.c

191

engine(debug, verbose);

sbin/dhcp6leased/engine.h

34

void engine(int, int);

sbin/dhcpleased/dhcpleased.c

201

engine(debug, verbose);

sbin/dhcpleased/engine.h

32

void engine(int, int);

sbin/slaacd/engine.h

37

void engine(int, int);

sbin/slaacd/slaacd.c

177

engine(debug, verbose);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

648

enum kgd_engine_type engine,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

658

switch (engine) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

669

pr_err("Invalid engine in IB submission: %d\n", engine);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

171

enum kgd_engine_type engine,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

513

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

515

uint32_t reg_offset = get_sdma_rlc_reg_offset(adev, engine, queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1088

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

70

int engine, int queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

804

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

365

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

565

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

586

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1227

int engine, int queue)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

116

int engine, int queue);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8881

cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

125

enum i2c_command_engine engine;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

108

struct dce_aux *engine)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

110

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

184

struct dce_aux *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

187

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

277

EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

281

static int read_channel_reply(struct dce_aux *engine, uint32_t size,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

285

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

335

struct dce_aux *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

338

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

399

struct dce_aux *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

40

engine->ctx->logger

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

404

if ((engine == NULL) || !is_engine_available(engine))

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

413

if (!acquire_engine(engine)) {

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

414

engine->ddc = ddc;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

415

release_engine(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

419

engine->ddc = ddc;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

424

void dce110_engine_destroy(struct dce_aux **engine)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

427

struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

430

*engine = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

79

struct dce_aux *engine)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

81

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

83

dal_ddc_close(engine->ddc);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

85

engine->ddc = NULL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

95

struct dce_aux *engine)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

97

struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

297

void dce110_engine_destroy(struct dce_aux **engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

341

struct dce_i2c_sw *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

346

engine->speed = speed ? speed : DCE_I2C_DEFAULT_I2C_SW_SPEED;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

348

engine->clock_delay = 1000 / engine->speed;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

350

if (engine->clock_delay < 12)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

351

engine->clock_delay = 12;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

355

struct dce_i2c_sw *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

366

engine->ddc = ddc;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

396

static void dce_i2c_sw_engine_submit_channel_request(struct dce_i2c_sw *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

399

struct ddc *ddc = engine->ddc;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

400

uint16_t clock_delay_div_4 = engine->clock_delay >> 2;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

404

bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

412

result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

417

result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

431

if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4))

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

439

static bool dce_i2c_sw_engine_submit_payload(struct dce_i2c_sw *engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

458

dce_i2c_sw_engine_submit_channel_request(engine, &request);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1622

enum engine_id engine,

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1628

if (engine != ENGINE_ID_UNKNOWN) {

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1633

field |= get_frontend_source(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1635

field &= ~get_frontend_source(engine);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

574

enum engine_id engine)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

576

switch (engine) {

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

296

enum engine_id engine,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1346

enum engine_id engine,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1352

if (engine != ENGINE_ID_UNKNOWN) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1357

field |= get_frontend_source(engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1359

field &= ~get_frontend_source(engine);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

424

enum engine_id engine)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

426

switch (engine) {

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

631

enum engine_id engine,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

177

i2c_command.engine = I2C_COMMAND_ENGINE_HW;//only HW

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

155

struct aux_engine *engine);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

157

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

160

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

163

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

166

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

172

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

174

bool (*is_engine_available)(struct aux_engine *engine);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

176

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

179

struct aux_engine *engine,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

183

struct aux_engine *engine);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

185

struct aux_engine **engine);

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

144

enum engine_id engine,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

306

.engine = DDC_I2C_COMMAND_ENGINE,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

332

cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

378

command.engine = DDC_I2C_COMMAND_ENGINE;

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c

77

enum engine_id engine,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

339

int engine, int queue);

sys/dev/pci/drm/i915/display/intel_overlay.c

1405

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/display/intel_overlay.c

1411

engine = to_gt(dev_priv)->engine[RCS0];

sys/dev/pci/drm/i915/display/intel_overlay.c

1412

if (!engine || !engine->kernel_context)

sys/dev/pci/drm/i915/display/intel_overlay.c

1420

overlay->context = engine->kernel_context;

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

77

return flag(rq->engine->uabi_class);

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

91

BUILD_BUG_ON(!typecheck(u16, rq->engine->uabi_class));

sys/dev/pci/drm/i915/gem/i915_gem_busy.c

92

return flag(rq->engine->uabi_class);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1009

if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1073

unsigned int class = ce->engine->uabi_class;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1127

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1134

for_each_uabi_engine(engine, ctx->i915) {

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1139

if (engine->legacy_idx == INVALID_ENGINE)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1142

GEM_BUG_ON(engine->legacy_idx >= max);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1143

GEM_BUG_ON(e->engines[engine->legacy_idx]);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1145

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1151

e->engines[engine->legacy_idx] = ce;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1152

e->num_engines = max(e->num_engines, engine->legacy_idx + 1);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1154

if (engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1224

ce = intel_context_create(pe[n].engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1338

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1340

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1344

static bool __cancel_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1360

return intel_engine_pulse(engine) == 0;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1365

struct intel_engine_cs *engine = NULL;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1390

found = i915_request_active_engine(rq, &engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1398

return engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1415

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1427

engine = active_engine(ce);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1430

if (engine && !__cancel_engine(engine) && (exit || !persistent))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1436

__reset_context(engines->ctx, engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

164

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

166

engine = intel_engine_lookup_user(ctx->i915,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

169

if (!engine)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

172

idx = engine->legacy_idx;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2065

ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2070

if (ce->engine->class != RENDER_CLASS) {

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2075

ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2114

if (!intel_engine_has_timeslices(ce->engine))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2118

intel_engine_has_semaphores(ce->engine))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2169

ce = lookup_user_engine(ctx, lookup, &user.engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2173

if (user.size < ce->engine->context_size) {

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2190

state = memdup_user(u64_to_user_ptr(user.image), ce->engine->context_size);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2196

shmem_state = uao_create_from_data(ce->engine->name,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2197

state, ce->engine->context_size);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

2535

ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

478

set->engines[idx].engine = siblings[0];

sys/dev/pci/drm/i915/gem/i915_gem_context.c

777

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

790

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/gem/i915_gem_context.c

793

if (!engine) {

sys/dev/pci/drm/i915/gem/i915_gem_context.c

802

set.engines[n].engine = engine;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

851

int idx = user_sseu.engine.engine_instance;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

861

if (pe->engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

867

if (user_sseu.engine.engine_class != I915_ENGINE_CLASS_RENDER)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

871

if (user_sseu.engine.engine_instance != 0)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

988

if (ce->engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

997

intel_engine_has_timeslices(ce->engine) &&

sys/dev/pci/drm/i915/gem/i915_gem_context.c

998

intel_engine_has_semaphores(ce->engine))

sys/dev/pci/drm/i915/gem/i915_gem_context_types.h

112

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2210

if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2341

err = intel_engine_cmd_parser(eb->context->engine,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2390

if (rq->context->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2391

err = rq->context->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2396

err = rq->context->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2407

err = rq->context->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2700

gt = ce->engine->gt;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2704

eb->wakeref = intel_gt_pm_get(ce->engine->gt);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2729

err = intel_gt_terminally_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2739

eb->gt = ce->engine->gt;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2752

intel_gt_pm_put(ce->engine->gt, eb->wakeref);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2771

intel_gt_pm_put(eb->context->engine->gt, eb->wakeref);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

326

return intel_engine_requires_cmd_parser(eb->context->engine) ||

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

327

(intel_engine_using_cmd_parser(eb->context->engine) &&

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

215

intel_engine_pm_get(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

229

intel_engine_pm_get(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

242

intel_engine_pm_put(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

101

engine = rq->engine;

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

104

if (engine->sched_engine->schedule)

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

105

engine->sched_engine->schedule(rq, attr);

sys/dev/pci/drm/i915/gem/i915_gem_wait.c

95

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1233

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1272

if (!ce || !intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1301

__func__, ce->engine->name, offset_low, offset_high,

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1697

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1722

if (!ce || !intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/huge_pages.c

1897

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

156

struct intel_gt *gt = t->ce->engine->gt;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

164

*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

300

struct drm_i915_private *i915 = t->ce->engine->i915;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

513

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

534

tiled_blits_create(struct intel_engine_cs *engine, struct rnd_state *prng)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

545

t->ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

660

static int __igt_client_tiled_blits(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

666

t = tiled_blits_create(engine, prng);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

717

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

720

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

723

if (!engine)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

726

err = __igt_client_tiled_blits(engine, &prng);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

20

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

210

rq = intel_engine_create_kernel_request(ctx->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

222

if (GRAPHICS_VER(ctx->engine->i915) >= 8) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

227

} else if (GRAPHICS_VER(ctx->engine->i915) >= 4) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

259

struct intel_gt *gt = ctx->engine->gt;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

269

if (intel_gt_is_wedged(ctx->engine->gt))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

272

return intel_engine_can_store_dword(ctx->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

291

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

295

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

299

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

301

return engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

332

ctx.engine = random_engine(i915, &prng);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

333

if (!ctx.engine) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

337

pr_info("%s: using %s\n", __func__, ctx.engine->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

338

intel_engine_pm_get(ctx.engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

417

intel_engine_pm_put(ctx.engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1005

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1006

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1011

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

106

nctx, engine->name, ktime_to_ns(times[1] - times[0]));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1060

ret = igt_spinner_init(*spin, ce->engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

108

err = igt_live_test_begin(&t, i915, __func__, engine->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1119

if (GRAPHICS_VER(ce->engine->i915) >= 11) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1169

unsigned int slices = hweight32(ce->engine->sseu.slice_mask);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1174

ret = intel_engine_reset(ce->engine, "sseu");

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1185

ret = __read_slice_count(ce->engine->kernel_context, obj, NULL, &rpcs);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1193

ret = igt_flush_test(ce->engine->i915);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

120

this = igt_request_alloc(ctx[n % nctx], engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1215

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1235

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1261

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1265

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1268

if (!engine)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1271

if (hweight32(engine->sseu.slice_mask) < 2)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1274

if (!engine->gt->info.sseu.has_slice_pg)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1281

pg_sseu = engine->sseu;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1284

~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1287

engine->name, name, flags,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1288

hweight32(engine->sseu.slice_mask),

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1291

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1302

ret = __sseu_test(name, flags, ce, obj, engine->sseu);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1312

ret = __sseu_test(name, flags, ce, obj, engine->sseu);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1411

if (intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1420

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1439

ce->engine->name,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1509

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

152

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1543

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1556

rq = igt_request_alloc(ctx, engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1566

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1567

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1572

err = engine->emit_bb_start(rq, i915_vma_offset(vma),

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1597

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1617

const u32 GPR0 = engine->mmio_base + 0x600;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1652

const u32 reg = engine->mmio_base + 0x420;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1655

vm = i915_vm_get(&engine->gt->ggtt->vm);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1687

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1689

rq = igt_request_alloc(ctx, engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1699

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1700

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1705

err = engine->emit_bb_start(rq, i915_vma_offset(vma),

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

171

engine->name,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1776

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1842

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1846

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1850

if (GRAPHICS_VER(i915) < 8 && engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1862

err = write_to_scratch(ctx_a, engine, obj_a,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1865

err = read_from_scratch(ctx_b, engine, obj_b,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

1872

engine->name, value,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

236

arg->ce[0]->engine->name, count, arg->result);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

279

arg->ce[0]->engine->name, count, arg->result);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

350

ce = intel_context_create(data[m].ce[0]->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

37

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

373

data[n].ce[0]->engine->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

449

GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

662

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

674

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

683

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

686

if (!engine->context_size)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

693

err = igt_live_test_begin(&t, i915, __func__, engine->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

710

ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

727

engine->name,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

73

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

755

ncontexts, engine->name, ndwords);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

789

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

82

this = igt_request_alloc(ctx[n], engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

821

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

827

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

843

ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

861

engine->name,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

888

ncontexts, engine->name, ndwords);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

915

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

926

*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

952

GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

96

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

987

err = rpcs_query_batch(rpcs, vma, ce->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_dmabuf.c

172

if (intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

373

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

388

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_migrate.c

397

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1540

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1581

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1586

vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1600

rq = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1608

err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1614

drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1617

__func__, engine->name, obj->mm.region->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1618

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1619

"%s\n", engine->name);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1621

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

543

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

545

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

551

vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

563

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

120

GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

145

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

21

igt_request_alloc(struct i915_gem_context *ctx, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c

31

ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);

sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.h

22

igt_request_alloc(struct i915_gem_context *ctx, struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

105

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

115

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

147

GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

191

intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

194

GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

293

void gen2_irq_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

295

engine->i915->irq_mask &= ~engine->irq_enable_mask;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

296

intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

297

intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

300

void gen2_irq_disable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

302

engine->i915->irq_mask |= engine->irq_enable_mask;

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

303

intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

306

void gen5_irq_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

308

gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

311

void gen5_irq_disable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen2_engine_cs.c

313

gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

31

void gen2_irq_enable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

32

void gen2_irq_disable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

33

void gen5_irq_enable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen2_engine_cs.h

34

void gen5_irq_disable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

153

*cs++ = intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

292

intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

377

GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

397

GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

425

void gen6_irq_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

427

ENGINE_WRITE(engine, RING_IMR,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

428

~(engine->irq_enable_mask | engine->irq_keep_mask));

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

431

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

433

gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

436

void gen6_irq_disable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

438

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

439

gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

442

void hsw_irq_enable_vecs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

444

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

447

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

449

gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

452

void hsw_irq_disable_vecs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

454

ENGINE_WRITE(engine, RING_IMR, ~0);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

455

gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

58

intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.c

92

intel_gt_scratch_offset(rq->engine->gt,

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

33

void gen6_irq_enable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

34

void gen6_irq_disable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

36

void hsw_irq_enable_vecs(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen6_engine_cs.h

37

void hsw_irq_disable_vecs(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

432

int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

438

batch_get_defaults(engine->i915, &bv);

sys/dev/pci/drm/i915/gt/gen7_renderclear.h

12

int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

168

static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

170

switch (engine->id) {

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

188

static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

190

i915_reg_t reg = gen12_get_aux_inv_reg(engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

196

return i915_mmio_reg_valid(reg) && !HAS_FLAT_CCS(engine->i915);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

199

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

201

i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

202

u32 gsi_offset = engine->gt->uncore->gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

204

if (!gen12_needs_ccs_aux_inv(engine))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

226

if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

246

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

252

if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) {

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

295

if (!HAS_3D_PIPELINE(engine->i915))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

297

else if (engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

331

if (!HAS_3D_PIPELINE(engine->i915))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

333

else if (engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

337

if (gen12_needs_ccs_aux_inv(rq->engine))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

353

cs = gen12_emit_aux_table_inv(engine, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

370

if (gen12_needs_ccs_aux_inv(rq->engine))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

393

if (rq->engine->class == VIDEO_DECODE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

396

if (gen12_needs_ccs_aux_inv(rq->engine) &&

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

397

rq->engine->class == COPY_ENGINE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

406

cs = gen12_emit_aux_table_inv(rq->engine, cs);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

416

static u32 preempt_address(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

418

return (i915_ggtt_offset(engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

634

*cs++ = preempt_address(rq->engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

647

if (intel_engine_has_semaphores(rq->engine) &&

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

648

!intel_uc_uses_guc_submission(&rq->engine->gt->uc))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

735

*cs++ = preempt_address(rq->engine);

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

789

if (intel_engine_has_semaphores(rq->engine) &&

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

790

!intel_uc_uses_guc_submission(&rq->engine->gt->uc))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

796

if (intel_engine_uses_wa_hold_switchout(rq->engine))

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

815

struct intel_gt *gt = rq->engine->gt;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

839

else if (rq->engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

99

if (rq->engine->class == VIDEO_DECODE_CLASS)

sys/dev/pci/drm/i915/gt/gen8_engine_cs.h

50

u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

256

if (rq->engine->sched_engine->retire_inflight_request_prio)

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

257

rq->engine->sched_engine->retire_inflight_request_prio(rq);

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

352

struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

439

struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

514

void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

519

b = engine->breadcrumbs;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.h

37

intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.h

39

irq_work_queue(&engine->breadcrumbs->irq_work);

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.h

42

void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_context.c

106

if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||

sys/dev/pci/drm/i915/gt/intel_context.c

112

ce->engine);

sys/dev/pci/drm/i915/gt/intel_context.c

268

intel_engine_pm_might_get(ce->engine);

sys/dev/pci/drm/i915/gt/intel_context.c

400

intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_context.c

402

GEM_BUG_ON(!engine->cops);

sys/dev/pci/drm/i915/gt/intel_context.c

403

GEM_BUG_ON(!engine->gt->vm);

sys/dev/pci/drm/i915/gt/intel_context.c

407

ce->engine = engine;

sys/dev/pci/drm/i915/gt/intel_context.c

408

ce->ops = engine->cops;

sys/dev/pci/drm/i915/gt/intel_context.c

409

ce->sseu = engine->sseu;

sys/dev/pci/drm/i915/gt/intel_context.c

415

ce->vm = i915_vm_get(engine->gt->vm);

sys/dev/pci/drm/i915/gt/intel_context.c

489

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/gt/intel_context.c

49

intel_context_create(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_context.c

496

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/gt/intel_context.c

57

intel_context_init(ce, engine);

sys/dev/pci/drm/i915/gt/intel_context.c

570

GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));

sys/dev/pci/drm/i915/gt/intel_context.c

623

total *= ce->engine->gt->clock_period_ns;

sys/dev/pci/drm/i915/gt/intel_context.c

637

avg *= ce->engine->gt->clock_period_ns;

sys/dev/pci/drm/i915/gt/intel_context.c

660

ce->ops->revoke(ce, NULL, ce->engine->props.preempt_timeout_ms);

sys/dev/pci/drm/i915/gt/intel_context.h

24

ENGINE_TRACE(ce__->engine, "context:%llx " fmt, \

sys/dev/pci/drm/i915/gt/intel_context.h

34

struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_context.h

41

intel_context_create(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

33

*cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

57

rq = intel_engine_create_kernel_request(ce->engine);

sys/dev/pci/drm/i915/gt/intel_context_sseu.c

80

GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);

sys/dev/pci/drm/i915/gt/intel_context_types.h

67

struct intel_context *(*create_virtual)(struct intel_engine_cs **engine,

sys/dev/pci/drm/i915/gt/intel_context_types.h

73

struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_context_types.h

89

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_context_types.h

91

#define __intel_context_inflight(engine) ptr_mask_bits(engine, 3)

sys/dev/pci/drm/i915/gt/intel_context_types.h

92

#define __intel_context_inflight_count(engine) ptr_unmask_bits(engine, 3)

sys/dev/pci/drm/i915/gt/intel_engine.h

153

intel_read_status_page(const struct intel_engine_cs *engine, int reg)

sys/dev/pci/drm/i915/gt/intel_engine.h

156

return READ_ONCE(engine->status_page.addr[reg]);

sys/dev/pci/drm/i915/gt/intel_engine.h

160

intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)

sys/dev/pci/drm/i915/gt/intel_engine.h

167

drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));

sys/dev/pci/drm/i915/gt/intel_engine.h

168

WRITE_ONCE(engine->status_page.addr[reg], value);

sys/dev/pci/drm/i915/gt/intel_engine.h

169

drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));

sys/dev/pci/drm/i915/gt/intel_engine.h

207

void intel_engine_stop(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

208

void intel_engine_cleanup(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

213

void intel_engine_free_request_pool(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

218

int intel_engine_init_common(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

219

void intel_engine_cleanup_common(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

221

int intel_engine_resume(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

223

int intel_ring_submission_setup(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

225

int intel_engine_stop_cs(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

226

void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

228

void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

230

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);

sys/dev/pci/drm/i915/gt/intel_engine.h

232

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

233

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

235

void intel_engine_get_instdone(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

238

void intel_engine_init_execlists(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

240

bool intel_engine_irq_enable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

241

void intel_engine_irq_disable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

243

static inline void __intel_engine_reset(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

246

if (engine->reset.rewind)

sys/dev/pci/drm/i915/gt/intel_engine.h

247

engine->reset.rewind(engine, stalled);

sys/dev/pci/drm/i915/gt/intel_engine.h

248

engine->serial++; /* contexts lost */

sys/dev/pci/drm/i915/gt/intel_engine.h

252

bool intel_engine_is_idle(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

254

void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);

sys/dev/pci/drm/i915/gt/intel_engine.h

255

static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

257

__intel_engine_flush_submission(engine, true);

sys/dev/pci/drm/i915/gt/intel_engine.h

262

bool intel_engine_can_store_dword(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

265

void intel_engine_dump(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

272

ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

275

void intel_engine_get_hung_entity(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

280

intel_engine_create_pinned_context(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

289

void xehp_enable_ccs_engines(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

295

static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

297

return engine->gt->submission_method >= INTEL_SUBMISSION_GUC;

sys/dev/pci/drm/i915/gt/intel_engine.h

301

intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

306

return intel_engine_has_preemption(engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

324

intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

332

GEM_BUG_ON(!intel_engine_uses_guc(engine));

sys/dev/pci/drm/i915/gt/intel_engine.h

334

return intel_guc_virtual_engine_has_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

338

intel_engine_has_heartbeat(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

343

if (intel_engine_is_virtual(engine))

sys/dev/pci/drm/i915/gt/intel_engine.h

344

return intel_virtual_engine_has_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine.h

346

return READ_ONCE(engine->props.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/intel_engine.h

350

intel_engine_get_sibling(struct intel_engine_cs *engine, unsigned int sibling)

sys/dev/pci/drm/i915/gt/intel_engine.h

352

GEM_BUG_ON(!intel_engine_is_virtual(engine));

sys/dev/pci/drm/i915/gt/intel_engine.h

353

return engine->cops->get_sibling(engine, sibling);

sys/dev/pci/drm/i915/gt/intel_engine.h

357

intel_engine_set_hung_context(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine.h

360

engine->hung_ce = ce;

sys/dev/pci/drm/i915/gt/intel_engine.h

364

intel_engine_clear_hung_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

366

intel_engine_set_hung_context(engine, NULL);

sys/dev/pci/drm/i915/gt/intel_engine.h

370

intel_engine_get_hung_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine.h

372

return engine->hung_ce;

sys/dev/pci/drm/i915/gt/intel_engine.h

375

u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

376

u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

377

u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

378

u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine.h

379

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1015

void intel_engine_init_execlists(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1017

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1028

static void cleanup_status_page(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1033

intel_engine_set_hwsp_writemask(engine, ~0u);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1035

vma = fetch_and_zero(&engine->status_page.vma);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1039

if (!HWS_NEEDS_PHYSICAL(engine->i915))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1046

static int pin_ggtt_status_page(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1052

if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1071

static int init_status_page(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1079

INIT_LIST_HEAD(&engine->status_page.timelines);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1088

obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1090

gt_err(engine->gt, "Failed to allocate status page\n");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1096

vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1105

if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1106

ret = pin_ggtt_status_page(engine, &ww, vma);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1116

engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1117

engine->status_page.vma = vma;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1135

static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1162

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1163

const unsigned int instance = engine->instance;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1164

const unsigned int class = engine->class;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1181

if (engine->gt->type == GT_MEDIA) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1205

if (gt_WARN_ONCE(engine->gt, !num,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1209

if (gt_WARN_ON_ONCE(engine->gt,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1233

engine->tlb_inv.mcr = regs == xehp_regs;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1234

engine->tlb_inv.reg = reg;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1235

engine->tlb_inv.done = val;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1238

(engine->class == VIDEO_DECODE_CLASS ||

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1239

engine->class == VIDEO_ENHANCEMENT_CLASS ||

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1240

engine->class == COMPUTE_CLASS ||

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1241

engine->class == OTHER_CLASS))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1242

engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1244

engine->tlb_inv.request = val;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1249

static int engine_setup_common(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1253

init_llist_head(&engine->barrier_tasks);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1255

err = intel_engine_init_tlb_invalidation(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1259

err = init_status_page(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1263

engine->breadcrumbs = intel_breadcrumbs_create(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1264

if (!engine->breadcrumbs) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1269

engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1270

if (!engine->sched_engine) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1274

engine->sched_engine->private_data = engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1276

err = intel_engine_init_cmd_parser(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1280

intel_engine_init_execlists(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1281

intel_engine_init__pm(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1282

intel_engine_init_retire(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1285

engine->sseu =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1286

intel_sseu_from_device_info(&engine->gt->info.sseu);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1288

intel_engine_init_workarounds(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1289

intel_engine_init_whitelist(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1290

intel_engine_init_ctx_wa(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1292

if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1293

engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1298

i915_sched_engine_put(engine->sched_engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1300

intel_breadcrumbs_put(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1302

cleanup_status_page(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1314

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1318

GEM_BUG_ON(!engine->gt->scratch);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1324

frame->rq.i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1325

frame->rq.engine = engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1339

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1341

dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1343

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1353

intel_engine_create_pinned_context(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1363

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1381

list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1396

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1397

struct i915_vma *hwsp = engine->status_page.vma;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1411

create_ggtt_bind_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1419

return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1425

create_kernel_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1429

return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1445

static int engine_init_common(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1450

engine->set_default_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1460

ce = create_kernel_context(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1469

if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1470

bce = create_ggtt_bind_context(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1481

engine->emit_fini_breadcrumb_dw = ret;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1482

engine->kernel_context = ce;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1483

engine->bind_context = bce;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1497

int (*setup)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1498

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1513

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1514

err = engine_setup_common(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1518

err = setup(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1520

intel_engine_cleanup_common(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1525

GEM_BUG_ON(engine->release == NULL);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1527

err = engine_init_common(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1531

intel_engine_add_user(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1544

void intel_engine_cleanup_common(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1546

GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1548

i915_sched_engine_put(engine->sched_engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1549

intel_breadcrumbs_put(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1551

intel_engine_fini_retire(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1552

intel_engine_cleanup_cmd_parser(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1554

if (engine->default_state)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1555

uao_detach(engine->default_state);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1557

if (engine->kernel_context)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1558

intel_engine_destroy_pinned_context(engine->kernel_context);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1560

if (engine->bind_context)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1561

intel_engine_destroy_pinned_context(engine->bind_context);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1564

GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1565

cleanup_status_page(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1567

intel_wa_list_free(&engine->ctx_wa_list);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1568

intel_wa_list_free(&engine->wa_list);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1569

intel_wa_list_free(&engine->whitelist);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1578

int intel_engine_resume(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1580

intel_engine_apply_workarounds(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1581

intel_engine_apply_whitelist(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1583

return engine->resume(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1586

u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1588

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1593

acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1595

acthd = ENGINE_READ(engine, RING_ACTHD);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1597

acthd = ENGINE_READ(engine, ACTHD);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1602

u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1606

if (GRAPHICS_VER(engine->i915) >= 8)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1607

bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1609

bbaddr = ENGINE_READ(engine, RING_BBADDR);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1614

static unsigned long stop_timeout(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1626

return READ_ONCE(engine->props.stop_timeout_ms);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1629

static int __intel_engine_stop_cs(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1633

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1634

const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1643

if (intel_engine_reset_needs_wa_22011802037(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1644

intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1647

err = __intel_wait_for_register_fw(engine->uncore, mode,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1658

int intel_engine_stop_cs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1662

if (GRAPHICS_VER(engine->i915) < 3)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1665

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1678

if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1679

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1681

ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1682

ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1689

if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1690

(ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1697

void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1699

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1701

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1704

static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1728

if (!_reg[engine->id].reg)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1731

val = intel_uncore_read(engine->uncore, _reg[engine->id]);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1765

void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1767

u32 fw_pending = __cs_pending_mi_force_wakes(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1770

__gpm_wait_for_fw_complete(engine->gt, fw_pending);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1774

void intel_engine_get_instdone(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1777

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1778

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1779

u32 mmio_base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1790

if (engine->id != RCS0)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1802

for_each_ss_steering(iter, engine->gt, slice, subslice) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1804

intel_gt_mcr_read(engine->gt,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1808

intel_gt_mcr_read(engine->gt,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1814

for_each_ss_steering(iter, engine->gt, slice, subslice)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1816

intel_gt_mcr_read(engine->gt,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1824

if (engine->id != RCS0)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1836

if (engine->id == RCS0)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1845

static bool ring_is_idle(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1849

if (I915_SELFTEST_ONLY(!engine->mmio_base))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1852

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1856

if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1857

(ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1861

if (GRAPHICS_VER(engine->i915) > 2 &&

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1862

!(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1865

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1870

void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1872

struct tasklet_struct *t = &engine->sched_engine->tasklet;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1898

bool intel_engine_is_idle(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1901

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1904

if (!intel_engine_pm_is_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1908

intel_synchronize_hardirq(engine->i915);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1909

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1912

if (!i915_sched_engine_is_empty(engine->sched_engine))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1916

return ring_is_idle(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1921

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1935

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1936

if (!intel_engine_is_idle(engine))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1943

bool intel_engine_irq_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1945

if (!engine->irq_enable)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1949

spin_lock(engine->gt->irq_lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1950

engine->irq_enable(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1951

spin_unlock(engine->gt->irq_lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1956

void intel_engine_irq_disable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1958

if (!engine->irq_disable)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1962

spin_lock(engine->gt->irq_lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1963

engine->irq_disable(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1964

spin_unlock(engine->gt->irq_lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1969

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1972

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1973

if (engine->sanitize)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1974

engine->sanitize(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1976

if (engine->set_default_submission)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1977

engine->set_default_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1981

bool intel_engine_can_store_dword(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1983

switch (GRAPHICS_VER(engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1988

return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1990

return !IS_I965G(engine->i915); /* who knows! */

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1992

return engine->class != VIDEO_DECODE_CLASS; /* b0rked */

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2084

static void intel_engine_print_registers(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2087

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2088

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2091

if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2092

drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2095

ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2097

ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2100

ENGINE_READ(engine, RING_START));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2102

ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2104

ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2106

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2107

ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2108

if (GRAPHICS_VER(engine->i915) > 2) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2110

ENGINE_READ(engine, RING_MI_MODE),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2111

ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2116

ENGINE_READ(engine, RING_IMR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2118

ENGINE_READ(engine, RING_ESR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2120

ENGINE_READ(engine, RING_EMR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2122

ENGINE_READ(engine, RING_EIR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2125

addr = intel_engine_get_active_head(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2128

addr = intel_engine_get_last_batch_head(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2132

addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2134

addr = ENGINE_READ(engine, RING_DMA_FADD);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2136

addr = ENGINE_READ(engine, DMA_FADD_I8XX);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2141

ENGINE_READ(engine, RING_IPEIR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2143

ENGINE_READ(engine, RING_IPEHR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2145

drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2146

drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2149

if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2152

&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2158

str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2159

str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2160

repr_timer(&engine->execlists.preempt),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2161

repr_timer(&engine->execlists.timer));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2167

ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2168

ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2183

i915_sched_engine_active_lock_bh(engine->sched_engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2214

i915_sched_engine_active_unlock_bh(engine->sched_engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2217

ENGINE_READ(engine, RING_PP_DIR_BASE));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2219

ENGINE_READ(engine, RING_PP_DIR_BASE_READ));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2221

ENGINE_READ(engine, RING_PP_DIR_DCLV));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2264

static void print_properties(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2272

.offset = offsetof(typeof(engine->props), x), \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2290

read_ul(&engine->props, p->offset),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2291

read_ul(&engine->defaults, p->offset));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2350

static void engine_dump_active_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2363

intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2372

if (intel_uc_uses_guc_submission(&engine->gt->uc))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2373

intel_guc_dump_active_requests(engine, hung_rq, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2375

intel_execlists_dump_active_requests(engine, hung_rq, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2381

void intel_engine_dump(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2385

struct i915_gpu_error * const error = &engine->i915->gpu_error;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2398

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2401

drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2403

str_yes_no(!llist_empty(&engine->barrier_tasks)));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2405

ewma__engine_latency_read(&engine->latency));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2406

if (intel_engine_supports_stats(engine))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2408

ktime_to_ms(intel_engine_get_busy_time(engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2411

engine->fw_domain, READ_ONCE(engine->fw_active));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2414

rq = READ_ONCE(engine->heartbeat.systole);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2420

i915_reset_engine_count(error, engine),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2422

print_properties(engine, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2424

engine_dump_active_requests(engine, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2426

drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2427

wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2429

intel_engine_print_registers(engine, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2430

intel_runtime_pm_put(engine->uncore->rpm, wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2435

intel_execlists_show_requests(engine, m, i915_request_show, 8);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2438

hexdump(m, engine->status_page.addr, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2440

drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2442

intel_engine_print_breadcrumbs(engine, m);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2452

ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2454

return engine->busyness(engine, now);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2471

static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2480

GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2493

lockdep_assert_held(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2496

request = execlists_active(&engine->execlists);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2511

list_for_each_entry(request, &engine->sched_engine->requests,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2523

void intel_engine_get_hung_entity(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2528

*ce = intel_engine_get_hung_context(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2530

intel_engine_clear_hung_context(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2540

if (intel_uc_uses_guc_submission(&engine->gt->uc))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2543

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2544

*rq = engine_execlist_find_hung_request(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2547

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2550

void xehp_enable_ccs_engines(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2560

if (!CCS_MASK(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2563

intel_uncore_write(engine->uncore, GEN12_RCU_MODE,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

358

static void __sprint_engine_name(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

365

GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

366

intel_engine_class_repr(engine->class),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

367

engine->instance) >= sizeof(engine->name));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

370

void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

376

if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

379

if (GRAPHICS_VER(engine->i915) >= 3)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

380

ENGINE_WRITE(engine, RING_HWSTAM, mask);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

382

ENGINE_WRITE16(engine, RING_HWSTAM, mask);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

385

static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

388

intel_engine_set_hwsp_writemask(engine, ~0u);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

391

static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

454

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

462

if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

474

engine = kzalloc(sizeof(*engine), GFP_KERNEL);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

475

if (!engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

478

BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

480

INIT_LIST_HEAD(&engine->pinned_contexts_list);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

481

engine->id = id;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

482

engine->legacy_idx = INVALID_ENGINE;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

483

engine->mask = BIT(id);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

484

engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

486

engine->i915 = i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

487

engine->gt = gt;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

488

engine->uncore = gt->uncore;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

490

engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

491

engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

493

engine->irq_handler = nop_irq_handler;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

495

engine->class = info->class;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

496

engine->instance = info->instance;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

497

engine->logical_mask = BIT(logical_instance);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

498

__sprint_engine_name(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

500

if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

501

__ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

502

engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

505

if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

506

engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

507

engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

510

engine->props.heartbeat_interval_ms =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

512

engine->props.max_busywait_duration_ns =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

514

engine->props.preempt_timeout_ms =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

516

engine->props.stop_timeout_ms =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

518

engine->props.timeslice_duration_ms =

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

527

if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

528

engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

533

u64 clamp = intel_clamp_##field(engine, engine->props.field); \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

534

if (clamp != engine->props.field) { \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

535

drm_notice(&engine->i915->drm, \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

538

engine->props.field = clamp; \

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

550

engine->defaults = engine->props; /* never to change again */

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

552

engine->context_size = intel_engine_context_size(gt, engine->class);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

553

if (WARN_ON(engine->context_size > BIT(20)))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

554

engine->context_size = 0;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

555

if (engine->context_size)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

558

ewma__engine_latency_init(&engine->latency);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

560

ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

563

intel_engine_sanitize_mmio(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

565

gt->engine_class[info->class][info->instance] = engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

566

gt->engine[id] = engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

571

u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

578

u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

585

u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

591

if (intel_guc_submission_is_wanted(gt_to_guc(engine->gt)))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

599

u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

606

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

612

if (intel_guc_submission_is_wanted(gt_to_guc(engine->gt)))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

620

static void __setup_engine_capabilities(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

622

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

624

if (engine->class == VIDEO_DECODE_CLASS) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

630

(GRAPHICS_VER(i915) >= 9 && engine->instance == 0))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

631

engine->uabi_capabilities |=

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

639

(engine->gt->info.vdbox_sfc_access &

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

640

BIT(engine->instance))) ||

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

641

(GRAPHICS_VER(i915) >= 9 && engine->instance == 0))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

642

engine->uabi_capabilities |=

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

644

} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

646

engine->gt->info.sfc_mask & BIT(engine->instance))

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

647

engine->uabi_capabilities |=

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

654

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

657

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

658

__setup_engine_capabilities(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

667

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

684

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

685

if (!engine->release)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

688

intel_wakeref_wait_for_idle(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

689

GEM_BUG_ON(intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

691

engine->release(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

692

engine->release = NULL;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

694

memset(&engine->reset, 0, sizeof(engine->reset));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

700

void intel_engine_free_request_pool(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

702

if (!engine->request_pool)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

706

kmem_cache_free(i915_request_slab_cache(), engine->request_pool);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

708

pool_put(i915_request_slab_cache(), engine->request_pool);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

714

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

720

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

721

intel_engine_free_request_pool(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

722

kfree(engine);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

723

gt->engine[id] = NULL;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

100

drm_dbg_printer(&engine->i915->drm, DRM_UT_DRIVER, "heartbeat");

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

103

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

105

engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

107

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

109

engine->name,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

117

reset_engine(struct intel_engine_cs *engine, struct i915_request *rq)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

120

show_heartbeat(rq, engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

122

if (intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

128

intel_guc_find_hung_context(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

130

intel_gt_handle_error(engine->gt, engine->mask,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

133

engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

139

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

140

container_of(wrk, typeof(*engine), heartbeat.work.work);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

141

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

146

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

148

rq = engine->heartbeat.systole;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

151

engine->heartbeat.systole = NULL;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

154

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

157

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

160

if (i915_sched_engine_disabled(engine->sched_engine)) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

161

reset_engine(engine, engine->heartbeat.systole);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

165

if (engine->heartbeat.systole) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

166

long delay = READ_ONCE(engine->props.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

184

} else if (engine->sched_engine->schedule &&

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

199

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

202

reset_engine(engine, rq);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

209

serial = READ_ONCE(engine->serial);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

210

if (engine->wakeref_serial == serial)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

215

if (xchg(&engine->heartbeat.blocked, serial) == serial)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

216

intel_gt_handle_error(engine->gt, engine->mask,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

219

engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

23

static bool next_heartbeat(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

232

if (!engine->i915->params.enable_hangcheck || !next_heartbeat(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

233

i915_request_put(fetch_and_zero(&engine->heartbeat.systole));

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

234

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

237

void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

242

next_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

245

void intel_engine_park_heartbeat(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

247

if (cancel_delayed_work(&engine->heartbeat.work))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

248

i915_request_put(fetch_and_zero(&engine->heartbeat.systole));

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

253

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

256

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

257

if (intel_engine_pm_is_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

258

intel_engine_unpark_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

263

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

266

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

267

intel_engine_park_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

270

void intel_engine_init_heartbeat(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

272

INIT_DELAYED_WORK(&engine->heartbeat.work, heartbeat);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

275

static int __intel_engine_pulse(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

278

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

28

delay = READ_ONCE(engine->props.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

282

GEM_BUG_ON(!intel_engine_has_preemption(engine));

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

283

GEM_BUG_ON(!intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

295

next_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

30

rq = engine->heartbeat.systole;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

300

static unsigned long set_heartbeat(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

305

old = xchg(&engine->props.heartbeat_interval_ms, delay);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

307

intel_engine_unpark_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

309

intel_engine_park_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

314

int intel_engine_set_heartbeat(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

317

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

320

if (!delay && !intel_engine_has_preempt_reset(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

324

if (delay != engine->defaults.heartbeat_interval_ms &&

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

325

delay < 2 * engine->props.preempt_timeout_ms) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

326

if (intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

327

drm_notice(&engine->i915->drm, "%s heartbeat interval adjusted to a non-default value which may downgrade individual engine resets to full GPU resets!\n",

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

328

engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

330

drm_notice(&engine->i915->drm, "%s heartbeat interval adjusted to a non-default value which may cause engine resets to target innocent contexts!\n",

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

331

engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

334

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

340

if (delay != engine->props.heartbeat_interval_ms) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

341

unsigned long saved = set_heartbeat(engine, delay);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

344

if (intel_engine_has_preemption(engine)) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

345

err = __intel_engine_pulse(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

347

set_heartbeat(engine, saved);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

354

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

358

int intel_engine_pulse(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

360

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

363

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

366

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

371

err = __intel_engine_pulse(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

375

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

376

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

380

int intel_engine_flush_barriers(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

383

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

387

if (llist_empty(&engine->barrier_tasks))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

390

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

410

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

42

delay == engine->defaults.heartbeat_interval_ms) {

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

50

longer = READ_ONCE(engine->props.preempt_timeout_ms) * 2;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

51

longer = intel_clamp_heartbeat_interval_ms(engine, longer);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

62

mod_delayed_work(system_highpri_wq, &engine->heartbeat.work, delay + 1);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

79

static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

81

engine->wakeref_serial = READ_ONCE(engine->serial) + 1;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

83

if (!engine->heartbeat.systole && intel_engine_has_heartbeat(engine))

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

84

engine->heartbeat.systole = i915_request_get(rq);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

90

idle_pulse(rq->engine, rq);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

97

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

12

void intel_engine_init_heartbeat(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

14

int intel_engine_set_heartbeat(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

17

void intel_engine_park_heartbeat(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

18

void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

23

int intel_engine_pulse(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.h

24

int intel_engine_flush_barriers(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

103

ewma__engine_latency_add(&rq->engine->latency,

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

111

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

113

struct intel_gt_timelines *timelines = &engine->gt->timelines;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

115

ENGINE_TRACE(engine, "parking\n");

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

124

__intel_gt_pm_get(engine->gt);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

125

rq->context->wakeref = intel_wakeref_track(&engine->gt->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

146

__intel_wakeref_defer_park(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

151

static bool switch_to_kernel_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

153

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

167

if (intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

171

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

175

GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

178

if (engine->wakeref_serial == engine->serial)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

20

static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

218

engine->wakeref_serial = engine->serial + 1;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

22

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

237

__queue_and_release_pm(rq, ce->timeline, engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

24

if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

245

static void call_idle_barriers(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

249

llist_for_each_safe(node, next, llist_del_all(&engine->barrier_tasks)) {

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

25

intel_uncore_write(engine->gt->uncore,

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

260

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

261

container_of(wf, typeof(*engine), wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

263

engine->saturated = 0;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

272

if (!switch_to_kernel_context(engine))

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

275

ENGINE_TRACE(engine, "parked\n");

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

277

call_idle_barriers(engine); /* cleanup after wedging */

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

279

intel_engine_park_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

280

intel_breadcrumbs_park(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

282

if (engine->park)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

283

engine->park(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

286

intel_gt_pm_put_async(engine->gt, engine->wakeref_track);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

29

intel_uncore_write(engine->gt->uncore,

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

295

void intel_engine_init__pm(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

297

intel_wakeref_init(&engine->wakeref, engine->i915, &wf_ops, engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

298

intel_engine_init_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

300

intel_gsc_idle_msg_enable(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

311

void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

315

list_for_each_entry(ce, &engine->pinned_contexts_list,

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

318

if (ce == engine->kernel_context)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

42

int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

60

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

61

container_of(wf, typeof(*engine), wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

64

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

66

engine->wakeref_track = intel_gt_pm_get(engine->gt);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

69

ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

75

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

91

if (engine->unpark)

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

92

engine->unpark(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

94

intel_breadcrumbs_unpark(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

95

intel_engine_unpark_heartbeat(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

101

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

102

rq = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

103

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

108

void intel_engine_init__pm(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

110

void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

17

intel_engine_pm_is_awake(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

19

return intel_wakeref_is_active(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

22

static inline void __intel_engine_pm_get(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

24

__intel_wakeref_get(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

27

static inline void intel_engine_pm_get(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

29

intel_wakeref_get(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

32

static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

34

return intel_wakeref_get_if_active(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

37

static inline void intel_engine_pm_might_get(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

39

if (!intel_engine_is_virtual(engine)) {

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

40

intel_wakeref_might_get(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

42

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

44

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

49

intel_gt_pm_might_get(engine->gt);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

52

static inline void intel_engine_pm_put(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

54

intel_wakeref_put(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

57

static inline void intel_engine_pm_put_async(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

59

intel_wakeref_put_async(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

62

static inline void intel_engine_pm_put_delay(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

65

intel_wakeref_put_delay(&engine->wakeref, delay);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

68

static inline void intel_engine_pm_flush(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

70

intel_wakeref_unlock_wait(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

73

static inline void intel_engine_pm_might_put(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

75

if (!intel_engine_is_virtual(engine)) {

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

76

intel_wakeref_might_put(&engine->wakeref);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

78

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

80

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

85

intel_gt_pm_might_put(engine->gt);

sys/dev/pci/drm/i915/gt/intel_engine_pm.h

89

intel_engine_create_kernel_request(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_stats.h

16

static inline void intel_engine_context_in(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_stats.h

18

struct intel_engine_execlists_stats *stats = &engine->stats.execlists;

sys/dev/pci/drm/i915/gt/intel_engine_stats.h

39

static inline void intel_engine_context_out(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_stats.h

41

struct intel_engine_execlists_stats *stats = &engine->stats.execlists;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

510

void (*irq_enable)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

511

void (*irq_disable)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

512

void (*irq_handler)(struct intel_engine_cs *engine, u16 iir);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

514

void (*sanitize)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

515

int (*resume)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

518

void (*prepare)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

520

void (*rewind)(struct intel_engine_cs *engine, bool stalled);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

521

void (*cancel)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

523

void (*finish)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

526

void (*park)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

527

void (*unpark)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

529

void (*bump_serial)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

531

void (*set_default_submission)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

559

void (*release)(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_engine_types.h

570

ktime_t (*busyness)(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_engine_types.h

659

intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

661

return engine->flags & I915_ENGINE_USING_CMD_PARSER;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

665

intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

667

return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

671

intel_engine_supports_stats(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

673

return engine->flags & I915_ENGINE_SUPPORTS_STATS;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

677

intel_engine_has_preemption(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

679

return engine->flags & I915_ENGINE_HAS_PREEMPTION;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

683

intel_engine_has_semaphores(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

685

return engine->flags & I915_ENGINE_HAS_SEMAPHORES;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

689

intel_engine_has_timeslices(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

694

return engine->flags & I915_ENGINE_HAS_TIMESLICES;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

698

intel_engine_is_virtual(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

700

return engine->flags & I915_ENGINE_IS_VIRTUAL;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

704

intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

706

return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;

sys/dev/pci/drm/i915/gt/intel_engine_types.h

713

intel_engine_uses_wa_hold_switchout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_types.h

715

return engine->flags & I915_ENGINE_USES_WA_HOLD_SWITCHOUT;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

107

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

112

for_each_uabi_engine(engine, i915) { /* all engines must agree! */

sys/dev/pci/drm/i915/gt/intel_engine_user.c

115

if (engine->sched_engine->schedule)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

122

if (intel_uc_uses_guc_submission(&engine->gt->uc))

sys/dev/pci/drm/i915/gt/intel_engine_user.c

126

if (engine->flags & BIT(map[i].engine))

sys/dev/pci/drm/i915/gt/intel_engine_user.c

142

u8 engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

151

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

156

for_each_uabi_engine(engine, i915) { /* all engines must agree! */

sys/dev/pci/drm/i915/gt/intel_engine_user.c

159

if (engine->sched_engine->schedule)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

166

if (intel_uc_uses_guc_submission(&engine->gt->uc))

sys/dev/pci/drm/i915/gt/intel_engine_user.c

170

if (engine->flags & map[i].engine)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

228

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

230

if (engine->gt != ring->gt || engine->class != ring->class) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

231

ring->gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

232

ring->class = engine->class;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

236

engine->legacy_idx = legacy_ring_idx(ring);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

237

if (engine->legacy_idx != INVALID_ENGINE)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

241

static void engine_rename(struct intel_engine_cs *engine, const char *name, u16 instance)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

243

char old[sizeof(engine->name)];

sys/dev/pci/drm/i915/gt/intel_engine_user.c

245

memcpy(old, engine->name, sizeof(engine->name));

sys/dev/pci/drm/i915/gt/intel_engine_user.c

246

scnprintf(engine->name, sizeof(engine->name), "%s%u", name, instance);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

247

drm_dbg(&engine->i915->drm, "renamed %s to %s\n", old, engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

263

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_engine_user.c

264

container_of(it, typeof(*engine), uabi_list);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

266

if (intel_gt_has_unrecoverable_error(engine->gt))

sys/dev/pci/drm/i915/gt/intel_engine_user.c

269

GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));

sys/dev/pci/drm/i915/gt/intel_engine_user.c

270

engine->uabi_class = uabi_classes[engine->class];

sys/dev/pci/drm/i915/gt/intel_engine_user.c

271

if (engine->uabi_class == I915_NO_UABI_CLASS) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

274

GEM_BUG_ON(engine->uabi_class >=

sys/dev/pci/drm/i915/gt/intel_engine_user.c

277

i915->engine_uabi_class_count[engine->uabi_class]++;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

279

engine->uabi_instance = name_instance;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

285

engine_rename(engine,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

286

intel_engine_class_repr(engine->class),

sys/dev/pci/drm/i915/gt/intel_engine_user.c

289

if (engine->uabi_class == I915_NO_UABI_CLASS)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

292

rb_link_node(&engine->uabi_node, prev, p);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

293

rb_insert_color(&engine->uabi_node, &i915->uabi_engines);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

296

engine->uabi_class,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

297

engine->uabi_instance) != engine);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

300

add_legacy_ring(&ring, engine);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

302

prev = &engine->uabi_node;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

308

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

315

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

317

if (!engine) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

324

if (engine->uabi_class != class ||

sys/dev/pci/drm/i915/gt/intel_engine_user.c

325

engine->uabi_instance != inst) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

327

engine->name,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

328

engine->uabi_class,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

329

engine->uabi_instance,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

342

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

343

unsigned int bit = BIT(engine->uabi_class);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

344

unsigned int expected = engine->default_state ? bit : 0;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

348

engine->uabi_class, engine->name);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

363

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.c

367

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

368

if (engine->default_state)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

369

which |= BIT(engine->uabi_class);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

39

void intel_engine_add_user(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_engine_user.c

41

llist_add(&engine->uabi_llist, &engine->i915->uabi_engines_llist);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

87

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_engine_user.c

88

container_of(pos, typeof(*engine), uabi_llist);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

89

list_add(&engine->uabi_list, engines);

sys/dev/pci/drm/i915/gt/intel_engine_user.c

98

u8 engine;

sys/dev/pci/drm/i915/gt/intel_engine_user.h

19

void intel_engine_add_user(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1003

if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1016

if (inflight && inflight != engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1023

first_virtual_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1025

struct intel_engine_execlists *el = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1030

rb_entry(rb, typeof(*ve), nodes[engine->id].rb);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1034

if (!rq || !virtual_matches(ve, rq, engine)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1048

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1052

if (likely(engine == ve->siblings[0]))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1056

if (!intel_engine_has_relative_mmio(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1057

lrc_update_offsets(&ve->context, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1066

if (ve->siblings[n] == engine) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1098

if (w->engine != rq->engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1121

static void defer_active(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1125

rq = __unwind_incomplete_requests(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1129

defer_request(rq, i915_sched_lookup_priolist(engine->sched_engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1152

static bool needs_timeslice(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1155

if (!intel_engine_has_timeslices(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1163

if (READ_ONCE(engine->execlists.pending[0]))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1168

&engine->sched_engine->requests)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1169

ENGINE_TRACE(engine, "timeslice required for second inflight context\n");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1174

if (!i915_sched_engine_is_empty(engine->sched_engine)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1175

ENGINE_TRACE(engine, "timeslice required for queue\n");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1179

if (!RB_EMPTY_ROOT(&engine->execlists.virtual.rb_root)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1180

ENGINE_TRACE(engine, "timeslice required for virtual\n");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1188

timeslice_expired(struct intel_engine_cs *engine, const struct i915_request *rq)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1190

const struct intel_engine_execlists *el = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1195

if (!needs_timeslice(engine, rq))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1201

static unsigned long timeslice(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1203

return READ_ONCE(engine->props.timeslice_duration_ms);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1206

static void start_timeslice(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1208

struct intel_engine_execlists *el = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1213

if (needs_timeslice(engine, *el->active)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1222

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1226

duration = timeslice(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1237

static unsigned long active_preempt_timeout(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1244

engine->execlists.preempt_target = rq;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1250

return READ_ONCE(engine->props.preempt_timeout_ms);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1253

static void set_preempt_timeout(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1256

if (!intel_engine_has_preempt_reset(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1259

set_timer_ms(&engine->execlists.preempt,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1260

active_preempt_timeout(engine, rq));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1271

static void execlists_dequeue(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1273

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1274

struct i915_sched_engine * const sched_engine = engine->sched_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1320

if (need_preempt(engine, last)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1321

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1334

ring_set_paused(engine, 1);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1343

__unwind_incomplete_requests(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1346

} else if (timeslice_expired(engine, last)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1347

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1372

ring_set_paused(engine, 1);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1373

defer_active(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1411

while ((ve = first_virtual_engine(engine))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1417

if (unlikely(!virtual_matches(ve, rq, engine)))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1420

GEM_BUG_ON(rq->engine != &ve->base);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1430

spin_unlock(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1434

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1441

str_yes_no(engine != ve->siblings[0]));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1446

rb = &ve->nodes[engine->id].rb;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1450

GEM_BUG_ON(!(rq->execution_mask & engine->mask));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1451

WRITE_ONCE(rq->engine, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1467

virtual_xfer_context(ve, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1468

GEM_BUG_ON(ve->siblings[0] != engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1533

if (rq->execution_mask != engine->mask)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1608

set_preempt_timeout(engine, *active);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1609

execlists_submit_ports(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1611

ring_set_paused(engine, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1618

static void execlists_dequeue_irq(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1621

execlists_dequeue(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1750

wa_csb_read(const struct intel_engine_cs *engine, u64 * const csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1765

int idx = csb - engine->execlists.csb_status;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1775

entry = intel_uncore_read64(engine->uncore,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1776

_MMIO(engine->mmio_base + status));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1783

static u64 csb_read(const struct intel_engine_cs *engine, u64 * const csb)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1799

entry = wa_csb_read(engine, csb);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1815

process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1817

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1828

GEM_BUG_ON(!tasklet_is_locked(&engine->sched_engine->tasklet) &&

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1829

!reset_in_progress(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1863

ENGINE_TRACE(engine, "cs-irq head=%d, tail=%d\n", head, tail);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1904

csb = csb_read(engine, buf + head);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1905

ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1908

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1910

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1922

ring_set_paused(engine, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1942

ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1970

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1972

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1974

ENGINE_READ(engine, RING_START),

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1975

ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1976

ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1977

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1978

ENGINE_READ(engine, RING_MI_MODE));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1979

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1986

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

205

static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2066

&rq->engine->sched_engine->hold);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

207

GEM_BUG_ON(!intel_engine_is_virtual(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2078

if (w->engine != rq->engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

208

return container_of(engine, struct virtual_engine, base);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2097

static bool execlists_hold(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2103

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2117

GEM_BUG_ON(rq->engine != engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2119

GEM_BUG_ON(list_empty(&engine->sched_engine->hold));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2122

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2140

if (s->engine != rq->engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2166

i915_sched_lookup_priolist(rq->engine->sched_engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2178

if (w->engine != rq->engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2195

static void execlists_unhold(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2198

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2206

if (rq_prio(rq) > engine->sched_engine->queue_priority_hint) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2207

engine->sched_engine->queue_priority_hint = rq_prio(rq);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2208

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2211

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2225

struct intel_engine_cs *engine = cap->rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2230

vma = intel_engine_coredump_add_request(gt->engine, cap->rq, gfp);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2235

intel_engine_coredump_add_vma(gt->engine, vma, compress);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2239

gt->simulated = gt->engine->simulated;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2247

execlists_unhold(engine, cap->rq);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2253

static struct execlists_capture *capture_regs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2262

cap->error = i915_gpu_coredump_alloc(engine->i915, gfp);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2266

cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp, CORE_DUMP_FLAG_NONE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2270

cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp, CORE_DUMP_FLAG_NONE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2271

if (!cap->error->gt->engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2274

cap->error->gt->engine->hung = true;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2288

active_context(struct intel_engine_cs *engine, u32 ccid)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2290

const struct intel_engine_execlists * const el = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2301

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2310

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2317

ENGINE_TRACE(engine, "ccid:%x not found\n", ccid);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2321

static u32 active_ccid(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2323

return ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2326

static void execlists_capture(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2328

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2339

cap = capture_regs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2343

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2344

cap->rq = active_context(engine, active_ccid(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2349

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2373

if (!execlists_hold(engine, cap->rq))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2387

static void execlists_reset(struct intel_engine_cs *engine, const char *msg)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2389

const unsigned int bit = I915_RESET_ENGINE + engine->id;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2390

unsigned long *lock = &engine->gt->reset.flags;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2392

if (!intel_has_reset_engine(engine->gt))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2398

ENGINE_TRACE(engine, "reset for %s\n", msg);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2401

tasklet_disable_nosync(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2403

ring_set_paused(engine, 1); /* Freeze the current request in place */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2404

execlists_capture(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2405

intel_engine_reset(engine, msg);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2407

tasklet_enable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2411

static bool preempt_timeout(const struct intel_engine_cs *const engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2413

const struct timeout *t = &engine->execlists.preempt;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

242

static void ring_set_paused(const struct intel_engine_cs *engine, int state)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2421

return engine->execlists.pending[0];

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2432

struct intel_engine_cs * const engine = sched_engine->private_data;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2437

inactive = process_csb(engine, post);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2440

if (unlikely(preempt_timeout(engine))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2441

const struct i915_request *rq = *engine->execlists.active;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2453

cancel_timer(&engine->execlists.preempt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2454

if (rq == engine->execlists.preempt_target)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2455

engine->execlists.error_interrupt |= ERROR_PREEMPT;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2457

set_timer_ms(&engine->execlists.preempt,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2458

active_preempt_timeout(engine, rq));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2461

if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2465

if (engine->execlists.error_interrupt & GENMASK(15, 0))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2467

else if (engine->execlists.error_interrupt & ERROR_CSB)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2469

else if (engine->execlists.error_interrupt & ERROR_PREEMPT)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2474

engine->execlists.error_interrupt = 0;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2475

execlists_reset(engine, msg);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2478

if (!engine->execlists.pending[0]) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2479

execlists_dequeue_irq(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2480

start_timeslice(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2487

static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2495

eir = ENGINE_READ(engine, RING_EIR) & GENMASK(15, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2496

ENGINE_TRACE(engine, "CS error: %x\n", eir);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

250

engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2500

ENGINE_WRITE(engine, RING_EMR, ~0u);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2501

ENGINE_WRITE(engine, RING_EIR, eir);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2502

WRITE_ONCE(engine->execlists.error_interrupt, eir);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2508

WRITE_ONCE(engine->execlists.yield,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2509

ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2510

ENGINE_TRACE(engine, "semaphore yield: %08x\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2511

engine->execlists.yield);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2512

if (timer_delete(&engine->execlists.timer))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2520

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2523

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2528

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2529

container_of(execlists, typeof(*engine), execlists);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2532

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2550

static void queue_request(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2555

i915_sched_lookup_priolist(engine->sched_engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2560

static bool submit_queue(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2563

struct i915_sched_engine *sched_engine = engine->sched_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2572

static bool ancestor_on_hold(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2576

return !list_empty(&engine->sched_engine->hold) && hold_request(rq);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2581

struct intel_engine_cs *engine = request->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2585

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2587

if (unlikely(ancestor_on_hold(engine, request))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2590

&engine->sched_engine->hold);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2593

queue_request(engine, request);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2595

GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2598

if (submit_queue(engine, request))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2599

__execlists_kick(&engine->execlists);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2602

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2607

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2612

err = lrc_pre_pin(ce, engine, ww, vaddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2617

lrc_init_state(ce, engine, *vaddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2619

__i915_gem_object_flush_map(ce->state->obj, 0, engine->context_size);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2629

return __execlists_context_pre_pin(ce, ce->engine, ww, vaddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2634

return lrc_pin(ce, ce->engine, vaddr);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2639

return lrc_alloc(ce, ce->engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2645

struct intel_engine_cs *engine = NULL;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2647

i915_request_active_engine(rq, &engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2649

if (engine && intel_engine_pulse(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2650

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2716

const struct intel_engine_cs * const engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2739

err = engine->emit_flush(rq, EMIT_FLUSH);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2744

err = engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2756

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2799

ret = request->engine->emit_flush(request, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2807

static void reset_csb_pointers(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2809

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2812

ring_set_paused(engine, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2818

ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2820

ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2842

ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2844

ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2849

static void sanitize_hwsp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2853

list_for_each_entry(tl, &engine->status_page.timelines, engine_link)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2857

static void execlists_sanitize(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2859

GEM_BUG_ON(execlists_active(&engine->execlists));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2871

memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2873

reset_csb_pointers(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2880

sanitize_hwsp(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2883

drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2885

intel_engine_reset_pinned_contexts(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2888

static void enable_error_interrupt(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2892

engine->execlists.error_interrupt = 0;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2893

ENGINE_WRITE(engine, RING_EMR, ~0u);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2894

ENGINE_WRITE(engine, RING_EIR, ~0u); /* clear all existing errors */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2896

status = ENGINE_READ(engine, RING_ESR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2898

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2900

engine->name, status);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2901

intel_gt_reset_engine(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2928

ENGINE_WRITE(engine, RING_EMR, ~I915_ERROR_INSTRUCTION);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2931

static void enable_execlists(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2935

assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2937

intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2939

if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2943

ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2945

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2947

ENGINE_WRITE_FW(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2949

i915_ggtt_offset(engine->status_page.vma));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2950

ENGINE_POSTING_READ(engine, RING_HWS_PGA);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2952

enable_error_interrupt(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2955

static int execlists_resume(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2957

intel_mocs_init_engine(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2958

intel_breadcrumbs_reset(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2960

enable_execlists(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2962

if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2963

xehp_enable_ccs_engines(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2968

static void execlists_reset_prepare(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2970

ENGINE_TRACE(engine, "depth<-%d\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2971

atomic_read(&engine->sched_engine->tasklet.count));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2982

__tasklet_disable_sync_once(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2983

GEM_BUG_ON(!reset_in_progress(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2997

ring_set_paused(engine, 1);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2998

intel_engine_stop_cs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3004

if (intel_engine_reset_needs_wa_22011802037(engine->gt))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3005

intel_engine_wait_for_pending_mi_fw(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3007

engine->execlists.reset_ccid = active_ccid(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

301

static bool need_preempt(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3011

reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3013

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3018

inactive = process_csb(engine, inactive); /* drain preemption events */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3021

reset_csb_pointers(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3027

execlists_reset_active(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3038

rq = active_context(engine, engine->execlists.reset_ccid);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3052

GEM_BUG_ON(!intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

306

if (!intel_engine_has_semaphores(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3098

ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3100

lrc_reset_regs(ce, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3101

ce->lrc.lrca = lrc_update_regs(ce, engine, head);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3104

static void execlists_reset_csb(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3106

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3111

inactive = reset_csb(engine, post);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3113

execlists_reset_active(engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3120

static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3124

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3127

execlists_reset_csb(engine, stalled);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3131

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3132

__unwind_incomplete_requests(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3133

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3141

struct intel_engine_cs * const engine = sched_engine->private_data;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3144

WRITE_ONCE(engine->sched_engine->queue_priority_hint, INT_MIN);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3147

static void execlists_reset_cancel(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3149

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3150

struct i915_sched_engine * const sched_engine = engine->sched_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3155

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3171

execlists_reset_csb(engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3174

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3177

list_for_each_entry(rq, &engine->sched_engine->requests, sched.link)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3179

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3203

rb_entry(rb, typeof(*ve), nodes[engine->id].rb);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3212

rq->engine = engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3228

GEM_BUG_ON(__tasklet_is_enabled(&engine->sched_engine->tasklet));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3229

engine->sched_engine->tasklet.callback = nop_submission_tasklet;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3231

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3235

static void execlists_reset_finish(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3237

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3249

GEM_BUG_ON(!reset_in_progress(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3252

if (__tasklet_enable(&engine->sched_engine->tasklet))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3255

ENGINE_TRACE(engine, "depth->%d\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3256

atomic_read(&engine->sched_engine->tasklet.count));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3259

static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3261

ENGINE_WRITE(engine, RING_IMR,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3262

~(engine->irq_enable_mask | engine->irq_keep_mask));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3263

ENGINE_POSTING_READ(engine, RING_IMR);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3266

static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3268

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3271

static void execlists_park(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3273

cancel_timer(&engine->execlists.timer);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3274

cancel_timer(&engine->execlists.preempt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3277

WRITE_ONCE(engine->sched_engine->queue_priority_hint, INT_MIN);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

328

if (engine->sched_engine->queue_priority_hint <= last_prio)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3282

lockdep_assert_held(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3283

list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3288

struct intel_engine_cs *engine, *locked;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3296

locked = READ_ONCE(rq->engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3298

while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3300

spin_lock(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3301

locked = engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3316

static bool can_preempt(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3318

return GRAPHICS_VER(engine->i915) > 8;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3323

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3324

struct i915_sched_engine *sched_engine = engine->sched_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3337

inflight = execlists_active(&engine->execlists);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3348

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

335

if (!list_is_last(&rq->sched.link, &engine->sched_engine->requests) &&

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3371

static void execlists_set_default_submission(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3373

engine->submit_request = execlists_submit_request;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3374

engine->sched_engine->schedule = i915_schedule;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3375

engine->sched_engine->kick_backend = kick_execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3376

engine->sched_engine->tasklet.callback = execlists_submission_tasklet;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3379

static void execlists_shutdown(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3382

timer_delete_sync(&engine->execlists.timer);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3383

timer_delete_sync(&engine->execlists.preempt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3384

tasklet_kill(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3387

static void execlists_release(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3389

engine->sanitize = NULL; /* no longer in control, nothing to sanitize */

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3391

execlists_shutdown(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3393

intel_engine_cleanup_common(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3394

lrc_fini_wa_ctx(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3397

static ktime_t __execlists_engine_busyness(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3400

struct intel_engine_execlists_stats *stats = &engine->stats.execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3414

static ktime_t execlists_engine_busyness(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3417

struct intel_engine_execlists_stats *stats = &engine->stats.execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3423

total = __execlists_engine_busyness(engine, now);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3430

logical_ring_default_vfuncs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3434

engine->resume = execlists_resume;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3436

engine->cops = &execlists_context_ops;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3437

engine->request_alloc = execlists_request_alloc;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3438

engine->add_active_request = add_to_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3439

engine->remove_active_request = remove_from_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3441

engine->reset.prepare = execlists_reset_prepare;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3442

engine->reset.rewind = execlists_reset_rewind;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3443

engine->reset.cancel = execlists_reset_cancel;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3444

engine->reset.finish = execlists_reset_finish;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3446

engine->park = execlists_park;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3447

engine->unpark = NULL;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3449

engine->emit_flush = gen8_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3450

engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3451

engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3452

if (GRAPHICS_VER(engine->i915) >= 12) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3453

engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3454

engine->emit_flush = gen12_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3456

engine->set_default_submission = execlists_set_default_submission;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3458

if (GRAPHICS_VER(engine->i915) < 11) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3459

engine->irq_enable = gen8_logical_ring_enable_irq;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3460

engine->irq_disable = gen8_logical_ring_disable_irq;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3469

intel_engine_set_irq_handler(engine, execlists_irq_handler);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3471

engine->flags |= I915_ENGINE_SUPPORTS_STATS;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3472

if (!intel_vgpu_active(engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3473

engine->flags |= I915_ENGINE_HAS_SEMAPHORES;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3474

if (can_preempt(engine)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3475

engine->flags |= I915_ENGINE_HAS_PREEMPTION;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3477

engine->flags |= I915_ENGINE_HAS_TIMESLICES;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3481

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3482

if (intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3483

engine->emit_bb_start = xehp_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3485

engine->emit_bb_start = xehp_emit_bb_start_noarb;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3487

if (intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3488

engine->emit_bb_start = gen8_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

349

return max(virtual_prio(&engine->execlists),

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3490

engine->emit_bb_start = gen8_emit_bb_start_noarb;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3493

engine->busyness = execlists_engine_busyness;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3496

static void logical_ring_default_irqs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

350

queue_prio(engine->sched_engine)) > last_prio;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3500

if (GRAPHICS_VER(engine->i915) < 11) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3509

shift = irq_shifts[engine->id];

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3512

engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3513

engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3514

engine->irq_keep_mask |= GT_CS_MASTER_ERROR_INTERRUPT << shift;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3515

engine->irq_keep_mask |= GT_WAIT_SEMAPHORE_INTERRUPT << shift;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3518

static void rcs_submission_override(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3520

switch (GRAPHICS_VER(engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3522

engine->emit_flush = gen12_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3523

engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3526

engine->emit_flush = gen11_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3527

engine->emit_fini_breadcrumb = gen11_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3530

engine->emit_flush = gen8_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3531

engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3536

int intel_execlists_submission_setup(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3538

struct intel_engine_execlists * const execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3539

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3540

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3541

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3543

tasklet_setup(&engine->sched_engine->tasklet, execlists_submission_tasklet);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3545

timer_setup(&engine->execlists.timer, execlists_timeslice, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3546

timer_setup(&engine->execlists.preempt, execlists_preempt, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3548

timeout_set(&engine->execlists.timer, execlists_timeslice,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3549

&engine->execlists.timer);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3550

timeout_set(&engine->execlists.preempt, execlists_preempt,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3551

&engine->execlists.preempt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3554

logical_ring_default_vfuncs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3555

logical_ring_default_irqs(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3557

seqcount_init(&engine->stats.execlists.lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3559

if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3560

rcs_submission_override(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3562

lrc_init_wa_ctx(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3570

engine->fw_domain = intel_uncore_forcewake_for_reg(engine->uncore,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3571

RING_EXECLIST_CONTROL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3579

(u64 *)&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3582

&engine->status_page.addr[INTEL_HWS_CSB_WRITE_INDEX(i915)];

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3589

engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3590

if (GRAPHICS_VER(engine->i915) >= 11 &&

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3591

GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3592

execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3593

execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3597

engine->sanitize = execlists_sanitize;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3598

engine->release = execlists_release;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3690

queue_rcu_work(ve->context.engine->i915->unordered_wq, &ve->rcu);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

371

__unwind_incomplete_requests(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3762

virtual_get_sibling(struct intel_engine_cs *engine, unsigned int sibling)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3764

struct virtual_engine *ve = to_virtual_engine(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

377

lockdep_assert_held(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

380

&engine->sched_engine->requests,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3903

struct virtual_engine *ve = to_virtual_engine(rq->engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

392

pl = i915_sched_lookup_priolist(engine->sched_engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

395

GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4083

void intel_execlists_show_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4091

const struct intel_engine_execlists *execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4092

struct i915_sched_engine *sched_engine = engine->sched_engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4146

rb_entry(rb, typeof(*ve), nodes[engine->id].rb);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4168

void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4174

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4176

intel_engine_dump_active_requests(&engine->sched_engine->requests, hung_rq, m);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4179

list_count_nodes(&engine->sched_engine->hold));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4181

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

424

atomic_notifier_call_chain(&rq->engine->context_status_notifier,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

430

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

450

ENGINE_TRACE(engine, "{ reset rq=%llx:%lld }\n",

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

461

lrc_init_regs(ce, engine, true);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

464

ce->lrc.lrca = lrc_update_regs(ce, engine, head);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

475

struct intel_engine_cs * const engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

481

!intel_engine_has_heartbeat(engine)))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

485

reset_active(rq, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

488

lrc_check_regs(ce, engine, "before");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

494

} else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

496

unsigned int tag = ffs(READ_ONCE(engine->context_tag));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

499

clear_bit(tag - 1, &engine->context_tag);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

506

unsigned int tag = __ffs(engine->context_tag);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

509

__clear_bit(tag, &engine->context_tag);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

515

ce->lrc.ccid |= engine->execlists.ccid;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

517

__intel_gt_pm_get(engine->gt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

518

if (engine->fw_domain && !engine->fw_active++)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

519

intel_uncore_forcewake_get(engine->uncore, engine->fw_domain);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

521

intel_engine_context_in(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

525

return engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

533

GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

541

GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

547

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

549

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

552

WRITE_ONCE(rq->engine, &ve->base);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

555

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

561

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

571

intel_context_remove_breadcrumbs(ce, engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

580

rq->execution_mask != engine->mask)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

590

struct intel_engine_cs * const engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

600

GEM_BUG_ON(ce->inflight != engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

603

lrc_check_regs(ce, engine, "after");

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

611

intel_engine_add_retire(engine, ce->timeline);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

614

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

624

GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

625

__set_bit(ccid - 1, &engine->context_tag);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

627

intel_engine_context_out(engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

629

if (engine->fw_domain && !--engine->fw_active)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

630

intel_uncore_forcewake_put(engine->uncore, engine->fw_domain);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

631

intel_gt_pm_put_async_untracked(engine->gt);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

642

if (ce->engine != engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

680

if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

758

const struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

759

container_of(execlists, typeof(*engine), execlists);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

765

ENGINE_TRACE(engine, "%s { %s%s }\n", msg,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

771

reset_in_progress(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

773

return unlikely(!__tasklet_is_enabled(&engine->sched_engine->tasklet));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

780

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

781

container_of(execlists, typeof(*engine), execlists);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

789

if (reset_in_progress(engine))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

794

engine->name);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

800

engine->name, execlists_num_ports(execlists));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

813

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

822

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

841

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

853

if (rq->execution_mask != engine->mask &&

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

856

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

872

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

881

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

890

engine->name,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

906

static void execlists_submit_ports(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

908

struct intel_engine_execlists *execlists = &engine->execlists;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

921

GEM_BUG_ON(!intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

996

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.h

25

int intel_execlists_submission_setup(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.h

27

void intel_execlists_show_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.h

35

void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.h

40

intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

345

ce = gt->engine[BCS0]->bind_context;

sys/dev/pci/drm/i915/gt/intel_ggtt.c

358

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

365

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/gt/intel_ggtt.c

366

intel_gt_pm_put(ce->engine->gt, wakeref);

sys/dev/pci/drm/i915/gt/intel_gpu_commands.h

121

#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)

sys/dev/pci/drm/i915/gt/intel_gt.c

1128

struct intel_engine_cs *engine = gt->engine[BCS0];

sys/dev/pci/drm/i915/gt/intel_gt.c

1130

if (engine && engine->bind_context)

sys/dev/pci/drm/i915/gt/intel_gt.c

1131

engine->bind_context_ready = ready;

sys/dev/pci/drm/i915/gt/intel_gt.c

1167

struct intel_engine_cs *engine = gt->engine[BCS0];

sys/dev/pci/drm/i915/gt/intel_gt.c

1169

if (engine)

sys/dev/pci/drm/i915/gt/intel_gt.c

1170

return engine->bind_context_ready;

sys/dev/pci/drm/i915/gt/intel_gt.c

226

static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_gt.c

228

GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);

sys/dev/pci/drm/i915/gt/intel_gt.c

229

GEN6_RING_FAULT_REG_POSTING_READ(engine);

sys/dev/pci/drm/i915/gt/intel_gt.c

293

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt.c

296

for_each_engine_masked(engine, gt, engine_mask, id)

sys/dev/pci/drm/i915/gt/intel_gt.c

297

gen6_clear_engine_error_register(engine);

sys/dev/pci/drm/i915/gt/intel_gt.c

303

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt.c

306

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt.c

309

fault = GEN6_RING_FAULT_REG_READ(engine);

sys/dev/pci/drm/i915/gt/intel_gt.c

517

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt.c

530

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt.c

536

GEM_BUG_ON(!engine->kernel_context);

sys/dev/pci/drm/i915/gt/intel_gt.c

538

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/intel_gt.c

607

rq->engine->default_state = state;

sys/dev/pci/drm/i915/gt/intel_gt.c

636

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt.c

643

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt.c

644

if (intel_engine_verify_workarounds(engine, "load"))

sys/dev/pci/drm/i915/gt/intel_gt.h

189

for_each_if ((engine__) = (gt__)->engine[(id__)])

sys/dev/pci/drm/i915/gt/intel_gt.h

195

((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \

sys/dev/pci/drm/i915/gt/intel_gt.h

93

#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \

sys/dev/pci/drm/i915/gt/intel_gt.h

94

intel_gt_needs_wa_16018031267(engine->gt) && \

sys/dev/pci/drm/i915/gt/intel_gt.h

95

engine->class == COPY_ENGINE_CLASS && engine->instance == 0)

sys/dev/pci/drm/i915/gt/intel_gt_engines_debugfs.c

19

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt_engines_debugfs.c

24

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_gt_engines_debugfs.c

25

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

136

struct intel_engine_cs *engine = gt->engine_class[class][instance];

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

137

if (engine)

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

138

return intel_engine_cs_irq(engine, intr);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

44

static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir)

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

47

engine->irq_handler(engine, iir);

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

51

intel_engine_set_irq_handler(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

52

void (*fn)(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_gt_irq.h

62

smp_store_mb(engine->irq_handler, fn);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

187

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

211

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

212

if (engine->reset.prepare)

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

213

engine->reset.prepare(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

215

if (engine->sanitize)

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

216

engine->sanitize(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

220

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

221

__intel_engine_reset(engine, false);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

226

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

227

if (engine->reset.finish)

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

228

engine->reset.finish(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

258

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

298

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

299

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

301

engine->serial++; /* kernel context lost */

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

302

err = intel_engine_resume(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

304

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_gt_pm.c

307

engine->name, err);

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

321

#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

104

first = READ_ONCE(engine->retire);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

107

while (!try_cmpxchg(&engine->retire, &first, tl));

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

112

void intel_engine_add_retire(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

116

GEM_BUG_ON(intel_engine_is_virtual(engine));

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

118

if (add_retire(engine, tl))

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

119

queue_work(engine->i915->unordered_wq, &engine->retire_work);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

122

void intel_engine_init_retire(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

124

INIT_WORK(&engine->retire_work, engine_retire);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

127

void intel_engine_fini_retire(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

129

flush_work(&engine->retire_work);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

130

GEM_BUG_ON(engine->retire);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

29

static bool engine_active(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

31

return !list_empty(&engine->kernel_context->timeline->requests);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

36

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

46

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

47

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

50

flush_work(&engine->retire_work);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

51

flush_delayed_work(&engine->wakeref.work);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

54

active |= engine_active(engine);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

62

struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

63

container_of(work, typeof(*engine), retire_work);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

64

struct intel_timeline *tl = xchg(&engine->retire, NULL);

sys/dev/pci/drm/i915/gt/intel_gt_requests.c

88

static bool add_retire(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_gt_requests.h

22

void intel_engine_init_retire(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_gt_requests.h

23

void intel_engine_add_retire(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_gt_requests.h

25

void intel_engine_fini_retire(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_gt_types.h

205

struct intel_engine_cs *engine[I915_NUM_ENGINES];

sys/dev/pci/drm/i915/gt/intel_lrc.c

101

if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1015

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1020

set_redzone(state, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1024

shmem_read(ce->default_state, 0, state, engine->context_size);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1026

uao_read(ce->default_state, 0, state, engine->context_size);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1043

__lrc_init_regs(state + LRC_STATE_OFFSET, ce, engine, inhibit);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1076

__lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1082

context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1087

if (GRAPHICS_VER(engine->i915) >= 12) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1093

if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1098

obj = i915_gem_object_create_lmem(engine->i915, context_size,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1101

obj = i915_gem_object_create_shmem(engine->i915, context_size);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1110

if (intel_gt_needs_wa_22016122933(engine->gt))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1114

vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1124

pinned_timeline(struct intel_context *ce, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1128

return intel_timeline_create_from_engine(engine, page_unmask_bits(tl));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1131

int lrc_alloc(struct intel_context *ce, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1140

ce->default_state = engine->default_state;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1142

vma = __lrc_alloc_state(ce, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1146

ring = intel_engine_create_ring(engine, ce->ring_size);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1160

tl = pinned_timeline(ce, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1162

tl = intel_timeline_create(engine->gt);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1190

lrc_init_regs(ce, ce->engine, true);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1191

ce->lrc.lrca = lrc_update_regs(ce, ce->engine, ce->ring->tail);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1196

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1204

intel_gt_coherent_map_type(ce->engine->gt,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1214

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1220

lrc_init_state(ce, engine, vaddr);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1222

ce->lrc.lrca = lrc_update_regs(ce, engine, ce->ring->tail);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1233

ce->engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1292

GEM_BUG_ON(lrc_ring_gpr0(ce->engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1299

(lrc_ring_gpr0(ce->engine) + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1308

GEM_BUG_ON(lrc_ring_cmd_buf_cctl(ce->engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1315

(lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1361

if (IS_DG2_G11(ce->engine->i915))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1364

cs = gen12_emit_aux_table_inv(ce->engine, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1367

if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1371

if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

sys/dev/pci/drm/i915/gt/intel_lrc.c

1372

IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||

sys/dev/pci/drm/i915/gt/intel_lrc.c

1373

IS_DG2(ce->engine->i915))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1386

if (IS_DG2_G11(ce->engine->i915))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1387

if (ce->engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1392

return gen12_emit_aux_table_inv(ce->engine, cs);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1397

struct intel_gt *gt = ce->engine->gt;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1443

if (NEEDS_FASTCOLOR_BLT_WABB(ce->engine))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1451

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1464

lrc_setup_bb_per_ctx(ce->lrc_reg_state, engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1470

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1484

lrc_setup_indirect_ctx(ce->lrc_reg_state, engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1540

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1555

if (engine->class == RENDER_CLASS) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1557

intel_sseu_make_rpcs(engine->gt, &ce->sseu);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1559

i915_oa_init_reg_state(ce, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1566

if (ce->engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1570

GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1571

setup_indirect_ctx_bb(ce, engine, fn);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1572

setup_per_ctx_bb(ce, engine, xehp_emit_per_ctx_bb);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1579

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1581

set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1585

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1595

engine->name,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1605

engine->name,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1612

x = lrc_ring_mi_mode(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1615

engine->name, regs[x + 1]);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1641

gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1646

*batch++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1661

*batch++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1683

static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1689

if (IS_BROADWELL(engine->i915))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1690

batch = gen8_emit_flush_coherentl3_wa(engine, batch);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1735

static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1763

batch = gen8_emit_flush_coherentl3_wa(engine, batch);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1776

if (HAS_POOLED_EU(engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1809

static int lrc_create_wa_ctx(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1815

obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_SIZE);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1819

vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1825

engine->wa_ctx.vma = vma;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1833

void lrc_fini_wa_ctx(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1835

i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1838

typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1840

void lrc_init_wa_ctx(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1842

struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;

sys/dev/pci/drm/i915/gt/intel_lrc.c

1852

if (GRAPHICS_VER(engine->i915) >= 11 ||

sys/dev/pci/drm/i915/gt/intel_lrc.c

1853

!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))

sys/dev/pci/drm/i915/gt/intel_lrc.c

1856

if (GRAPHICS_VER(engine->i915) == 9) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1859

} else if (GRAPHICS_VER(engine->i915) == 8) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

1864

err = lrc_create_wa_ctx(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1871

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/gt/intel_lrc.c

1877

if (!engine->wa_ctx.vma)

sys/dev/pci/drm/i915/gt/intel_lrc.c

1908

batch_ptr = wa_bb_fn[i](engine, batch_ptr);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1918

err = i915_inject_probe_error(engine->i915, -ENODEV);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1932

i915_vma_put(engine->wa_ctx.vma);

sys/dev/pci/drm/i915/gt/intel_lrc.c

49

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

60

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_lrc.c

641

static const u8 *reg_offsets(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

649

GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&

sys/dev/pci/drm/i915/gt/intel_lrc.c

650

!intel_engine_has_relative_mmio(engine));

sys/dev/pci/drm/i915/gt/intel_lrc.c

652

if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

653

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))

sys/dev/pci/drm/i915/gt/intel_lrc.c

655

else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

657

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

659

else if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

661

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

666

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

668

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

670

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

677

static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

679

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

681

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

683

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

685

else if (engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

691

static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

693

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

695

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

697

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

699

else if (GRAPHICS_VER(engine->i915) >= 8 &&

sys/dev/pci/drm/i915/gt/intel_lrc.c

700

engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

706

static int lrc_ring_gpr0(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

708

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

710

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

712

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

714

else if (engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

720

static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

722

if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

724

else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

730

static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

734

x = lrc_ring_wa_bb_per_ctx(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

741

static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

745

x = lrc_ring_indirect_ptr(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

752

static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

754

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_lrc.c

760

else if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_lrc.c

762

else if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

764

else if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

771

lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

773

if (GRAPHICS_VER(engine->i915) >= 12)

sys/dev/pci/drm/i915/gt/intel_lrc.c

775

else if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

777

else if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gt/intel_lrc.c

779

else if (GRAPHICS_VER(engine->i915) >= 8)

sys/dev/pci/drm/i915/gt/intel_lrc.c

78

if (GRAPHICS_VER(engine->i915) >= 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

782

GEM_BUG_ON(GRAPHICS_VER(engine->i915) < 8);

sys/dev/pci/drm/i915/gt/intel_lrc.c

789

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

792

GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

793

regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =

sys/dev/pci/drm/i915/gt/intel_lrc.c

801

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

807

GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

808

regs[lrc_ring_indirect_ptr(engine) + 1] =

sys/dev/pci/drm/i915/gt/intel_lrc.c

811

GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

812

regs[lrc_ring_indirect_offset(engine) + 1] =

sys/dev/pci/drm/i915/gt/intel_lrc.c

813

lrc_ring_indirect_offset_default(engine) << 6;

sys/dev/pci/drm/i915/gt/intel_lrc.c

827

if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&

sys/dev/pci/drm/i915/gt/intel_lrc.c

828

(ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {

sys/dev/pci/drm/i915/gt/intel_lrc.c

841

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

851

if (GRAPHICS_VER(engine->i915) < 11)

sys/dev/pci/drm/i915/gt/intel_lrc.c

861

loc = lrc_ring_bb_offset(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

867

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

869

const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;

sys/dev/pci/drm/i915/gt/intel_lrc.c

874

GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);

sys/dev/pci/drm/i915/gt/intel_lrc.c

875

regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =

sys/dev/pci/drm/i915/gt/intel_lrc.c

880

lrc_setup_indirect_ctx(regs, engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

911

static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

915

x = lrc_ring_mi_mode(engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

924

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

941

set_offsets(regs, reg_offsets(engine), engine, inhibit);

sys/dev/pci/drm/i915/gt/intel_lrc.c

943

init_common_regs(regs, ce, engine, inhibit);

sys/dev/pci/drm/i915/gt/intel_lrc.c

946

init_wa_bb_regs(regs, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

948

__reset_stop_ring(regs, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

952

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.c

955

__lrc_init_regs(ce->lrc_reg_state, ce, engine, inhibit);

sys/dev/pci/drm/i915/gt/intel_lrc.c

959

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

961

__reset_stop_ring(ce->lrc_reg_state, engine);

sys/dev/pci/drm/i915/gt/intel_lrc.c

965

set_redzone(void *vaddr, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

970

vaddr += engine->context_size;

sys/dev/pci/drm/i915/gt/intel_lrc.c

976

check_redzone(const void *vaddr, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_lrc.c

981

vaddr += engine->context_size;

sys/dev/pci/drm/i915/gt/intel_lrc.c

984

drm_err_once(&engine->i915->drm,

sys/dev/pci/drm/i915/gt/intel_lrc.c

986

engine->name);

sys/dev/pci/drm/i915/gt/intel_lrc.h

33

void lrc_init_wa_ctx(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_lrc.h

34

void lrc_fini_wa_ctx(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_lrc.h

37

struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_lrc.h

44

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.h

49

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.h

55

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.h

59

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.h

62

const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_lrc.h

65

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_lrc.h

68

struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_lrc.h

71

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_migrate.c

1021

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/intel_migrate.c

1022

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/intel_migrate.c

1041

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

1060

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

162

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

168

engine = gt->engine_class[COPY_ENGINE_CLASS][i];

sys/dev/pci/drm/i915/gt/intel_migrate.c

169

if (!engine_supports_migration(engine))

sys/dev/pci/drm/i915/gt/intel_migrate.c

23

static bool engine_supports_migration(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_migrate.c

233

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

237

engine = gt->engine_class[COPY_ENGINE_CLASS][i];

sys/dev/pci/drm/i915/gt/intel_migrate.c

238

if (engine_supports_migration(engine))

sys/dev/pci/drm/i915/gt/intel_migrate.c

239

return engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

248

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

25

if (!engine)

sys/dev/pci/drm/i915/gt/intel_migrate.c

252

engine = first_copy_engine(gt);

sys/dev/pci/drm/i915/gt/intel_migrate.c

253

if (!engine)

sys/dev/pci/drm/i915/gt/intel_migrate.c

260

ce = intel_engine_create_pinned_context(engine, vm, SZ_512K,

sys/dev/pci/drm/i915/gt/intel_migrate.c

289

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

294

engine = gt->engine_class[COPY_ENGINE_CLASS][i];

sys/dev/pci/drm/i915/gt/intel_migrate.c

295

if (engine_supports_migration(engine))

sys/dev/pci/drm/i915/gt/intel_migrate.c

296

engines[count++] = engine;

sys/dev/pci/drm/i915/gt/intel_migrate.c

314

ce = __migrate_engines(m->context->engine->gt);

sys/dev/pci/drm/i915/gt/intel_migrate.c

33

GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);

sys/dev/pci/drm/i915/gt/intel_migrate.c

401

offset += (u64)rq->engine->instance << 32;

sys/dev/pci/drm/i915/gt/intel_migrate.c

535

int mocs = rq->engine->gt->mocs.uc_index << 1;

sys/dev/pci/drm/i915/gt/intel_migrate.c

567

*cs++ = rq->engine->instance |

sys/dev/pci/drm/i915/gt/intel_migrate.c

570

*cs++ = rq->engine->instance |

sys/dev/pci/drm/i915/gt/intel_migrate.c

585

u32 instance = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

689

struct drm_i915_private *i915 = ce->engine->i915;

sys/dev/pci/drm/i915/gt/intel_migrate.c

699

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/intel_migrate.c

700

GEM_BUG_ON(IS_DGFX(ce->engine->i915) && (!src_is_lmem && !dst_is_lmem));

sys/dev/pci/drm/i915/gt/intel_migrate.c

741

if (HAS_64K_PAGES(ce->engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_migrate.c

764

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/intel_migrate.c

765

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/intel_migrate.c

801

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

814

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

829

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

838

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

843

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

879

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_migrate.c

921

int mocs = rq->engine->gt->mocs.uc_index << 1;

sys/dev/pci/drm/i915/gt/intel_migrate.c

947

*cs++ = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

967

*cs++ = rq->engine->instance;

sys/dev/pci/drm/i915/gt/intel_migrate.c

992

struct drm_i915_private *i915 = ce->engine->i915;

sys/dev/pci/drm/i915/gt/intel_migrate.c

998

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/intel_mocs.c

566

static u32 mocs_offset(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_mocs.c

577

GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));

sys/dev/pci/drm/i915/gt/intel_mocs.c

578

return offset[engine->id];

sys/dev/pci/drm/i915/gt/intel_mocs.c

581

static void init_mocs_table(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_mocs.c

584

__init_mocs_table(engine->uncore, table, mocs_offset(engine));

sys/dev/pci/drm/i915/gt/intel_mocs.c

629

void intel_mocs_init_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_mocs.c

635

assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gt/intel_mocs.c

637

flags = get_mocs_settings(engine->i915, &table);

sys/dev/pci/drm/i915/gt/intel_mocs.c

643

init_mocs_table(engine, &table);

sys/dev/pci/drm/i915/gt/intel_mocs.c

645

if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_mocs.c

646

init_l3cc_table(engine->gt, &table);

sys/dev/pci/drm/i915/gt/intel_mocs.h

38

void intel_mocs_init_engine(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_rc6.c

138

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

157

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

158

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_rc6.c

208

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

215

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

216

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_rc6.c

231

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

242

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

243

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_rc6.c

359

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

367

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

368

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_rc6.c

387

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

394

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

395

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_rc6.c

60

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rc6.c

75

for_each_engine(engine, rc6_to_gt(rc6), id)

sys/dev/pci/drm/i915/gt/intel_rc6.c

76

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

145

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

15

render_state_get_rodata(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_renderstate.c

151

so->rodata = render_state_get_rodata(engine);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

156

obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

160

so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

17

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_renderstate.c

185

err = render_state_setup(so, engine->i915);

sys/dev/pci/drm/i915/gt/intel_renderstate.c

20

switch (GRAPHICS_VER(engine->i915)) {

sys/dev/pci/drm/i915/gt/intel_renderstate.c

212

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_renderstate.c

222

err = engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/intel_renderstate.c

229

err = engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/intel_reset.c

1001

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_reset.c

1002

engine->submit_request = nop_submit_request;

sys/dev/pci/drm/i915/gt/intel_reset.c

1014

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_reset.c

1015

if (engine->reset.cancel)

sys/dev/pci/drm/i915/gt/intel_reset.c

1016

engine->reset.cancel(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1047

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

1051

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_reset.c

1052

if (intel_engine_is_idle(engine))

sys/dev/pci/drm/i915/gt/intel_reset.c

1055

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/gt/intel_reset.c

1176

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

1180

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_reset.c

1181

ret = intel_engine_resume(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1334

int intel_gt_reset_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

1336

return __intel_gt_reset(engine->gt, engine->mask);

sys/dev/pci/drm/i915/gt/intel_reset.c

1339

int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)

sys/dev/pci/drm/i915/gt/intel_reset.c

1341

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_reset.c

1344

ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);

sys/dev/pci/drm/i915/gt/intel_reset.c

1345

GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));

sys/dev/pci/drm/i915/gt/intel_reset.c

1347

if (intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/gt/intel_reset.c

1350

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_reset.c

1353

reset_prepare_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1356

drm_notice(&engine->i915->drm,

sys/dev/pci/drm/i915/gt/intel_reset.c

1357

"Resetting %s for %s\n", engine->name, msg);

sys/dev/pci/drm/i915/gt/intel_reset.c

1358

i915_increase_reset_engine_count(&engine->i915->gpu_error, engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1360

ret = intel_gt_reset_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1363

ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);

sys/dev/pci/drm/i915/gt/intel_reset.c

1372

__intel_engine_reset(engine, true);

sys/dev/pci/drm/i915/gt/intel_reset.c

1379

ret = intel_engine_resume(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1382

intel_engine_cancel_stop_cs(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1383

reset_finish_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1384

intel_engine_pm_put_async(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

1401

int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)

sys/dev/pci/drm/i915/gt/intel_reset.c

1406

err = __intel_engine_reset_bh(engine, msg);

sys/dev/pci/drm/i915/gt/intel_reset.c

1484

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

1523

for_each_engine_masked(engine, gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gt/intel_reset.c

1525

if (test_and_set_bit(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/intel_reset.c

1529

if (__intel_engine_reset_bh(engine, msg) == 0)

sys/dev/pci/drm/i915/gt/intel_reset.c

1530

engine_mask &= ~engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

1532

clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/intel_reset.c

1556

for_each_engine(engine, gt, tmp) {

sys/dev/pci/drm/i915/gt/intel_reset.c

1557

while (test_and_set_bit(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/intel_reset.c

1560

I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/intel_reset.c

1571

for_each_engine(engine, gt, tmp)

sys/dev/pci/drm/i915/gt/intel_reset.c

1572

clear_bit_unlock(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/intel_reset.c

322

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

331

for_each_engine_masked(engine, gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gt/intel_reset.c

332

hw_mask |= engine->reset_domain;

sys/dev/pci/drm/i915/gt/intel_reset.c

353

static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

357

GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);

sys/dev/pci/drm/i915/gt/intel_reset.c

359

vecs_id = _VECS((engine->instance) / 2);

sys/dev/pci/drm/i915/gt/intel_reset.c

361

return engine->gt->engine[vecs_id];

sys/dev/pci/drm/i915/gt/intel_reset.c

374

static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_reset.c

377

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_reset.c

379

MISSING_CASE(engine->class);

sys/dev/pci/drm/i915/gt/intel_reset.c

382

sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

385

sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

388

sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

390

sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);

sys/dev/pci/drm/i915/gt/intel_reset.c

394

sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

397

sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

400

sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

402

sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);

sys/dev/pci/drm/i915/gt/intel_reset.c

408

static int gen11_lock_sfc(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_reset.c

412

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_reset.c

413

u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;

sys/dev/pci/drm/i915/gt/intel_reset.c

418

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_reset.c

420

if ((BIT(engine->instance) & vdbox_sfc_access) == 0)

sys/dev/pci/drm/i915/gt/intel_reset.c

425

get_sfc_forced_lock_data(engine, &sfc_lock);

sys/dev/pci/drm/i915/gt/intel_reset.c

435

if (engine->class != VIDEO_DECODE_CLASS ||

sys/dev/pci/drm/i915/gt/intel_reset.c

436

GRAPHICS_VER(engine->i915) != 12)

sys/dev/pci/drm/i915/gt/intel_reset.c

447

GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &

sys/dev/pci/drm/i915/gt/intel_reset.c

451

paired_vecs = find_sfc_paired_vecs_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

456

*unlock_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

492

ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");

sys/dev/pci/drm/i915/gt/intel_reset.c

500

static void gen11_unlock_sfc(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

502

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_reset.c

503

u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;

sys/dev/pci/drm/i915/gt/intel_reset.c

506

if (engine->class != VIDEO_DECODE_CLASS &&

sys/dev/pci/drm/i915/gt/intel_reset.c

507

engine->class != VIDEO_ENHANCEMENT_CLASS)

sys/dev/pci/drm/i915/gt/intel_reset.c

510

if (engine->class == VIDEO_DECODE_CLASS &&

sys/dev/pci/drm/i915/gt/intel_reset.c

511

(BIT(engine->instance) & vdbox_sfc_access) == 0)

sys/dev/pci/drm/i915/gt/intel_reset.c

514

get_sfc_forced_lock_data(engine, &sfc_lock);

sys/dev/pci/drm/i915/gt/intel_reset.c

523

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

532

for_each_engine_masked(engine, gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gt/intel_reset.c

533

reset_mask |= engine->reset_domain;

sys/dev/pci/drm/i915/gt/intel_reset.c

534

ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);

sys/dev/pci/drm/i915/gt/intel_reset.c

554

for_each_engine_masked(engine, gt, unlock_mask, tmp)

sys/dev/pci/drm/i915/gt/intel_reset.c

555

gen11_unlock_sfc(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

560

static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

562

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_reset.c

563

const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_reset.c

567

if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))

sys/dev/pci/drm/i915/gt/intel_reset.c

593

gt_err(engine->gt,

sys/dev/pci/drm/i915/gt/intel_reset.c

595

engine->name, request,

sys/dev/pci/drm/i915/gt/intel_reset.c

601

static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

603

intel_uncore_write_fw(engine->uncore,

sys/dev/pci/drm/i915/gt/intel_reset.c

604

RING_RESET_CTL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_reset.c

612

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

620

for_each_engine_masked(engine, gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gt/intel_reset.c

621

ret = gen8_engine_reset_prepare(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

655

for_each_engine_masked(engine, gt, engine_mask, tmp)

sys/dev/pci/drm/i915/gt/intel_reset.c

656

gen8_engine_reset_cancel(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

735

if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {

sys/dev/pci/drm/i915/gt/intel_reset.c

828

static void reset_prepare_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

837

intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gt/intel_reset.c

838

if (engine->reset.prepare)

sys/dev/pci/drm/i915/gt/intel_reset.c

839

engine->reset.prepare(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

887

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

903

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_reset.c

904

if (intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/gt/intel_reset.c

905

awake |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_reset.c

906

reset_prepare_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

919

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

932

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_reset.c

933

__intel_engine_reset(engine, stalled_mask & engine->mask);

sys/dev/pci/drm/i915/gt/intel_reset.c

943

static void reset_finish_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_reset.c

945

if (engine->reset.finish)

sys/dev/pci/drm/i915/gt/intel_reset.c

946

engine->reset.finish(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

947

intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gt/intel_reset.c

949

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

954

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.c

957

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_reset.c

958

reset_finish_engine(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

959

if (awake & engine->mask)

sys/dev/pci/drm/i915/gt/intel_reset.c

960

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

973

intel_engine_signal_breadcrumbs(request->engine);

sys/dev/pci/drm/i915/gt/intel_reset.c

981

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_reset.h

36

int intel_engine_reset(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_reset.h

38

int __intel_engine_reset_bh(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_reset.h

59

int intel_gt_reset_engine(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_ring.c

146

intel_engine_create_ring(struct intel_engine_cs *engine, int size)

sys/dev/pci/drm/i915/gt/intel_ring.c

148

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring.c

174

vma = create_ring_vma(engine->gt->ggtt, size);

sys/dev/pci/drm/i915/gt/intel_ring.h

16

intel_engine_create_ring(struct intel_engine_cs *engine, int size);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1036

ret = request->engine->emit_flush(request, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1050

struct intel_uncore *uncore = request->engine->uncore;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

108

} else if (GRAPHICS_VER(engine->i915) == 6) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1086

static void i9xx_set_default_submission(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1088

engine->submit_request = i9xx_submit_request;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

109

hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1091

static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1093

engine->submit_request = gen6_bsd_submit_request;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1096

static void ring_release(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1098

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1101

(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1103

intel_engine_cleanup_common(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1105

if (engine->wa_ctx.vma) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1106

intel_context_put(engine->wa_ctx.vma->private);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1107

i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

111

hwsp = RING_HWS_PGA(engine->mmio_base);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1110

intel_ring_unpin(engine->legacy.ring);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1111

intel_ring_put(engine->legacy.ring);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1113

intel_timeline_unpin(engine->legacy.timeline);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1114

intel_timeline_put(engine->legacy.timeline);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1117

static void irq_handler(struct intel_engine_cs *engine, u16 iir)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1119

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1122

static void setup_irq(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1124

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1126

intel_engine_set_irq_handler(engine, irq_handler);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1129

engine->irq_enable = gen6_irq_enable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1130

engine->irq_disable = gen6_irq_disable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1132

engine->irq_enable = gen5_irq_enable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1133

engine->irq_disable = gen5_irq_disable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1135

engine->irq_enable = gen2_irq_enable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1136

engine->irq_disable = gen2_irq_disable;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

114

intel_uncore_write_fw(engine->uncore, hwsp, offset);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1142

lockdep_assert_held(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1143

list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1148

spin_lock_irq(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

115

intel_uncore_posting_read_fw(engine->uncore, hwsp);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1154

spin_unlock_irq(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1159

static void setup_common(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1161

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1166

setup_irq(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1168

engine->resume = xcs_resume;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1169

engine->sanitize = xcs_sanitize;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1171

engine->reset.prepare = reset_prepare;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1172

engine->reset.rewind = reset_rewind;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1173

engine->reset.cancel = reset_cancel;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1174

engine->reset.finish = reset_finish;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1176

engine->add_active_request = add_to_engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1177

engine->remove_active_request = remove_from_engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1179

engine->cops = &ring_context_ops;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

118

static void flush_cs_tlb(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1180

engine->request_alloc = ring_request_alloc;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1187

engine->emit_fini_breadcrumb = gen2_emit_breadcrumb;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1189

engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1191

engine->set_default_submission = i9xx_set_default_submission;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1194

engine->emit_bb_start = gen6_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1196

engine->emit_bb_start = gen4_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1198

engine->emit_bb_start = i830_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

120

if (!IS_GRAPHICS_VER(engine->i915, 6, 7))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1200

engine->emit_bb_start = gen2_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1203

static void setup_rcs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1205

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1208

engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1210

engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1213

engine->emit_flush = gen7_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1214

engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1216

engine->emit_flush = gen6_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1217

engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1219

engine->emit_flush = gen4_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1222

engine->emit_flush = gen2_emit_flush;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1224

engine->emit_flush = gen4_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1225

engine->irq_enable_mask = I915_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1229

engine->emit_bb_start = hsw_emit_bb_start;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1232

static void setup_vcs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1234

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1239

engine->set_default_submission = gen6_bsd_set_default_submission;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

124

if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1240

engine->emit_flush = gen6_emit_flush_vcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1241

engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1244

engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1246

engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1248

engine->emit_flush = gen4_emit_flush_vcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

125

drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1250

engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1252

engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1256

static void setup_bcs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1258

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

126

engine->name);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1260

engine->emit_flush = gen6_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1261

engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1264

engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1266

engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1269

static void setup_vecs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1271

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1275

engine->emit_flush = gen6_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1276

engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1277

engine->irq_enable = hsw_irq_enable_vecs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1278

engine->irq_disable = hsw_irq_disable_vecs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

128

ENGINE_WRITE_FW(engine, RING_INSTPM,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1280

engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1283

static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1286

return gen7_setup_clear_gpr_bb(engine, vma);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1289

static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1303

err = gen7_ctx_switch_bb_setup(engine, vma);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1307

engine->wa_ctx.vma = vma;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

131

if (__intel_wait_for_register_fw(engine->uncore,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1315

static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

132

RING_INSTPM(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1321

if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1324

err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1332

obj = i915_gem_object_create_internal(engine->i915, size);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1336

vma = i915_vma_instance(obj, engine->gt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1342

vma->private = intel_context_create(engine); /* dummy residuals */

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

135

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1353

int intel_ring_submission_setup(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1361

setup_common(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1363

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1365

setup_rcs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1368

setup_vcs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1371

setup_bcs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1374

setup_vecs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1377

MISSING_CASE(engine->class);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1381

timeline = intel_timeline_create_from_engine(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1389

ring = intel_engine_create_ring(engine, SZ_16K);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

139

static void ring_setup_status_page(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1395

GEM_BUG_ON(engine->legacy.ring);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1396

engine->legacy.ring = ring;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1397

engine->legacy.timeline = timeline;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1399

gen7_wa_vma = gen7_ctx_vma(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

141

set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1412

err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

142

set_hwstam(engine, ~0u);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1423

GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1426

err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

144

flush_cs_tlb(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1444

engine->release = ring_release;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1458

intel_engine_cleanup_common(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

160

static void set_pp_dir(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

162

struct i915_address_space *vm = vm_alias(engine->gt->vm);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

167

ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

168

ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

170

if (GRAPHICS_VER(engine->i915) >= 7) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

171

ENGINE_WRITE_FW(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

177

static bool stop_ring(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

180

ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

181

ENGINE_POSTING_READ(engine, RING_HEAD);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

184

ENGINE_WRITE_FW(engine, RING_CTL, 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

185

ENGINE_POSTING_READ(engine, RING_CTL);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

188

ENGINE_WRITE_FW(engine, RING_HEAD, 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

189

ENGINE_WRITE_FW(engine, RING_TAIL, 0);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

191

return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

194

static int xcs_resume(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

196

struct intel_ring *ring = engine->legacy.ring;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

199

ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

206

intel_synchronize_hardirq(engine->i915);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

207

if (!stop_ring(engine))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

210

if (HWS_NEEDS_PHYSICAL(engine->i915))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

211

ring_setup_phys_status_page(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

213

ring_setup_status_page(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

215

intel_breadcrumbs_reset(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

218

ENGINE_POSTING_READ(engine, RING_HEAD);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

226

ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

233

set_pp_dir(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

249

ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

250

if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

254

ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

255

if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

256

ENGINE_TRACE(engine, "failed to reset empty ring: [%x, %x]: %x\n",

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

257

ENGINE_READ_FW(engine, RING_HEAD),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

258

ENGINE_READ_FW(engine, RING_TAIL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

263

ENGINE_WRITE_FW(engine, RING_CTL,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

267

if (__intel_wait_for_register_fw(engine->uncore,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

268

RING_CTL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

271

ENGINE_TRACE(engine, "failed to restart\n");

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

275

if (GRAPHICS_VER(engine->i915) > 2) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

276

ENGINE_WRITE_FW(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

278

ENGINE_POSTING_READ(engine, RING_MI_MODE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

283

ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

284

ENGINE_POSTING_READ(engine, RING_TAIL);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

288

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

292

gt_err(engine->gt, "%s initialization failed\n", engine->name);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

293

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

295

ENGINE_READ(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

296

ENGINE_READ(engine, RING_CTL) & RING_VALID,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

297

ENGINE_READ(engine, RING_HEAD), ring->head,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

298

ENGINE_READ(engine, RING_TAIL), ring->tail,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

299

ENGINE_READ(engine, RING_START),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

305

static void sanitize_hwsp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

309

list_for_each_entry(tl, &engine->status_page.timelines, engine_link)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

313

static void xcs_sanitize(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

325

memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

332

sanitize_hwsp(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

335

drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

337

intel_engine_reset_pinned_contexts(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

340

static void reset_prepare(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

357

ENGINE_TRACE(engine, "\n");

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

358

intel_engine_stop_cs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

360

if (!stop_ring(engine)) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

362

ENGINE_TRACE(engine,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

365

ENGINE_READ_FW(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

366

ENGINE_READ_FW(engine, RING_HEAD),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

367

ENGINE_READ_FW(engine, RING_TAIL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

368

ENGINE_READ_FW(engine, RING_START));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

37

static void set_hwstam(struct intel_engine_cs *engine, u32 mask)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

375

if (wait_for_atomic((!stop_ring(engine) == 0), 20)) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

376

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

379

engine->name,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

380

ENGINE_READ_FW(engine, RING_CTL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

381

ENGINE_READ_FW(engine, RING_HEAD),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

382

ENGINE_READ_FW(engine, RING_TAIL),

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

383

ENGINE_READ_FW(engine, RING_START));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

388

static void reset_rewind(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

395

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

397

list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

43

if (engine->class == RENDER_CLASS) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

44

if (GRAPHICS_VER(engine->i915) >= 6)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

445

GEM_BUG_ON(rq->ring != engine->legacy.ring);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

448

head = engine->legacy.ring->tail;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

450

engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

452

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

455

static void reset_finish(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

459

static void reset_cancel(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

464

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

467

list_for_each_entry(request, &engine->sched_engine->requests, sched.link)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

469

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

473

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

481

ENGINE_WRITE(request->engine, RING_TAIL,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

50

intel_engine_set_hwsp_writemask(engine, mask);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

514

shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

516

uao_read(ce->default_state, 0, vaddr, ce->engine->context_size);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

53

static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

566

alloc_context_vma(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

568

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

573

obj = i915_gem_object_create_shmem(i915, engine->context_size);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

58

if (GRAPHICS_VER(engine->i915) >= 4)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

595

vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

61

intel_uncore_write(engine->uncore, HWS_PGA, addr);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

610

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

613

ce->default_state = engine->default_state;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

616

GEM_BUG_ON(!engine->legacy.ring);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

617

ce->ring = engine->legacy.ring;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

620

if (engine->context_size) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

623

vma = alloc_context_vma(engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

630

ce->timeline = intel_timeline_get(engine->legacy.timeline);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

64

static struct vm_page *status_page(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

650

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

655

engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

656

lockdep_assert_held(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

657

list_for_each_entry_continue(rq, &engine->sched_engine->requests,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

66

struct drm_i915_gem_object *obj = engine->status_page.vma->obj;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

668

struct intel_engine_cs *engine = NULL;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

670

i915_request_active_engine(rq, &engine);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

672

if (engine && intel_engine_pulse(engine))

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

673

intel_gt_handle_error(engine->gt, engine->mask, 0,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

701

const struct intel_engine_cs * const engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

709

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

713

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

718

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

719

*cs++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

72

static void ring_setup_phys_status_page(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

723

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

728

return rq->engine->emit_flush(rq, EMIT_FLUSH);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

735

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

736

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

739

IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

74

set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

75

set_hwstam(engine, ~0u);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

767

for_each_engine(signaller, engine->gt, id) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

768

if (signaller == engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

78

static void set_hwsp(struct intel_engine_cs *engine, u32 offset)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

801

*cs++ = i915_ggtt_offset(engine->kernel_context->state) |

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

821

for_each_engine(signaller, engine->gt, id) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

822

if (signaller == engine)

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

834

*cs++ = intel_gt_scratch_offset(engine->gt,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

86

if (GRAPHICS_VER(engine->i915) == 7) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

87

switch (engine->id) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

906

ret = rq->engine->emit_flush(rq, EMIT_FLUSH);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

922

return rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

927

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

93

GEM_BUG_ON(engine->id);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

930

ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

934

if (engine->kernel_context->state) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

936

engine->kernel_context,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

942

ret = engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

943

i915_vma_offset(engine->wa_ctx.vma), 0,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

948

ret = engine->emit_flush(rq, EMIT_FLUSH);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

953

return engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

958

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

963

GEM_BUG_ON(HAS_EXECLISTS(engine->i915));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

965

if (engine->wa_ctx.vma && ce != engine->kernel_context) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

966

if (engine->wa_ctx.vma->private != ce &&

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

972

residuals = &engine->wa_ctx.vma->private;

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

983

GEM_BUG_ON(engine->id != RCS0);

sys/dev/pci/drm/i915/gt/intel_rps.c

1034

struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;

sys/dev/pci/drm/i915/gt/intel_rps.c

1536

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rps.c

1539

for_each_engine(engine, rps_to_gt(rps), id) {

sys/dev/pci/drm/i915/gt/intel_rps.c

1540

if (!intel_engine_supports_stats(engine))

sys/dev/pci/drm/i915/gt/intel_rps.c

1953

intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10);

sys/dev/pci/drm/i915/gt/intel_rps.c

84

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_rps.c

90

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_rps.c

94

dt = intel_engine_get_busy_time(engine, &timestamp);

sys/dev/pci/drm/i915/gt/intel_rps.c

95

last = engine->stats.rps;

sys/dev/pci/drm/i915/gt/intel_rps.c

96

engine->stats.rps = dt;

sys/dev/pci/drm/i915/gt/intel_timeline.c

167

intel_timeline_create_from_engine(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_timeline.c

170

struct i915_vma *hwsp = engine->status_page.vma;

sys/dev/pci/drm/i915/gt/intel_timeline.c

173

tl = __intel_timeline_create(engine->gt, hwsp, offset);

sys/dev/pci/drm/i915/gt/intel_timeline.c

179

list_add_tail(&tl->engine_link, &engine->status_page.timelines);

sys/dev/pci/drm/i915/gt/intel_timeline.c

460

to_request(fence)->engine->name);

sys/dev/pci/drm/i915/gt/intel_timeline.h

30

intel_timeline_create_from_engine(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_tlb.c

101

engine->name, TLB_INVAL_TIMEOUT_MS);

sys/dev/pci/drm/i915/gt/intel_tlb.c

30

static int wait_for_invalidate(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_tlb.c

32

if (engine->tlb_inv.mcr)

sys/dev/pci/drm/i915/gt/intel_tlb.c

33

return intel_gt_mcr_wait_for_reg(engine->gt,

sys/dev/pci/drm/i915/gt/intel_tlb.c

34

engine->tlb_inv.reg.mcr_reg,

sys/dev/pci/drm/i915/gt/intel_tlb.c

35

engine->tlb_inv.done,

sys/dev/pci/drm/i915/gt/intel_tlb.c

40

return __intel_wait_for_register_fw(engine->gt->uncore,

sys/dev/pci/drm/i915/gt/intel_tlb.c

41

engine->tlb_inv.reg.reg,

sys/dev/pci/drm/i915/gt/intel_tlb.c

42

engine->tlb_inv.done,

sys/dev/pci/drm/i915/gt/intel_tlb.c

53

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_tlb.c

67

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_tlb.c

68

if (!intel_engine_pm_is_awake(engine))

sys/dev/pci/drm/i915/gt/intel_tlb.c

71

if (engine->tlb_inv.mcr)

sys/dev/pci/drm/i915/gt/intel_tlb.c

73

engine->tlb_inv.reg.mcr_reg,

sys/dev/pci/drm/i915/gt/intel_tlb.c

74

engine->tlb_inv.request);

sys/dev/pci/drm/i915/gt/intel_tlb.c

77

engine->tlb_inv.reg.reg,

sys/dev/pci/drm/i915/gt/intel_tlb.c

78

engine->tlb_inv.request);

sys/dev/pci/drm/i915/gt/intel_tlb.c

80

awake |= engine->mask;

sys/dev/pci/drm/i915/gt/intel_tlb.c

97

for_each_engine_masked(engine, gt, awake, tmp) {

sys/dev/pci/drm/i915/gt/intel_tlb.c

98

if (wait_for_invalidate(engine))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1004

ret = rq->engine->emit_flush(rq, EMIT_BARRIER);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1008

if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1009

IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1044

if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1045

IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1058

ret = rq->engine->emit_flush(rq, EMIT_BARRIER);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1493

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1496

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1497

if (engine->class != VIDEO_DECODE_CLASS ||

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1498

(engine->instance % 2))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1501

wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1615

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1618

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1619

if (engine->class == VIDEO_DECODE_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1620

wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1922

static void skl_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1924

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1926

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1935

static void bxt_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1937

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1940

gen9_whitelist_build(&engine->whitelist);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1943

static void kbl_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1945

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1947

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1956

static void glk_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1958

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1960

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1969

static void cfl_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1971

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1973

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1992

static void allow_read_ctx_timestamp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1994

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1996

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1998

RING_CTX_TIMESTAMP(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2002

static void cml_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2004

allow_read_ctx_timestamp(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2006

cfl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2009

static void icl_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2011

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2013

allow_read_ctx_timestamp(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2015

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2042

whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2045

whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2048

whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2057

static void tgl_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2059

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2061

allow_read_ctx_timestamp(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2063

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2098

static void dg2_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2100

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2102

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2113

static void xelpg_whitelist_build(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2115

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2117

switch (engine->class) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2128

void intel_engine_init_whitelist(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2130

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2131

struct i915_wa_list *w = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2133

wa_init_start(w, engine->gt, "whitelist", engine->name);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2135

if (engine->gt->type == GT_MEDIA)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2137

else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2138

xelpg_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2140

dg2_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2142

tgl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2144

icl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2146

cml_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2148

cfl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2150

glk_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2152

kbl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2154

bxt_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2156

skl_whitelist_build(engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2165

void intel_engine_apply_whitelist(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2167

const struct i915_wa_list *wal = &engine->whitelist;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2168

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2169

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2196

engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2208

if (GRAPHICS_VER(engine->i915) >= 12) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2209

mocs_r = engine->gt->mocs.uc_index;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2210

mocs_w = engine->gt->mocs.uc_index;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2212

if (HAS_L3_CCS_READ(engine->i915) &&

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2213

engine->class == COMPUTE_CLASS) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2214

mocs_r = engine->gt->mocs.wb_index;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2222

drm_WARN_ON(&engine->i915->drm, mocs_r == 0);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2226

RING_CMD_CCTL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2233

rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2235

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2236

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2686

xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2688

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2693

RING_SEMA_WAIT_POLL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2697

if (NEEDS_FASTCOLOR_BLT_WABB(engine))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2698

wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2704

ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2743

static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2745

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2777

general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2779

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2780

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2887

engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2889

if (GRAPHICS_VER(engine->i915) < 4)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2892

engine_fake_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2899

if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2900

general_render_compute_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2901

ccs_engine_wa_mode(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2904

if (engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2905

ccs_engine_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2906

else if (engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2907

rcs_engine_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2909

xcs_engine_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2912

void intel_engine_init_workarounds(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2914

struct i915_wa_list *wal = &engine->wa_list;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2916

wa_init_start(wal, engine->gt, "engine", engine->name);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2917

engine_init_workarounds(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2921

void intel_engine_apply_workarounds(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2923

wa_list_apply(&engine->wa_list);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3042

vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3047

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3114

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3119

int intel_engine_verify_workarounds(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3122

return engine_wa_list_verify(engine->kernel_context,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3123

&engine->wa_list,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

336

static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

345

static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

362

static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

410

static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

413

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

415

gen8_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

438

static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

441

gen8_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

450

static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

453

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

546

static void skl_tune_iz_hashing(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

549

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

586

static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

589

gen9_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

590

skl_tune_iz_hashing(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

593

static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

596

gen9_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

607

static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

610

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

612

gen9_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

624

static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

627

gen9_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

634

static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

637

gen9_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

648

static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

651

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

703

static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

713

static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

716

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

778

static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

781

gen12_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

792

static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

795

dg2_ctx_gt_tuning_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

814

static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

817

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

819

dg2_ctx_gt_tuning_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

831

static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

834

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

836

xelpg_ctx_gt_tuning_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

862

static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

890

wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

893

static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

903

if (engine->class == COPY_ENGINE_CLASS) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

904

mocs = engine->gt->mocs.uc_index;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

906

BLIT_CCTL(engine->mmio_base),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

919

gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

922

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

923

fakewa_disable_nestedbb_mode(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

925

gen12_ctx_gt_mocs_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

929

__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

933

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

935

wa_init_start(wal, engine->gt, name, engine->name);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

943

gen12_ctx_gt_fake_wa_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

945

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

948

if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

949

xelpg_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

951

dg2_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

953

dg1_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

955

gen12_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

957

icl_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

959

cfl_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

961

glk_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

963

kbl_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

965

bxt_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

967

skl_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

969

chv_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

971

bdw_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

973

gen7_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

975

gen6_ctx_workarounds_init(engine, wal);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

985

void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

987

__intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");

sys/dev/pci/drm/i915/gt/intel_workarounds.c

992

struct i915_wa_list *wal = &rq->engine->ctx_wa_list;

sys/dev/pci/drm/i915/gt/intel_workarounds.c

993

struct intel_uncore *uncore = rq->engine->uncore;

sys/dev/pci/drm/i915/gt/intel_workarounds.h

24

void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.h

31

void intel_engine_init_whitelist(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.h

32

void intel_engine_apply_whitelist(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.h

34

void intel_engine_init_workarounds(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.h

35

void intel_engine_apply_workarounds(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/intel_workarounds.h

36

int intel_engine_verify_workarounds(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/mock_engine.c

106

intel_engine_signal_breadcrumbs(request->engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

111

struct mock_engine *engine = timer_container_of(engine, t, hw_delay);

sys/dev/pci/drm/i915/gt/mock_engine.c

115

spin_lock_irqsave(&engine->hw_lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

118

request = first_request(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

126

while ((request = first_request(engine))) {

sys/dev/pci/drm/i915/gt/mock_engine.c

128

mod_timer(&engine->hw_delay,

sys/dev/pci/drm/i915/gt/mock_engine.c

136

spin_unlock_irqrestore(&engine->hw_lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

167

ce->ring = mock_ring(ce->engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

171

ce->timeline = intel_timeline_create(ce->engine->gt);

sys/dev/pci/drm/i915/gt/mock_engine.c

173

kfree(ce->engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

238

struct mock_engine *engine =

sys/dev/pci/drm/i915/gt/mock_engine.c

239

container_of(request->engine, typeof(*engine), base);

sys/dev/pci/drm/i915/gt/mock_engine.c

244

spin_lock_irqsave(&engine->hw_lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

245

list_add_tail(&request->mock.link, &engine->hw_queue);

sys/dev/pci/drm/i915/gt/mock_engine.c

246

if (list_is_first(&request->mock.link, &engine->hw_queue)) {

sys/dev/pci/drm/i915/gt/mock_engine.c

248

mod_timer(&engine->hw_delay,

sys/dev/pci/drm/i915/gt/mock_engine.c

253

spin_unlock_irqrestore(&engine->hw_lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

258

lockdep_assert_held(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/mock_engine.c

259

list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);

sys/dev/pci/drm/i915/gt/mock_engine.c

264

struct intel_engine_cs *engine, *locked;

sys/dev/pci/drm/i915/gt/mock_engine.c

273

locked = READ_ONCE(rq->engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

275

while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {

sys/dev/pci/drm/i915/gt/mock_engine.c

277

spin_lock(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/mock_engine.c

278

locked = engine;

sys/dev/pci/drm/i915/gt/mock_engine.c

284

static void mock_reset_prepare(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

288

static void mock_reset_rewind(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/mock_engine.c

293

static void mock_reset_cancel(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

296

container_of(engine, typeof(*mock), base);

sys/dev/pci/drm/i915/gt/mock_engine.c

302

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

305

list_for_each_entry(rq, &engine->sched_engine->requests, sched.link)

sys/dev/pci/drm/i915/gt/mock_engine.c

307

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

318

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/gt/mock_engine.c

321

static void mock_reset_finish(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

325

static void mock_engine_release(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

328

container_of(engine, typeof(*mock), base);

sys/dev/pci/drm/i915/gt/mock_engine.c

332

i915_sched_engine_put(engine->sched_engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

333

intel_breadcrumbs_put(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/mock_engine.c

335

intel_context_unpin(engine->kernel_context);

sys/dev/pci/drm/i915/gt/mock_engine.c

336

intel_context_put(engine->kernel_context);

sys/dev/pci/drm/i915/gt/mock_engine.c

338

intel_engine_fini_retire(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

345

struct mock_engine *engine;

sys/dev/pci/drm/i915/gt/mock_engine.c

350

engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);

sys/dev/pci/drm/i915/gt/mock_engine.c

351

if (!engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

355

engine->base.i915 = i915;

sys/dev/pci/drm/i915/gt/mock_engine.c

356

engine->base.gt = to_gt(i915);

sys/dev/pci/drm/i915/gt/mock_engine.c

357

engine->base.uncore = to_gt(i915)->uncore;

sys/dev/pci/drm/i915/gt/mock_engine.c

358

snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);

sys/dev/pci/drm/i915/gt/mock_engine.c

359

engine->base.id = id;

sys/dev/pci/drm/i915/gt/mock_engine.c

360

engine->base.mask = BIT(id);

sys/dev/pci/drm/i915/gt/mock_engine.c

361

engine->base.legacy_idx = INVALID_ENGINE;

sys/dev/pci/drm/i915/gt/mock_engine.c

362

engine->base.instance = id;

sys/dev/pci/drm/i915/gt/mock_engine.c

363

engine->base.status_page.addr = (void *)(engine + 1);

sys/dev/pci/drm/i915/gt/mock_engine.c

365

engine->base.cops = &mock_context_ops;

sys/dev/pci/drm/i915/gt/mock_engine.c

366

engine->base.request_alloc = mock_request_alloc;

sys/dev/pci/drm/i915/gt/mock_engine.c

367

engine->base.emit_flush = mock_emit_flush;

sys/dev/pci/drm/i915/gt/mock_engine.c

368

engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;

sys/dev/pci/drm/i915/gt/mock_engine.c

369

engine->base.submit_request = mock_submit_request;

sys/dev/pci/drm/i915/gt/mock_engine.c

370

engine->base.add_active_request = mock_add_to_engine;

sys/dev/pci/drm/i915/gt/mock_engine.c

371

engine->base.remove_active_request = mock_remove_from_engine;

sys/dev/pci/drm/i915/gt/mock_engine.c

373

engine->base.reset.prepare = mock_reset_prepare;

sys/dev/pci/drm/i915/gt/mock_engine.c

374

engine->base.reset.rewind = mock_reset_rewind;

sys/dev/pci/drm/i915/gt/mock_engine.c

375

engine->base.reset.cancel = mock_reset_cancel;

sys/dev/pci/drm/i915/gt/mock_engine.c

376

engine->base.reset.finish = mock_reset_finish;

sys/dev/pci/drm/i915/gt/mock_engine.c

378

engine->base.release = mock_engine_release;

sys/dev/pci/drm/i915/gt/mock_engine.c

380

to_gt(i915)->engine[id] = &engine->base;

sys/dev/pci/drm/i915/gt/mock_engine.c

381

to_gt(i915)->engine_class[0][id] = &engine->base;

sys/dev/pci/drm/i915/gt/mock_engine.c

384

mtx_init(&engine->hw_lock, IPL_TTY);

sys/dev/pci/drm/i915/gt/mock_engine.c

385

timer_setup(&engine->hw_delay, hw_delay_complete, 0);

sys/dev/pci/drm/i915/gt/mock_engine.c

386

INIT_LIST_HEAD(&engine->hw_queue);

sys/dev/pci/drm/i915/gt/mock_engine.c

388

intel_engine_add_user(&engine->base);

sys/dev/pci/drm/i915/gt/mock_engine.c

390

return &engine->base;

sys/dev/pci/drm/i915/gt/mock_engine.c

393

int mock_engine_init(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

397

INIT_LIST_HEAD(&engine->pinned_contexts_list);

sys/dev/pci/drm/i915/gt/mock_engine.c

399

engine->sched_engine = i915_sched_engine_create(ENGINE_MOCK);

sys/dev/pci/drm/i915/gt/mock_engine.c

400

if (!engine->sched_engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

402

engine->sched_engine->private_data = engine;

sys/dev/pci/drm/i915/gt/mock_engine.c

404

intel_engine_init_execlists(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

405

intel_engine_init__pm(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

406

intel_engine_init_retire(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

408

engine->breadcrumbs = intel_breadcrumbs_create(NULL);

sys/dev/pci/drm/i915/gt/mock_engine.c

409

if (!engine->breadcrumbs)

sys/dev/pci/drm/i915/gt/mock_engine.c

412

ce = create_kernel_context(engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

417

engine->status_page.vma = ce->timeline->hwsp_ggtt;

sys/dev/pci/drm/i915/gt/mock_engine.c

419

engine->kernel_context = ce;

sys/dev/pci/drm/i915/gt/mock_engine.c

423

intel_breadcrumbs_put(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/mock_engine.c

425

i915_sched_engine_put(engine->sched_engine);

sys/dev/pci/drm/i915/gt/mock_engine.c

429

void mock_engine_flush(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

432

container_of(engine, typeof(*mock), base);

sys/dev/pci/drm/i915/gt/mock_engine.c

443

void mock_engine_reset(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

60

static struct intel_ring *mock_ring(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

75

ring->vma = create_ring_vma(engine->gt->ggtt, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/mock_engine.c

93

static struct i915_request *first_request(struct mock_engine *engine)

sys/dev/pci/drm/i915/gt/mock_engine.c

95

return list_first_entry_or_null(&engine->hw_queue,

sys/dev/pci/drm/i915/gt/mock_engine.h

26

int mock_engine_init(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/mock_engine.h

28

void mock_engine_flush(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/mock_engine.h

29

void mock_engine_reset(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/mock_engine.h

30

void mock_engine_free(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

106

err = i915_active_acquire_preallocate_barrier(&p->active, engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

116

GEM_BUG_ON(llist_empty(&engine->barrier_tasks));

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

118

err = fn(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

122

GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

124

if (engine_sync_barrier(engine)) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

125

struct drm_printer m = drm_err_printer(&engine->i915->drm, "pulse");

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

127

drm_printf(&m, "%s: no heartbeat pulse?\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

128

intel_engine_dump(engine, &m, "%s", engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

134

GEM_BUG_ON(READ_ONCE(engine->serial) != engine->wakeref_serial);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

139

struct drm_printer m = drm_err_printer(&engine->i915->drm, "pulse");

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

14

static void reset_heartbeat(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

142

engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

157

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

16

intel_engine_set_heartbeat(engine,

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

163

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

164

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

165

err = __live_idle_pulse(engine, intel_engine_flush_barriers);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

166

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

17

engine->defaults.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

177

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

183

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

184

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

185

err = __live_idle_pulse(engine, intel_engine_pulse);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

186

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

196

static int __live_heartbeat_off(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

200

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

202

engine->serial++;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

203

flush_delayed_work(&engine->heartbeat.work);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

204

if (!delayed_work_pending(&engine->heartbeat.work)) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

206

engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

211

err = intel_engine_set_heartbeat(engine, 0);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

215

engine->serial++;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

216

flush_delayed_work(&engine->heartbeat.work);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

217

if (delayed_work_pending(&engine->heartbeat.work)) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

219

engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

224

if (READ_ONCE(engine->heartbeat.systole)) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

226

engine->name);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

232

reset_heartbeat(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

234

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

241

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

249

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

250

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

253

err = __live_heartbeat_off(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

283

void st_engine_heartbeat_disable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

285

engine->props.heartbeat_interval_ms = 0;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

287

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

288

intel_engine_park_heartbeat(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

291

void st_engine_heartbeat_enable(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

293

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

295

engine->props.heartbeat_interval_ms =

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

296

engine->defaults.heartbeat_interval_ms;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

299

void st_engine_heartbeat_disable_no_pm(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

301

engine->props.heartbeat_interval_ms = 0;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

309

if (intel_engine_pm_get_if_awake(engine)) {

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

310

intel_engine_park_heartbeat(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

311

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

315

void st_engine_heartbeat_enable_no_pm(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

317

engine->props.heartbeat_interval_ms =

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

318

engine->defaults.heartbeat_interval_ms;

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

37

static int engine_sync_barrier(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

39

return timeline_sync(engine->kernel_context->timeline);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

90

static int __live_idle_pulse(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.c

96

GEM_BUG_ON(!intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.h

11

void st_engine_heartbeat_disable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.h

12

void st_engine_heartbeat_disable_no_pm(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.h

13

void st_engine_heartbeat_enable(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/selftest_engine_heartbeat.h

14

void st_engine_heartbeat_enable_no_pm(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

100

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1021

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1022

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1027

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1028

err = slice_semaphore_queue(engine, vma, 5);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1029

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1054

i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1088

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1114

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

112

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1127

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1136

if (!intel_engine_has_timeslices(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1150

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1151

timeslice = xchg(&engine->props.timeslice_duration_ms, 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1153

slot = memset32(engine->status_page.addr + 1000, 0, 4);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1155

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1172

err = wait_for_submit(engine, rq[A2], HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1175

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1179

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1190

err = wait_for_submit(engine, rq[B1], HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1193

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1198

ENGINE_TRACE(engine, "forcing tasklet for rewind\n");

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1201

timer_delete(&engine->execlists.timer);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1202

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1203

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1223

engine->name, i - 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1228

pr_debug("%s: slot[%d]:%x\n", engine->name, i, slot[i]);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

123

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1234

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1244

engine->props.timeslice_duration_ms = timeslice;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1245

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1257

static struct i915_request *nop_request(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1261

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

127

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1271

static long slice_timeout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1276

timeout = 2 * msecs_to_jiffies_timeout(timeslice(engine));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1288

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1328

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1332

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1335

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1339

rq = semaphore_queue(engine, vma, 0);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1344

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1345

err = wait_for_submit(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1348

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1353

nop = nop_request(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1358

err = wait_for_submit(engine, nop, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1362

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1367

GEM_BUG_ON(execlists_active(&engine->execlists) != rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1370

err = release_queue(engine, vma, 1, effective_prio(rq));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1377

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1378

} while (READ_ONCE(engine->execlists.pending[0]));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1381

if (i915_request_wait(rq, 0, slice_timeout(engine)) < 0) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1386

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1387

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1388

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1396

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1413

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1428

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1433

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1436

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1442

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1443

timeslice = xchg(&engine->props.timeslice_duration_ms, 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1468

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1489

if (wait_for_submit(engine, rq, HZ / 2)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1500

if (i915_request_wait(rq, 0, slice_timeout(engine)) >= 0) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1502

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1510

xchg(&engine->props.timeslice_duration_ms, timeslice);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1511

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1529

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1581

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1586

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1589

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1592

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1606

lo = igt_request_alloc(ctx_lo, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1649

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1654

hi = igt_request_alloc(ctx_hi, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

166

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1681

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1683

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1717

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1723

ce = i915_gem_context_get_engine(ctx, engine->legacy_idx);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1737

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1757

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1761

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1764

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1769

rq = spinner_create_request(&spin_lo, ctx_lo, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1785

rq = spinner_create_request(&spin_hi, ctx_hi, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

180

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1828

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1850

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1854

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1857

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

186

if (prio && !intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1862

rq = spinner_create_request(&spin_lo, ctx_lo, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1875

rq = spinner_create_request(&spin_hi, ctx_hi, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

189

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1890

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

192

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1956

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

196

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1972

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1975

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1978

engine->execlists.preempt_hang.count = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1981

a.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1998

b.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

201

tmp = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2025

if (engine->execlists.preempt_hang.count) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2027

engine->execlists.preempt_hang.count);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2052

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2063

GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2064

if (igt_live_test_begin(&t, arg->engine->i915,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2065

__func__, arg->engine->name))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2069

arg->a.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2083

err = intel_engine_pulse(arg->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2087

err = wait_for_reset(arg->engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2107

GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2108

if (igt_live_test_begin(&t, arg->engine->i915,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2109

__func__, arg->engine->name))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2113

arg->a.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2127

arg->b.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2142

err = intel_engine_pulse(arg->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2147

err = wait_for_reset(arg->engine, rq[1], HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2178

GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2179

if (igt_live_test_begin(&t, arg->engine->i915,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2180

__func__, arg->engine->name))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2184

arg->a.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2197

rq[1] = igt_request_alloc(arg->b.ctx, arg->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2211

arg->a.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2225

err = intel_engine_pulse(arg->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2229

err = wait_for_reset(arg->engine, rq[2], HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2244

if (intel_engine_has_semaphores(rq[1]->engine) &&

sys/dev/pci/drm/i915/gt/selftest_execlists.c

226

lrc_update_regs(ce[1], engine, ce[1]->ring->head);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2275

if (!intel_has_reset_engine(arg->engine->gt))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2278

GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2280

arg->a.ctx, arg->engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2294

err = intel_engine_pulse(arg->engine); /* force reset */

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2298

err = wait_for_reset(arg->engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2306

if (igt_flush_test(arg->engine->i915))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2311

static void force_reset_timeout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2313

engine->reset_timeout.probability = 999;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2314

atomic_set(&engine->reset_timeout.times, -1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2317

static void cancel_reset_timeout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2319

memset(&engine->reset_timeout, 0, sizeof(engine->reset_timeout));

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2324

struct intel_engine_cs *engine = arg->engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2331

if (!intel_has_reset_engine(engine->gt))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2334

GEM_TRACE("%s(%s)\n", __func__, engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2336

arg->a.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2351

err = intel_engine_pulse(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2355

force_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2358

while (!engine->execlists.pending[0])

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2359

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2360

timer_delete_sync(&engine->execlists.preempt);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2361

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2363

cancel_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2366

intel_engine_set_heartbeat(engine, 1);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2367

err = wait_for_reset(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2368

intel_engine_set_heartbeat(engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2369

engine->defaults.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2377

if (igt_flush_test(engine->i915))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2399

for_each_engine(data.engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

24

#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2400

if (!intel_engine_has_preemption(data.engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2443

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2466

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2470

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2476

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2477

engine->execlists.preempt_hang.count = 0;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2480

a.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2484

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2491

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2496

mod_timer(&engine->execlists.timer, jiffies + HZ);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2499

b.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2503

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2509

engine->sched_engine->schedule(rq_a, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2514

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2523

if (engine->execlists.preempt_hang.count) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2525

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2526

engine->execlists.preempt_hang.count,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2528

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2533

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2556

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2573

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2579

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2583

lo.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2596

__func__, engine->name, ring_size);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2600

pr_err("Timed out waiting to flush %s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2606

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2613

hi.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2622

lo.ctx, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2629

rq = igt_request_alloc(lo.ctx, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2635

rq = igt_request_alloc(hi.ctx, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2641

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2650

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2651

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2658

rq = igt_request_alloc(lo.ctx, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2671

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2672

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2701

static int create_gang(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2711

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2715

obj = i915_gem_object_create_internal(engine->i915, 4096);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

275

engine->sched_engine->schedule(rq[1], &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2772

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2796

static int __live_preempt_ring(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2806

if (igt_live_test_begin(&t, engine->i915, __func__, engine->name))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2812

tmp = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2844

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2863

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2866

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2868

engine->name, queue_sz, n,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2886

err = wait_for_submit(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2890

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2895

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2900

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2917

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2931

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2934

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2937

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

294

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2940

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2943

err = __live_preempt_ring(engine, &spin,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2949

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2961

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2974

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2982

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2985

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2991

err = create_gang(engine, &rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2996

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3000

engine->name, prio);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3022

drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3026

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3027

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

304

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3047

create_gpr_user(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3057

obj = i915_gem_object_create_internal(engine->i915, 4096);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3081

*cs++ = CS_GPR(engine, 0);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3102

*cs++ = CS_GPR(engine, 2 * i);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3147

create_gpr_client(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3156

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3170

batch = create_gpr_user(engine, vma, offset);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3188

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3207

static int preempt_user(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3218

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3238

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3250

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

328

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3280

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3285

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3288

if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3291

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3301

rq = create_gpr_client(engine, global,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3313

err = preempt_user(engine, global, i);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3320

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3336

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3369

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3396

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3400

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3403

rq = spinner_create_request(&spin_lo, ctx_lo, engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3417

rq = igt_request_alloc(ctx_hi, engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

342

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3425

while (READ_ONCE(engine->execlists.pending[0]))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3428

saved_timeout = engine->props.preempt_timeout_ms;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3429

engine->props.preempt_timeout_ms = 1; /* in ms, -> 1 jiffy */

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3434

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3435

engine->props.preempt_timeout_ms = saved_timeout;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3472

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

348

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

351

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3510

rq = igt_request_alloc(ctx, smoke->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3519

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

354

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3559

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3570

for_each_engine(engine, smoke->gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3572

arg[id].engine = engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

358

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3588

for_each_engine(engine, smoke->gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3616

for_each_engine(smoke->engine, smoke->gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

363

tmp = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3744

err = igt_live_test_begin(&t, gt->i915, __func__, ve[0]->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3790

__func__, ve[0]->engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3795

__func__, ve[0]->engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3822

nctx, ve[0]->engine->name, ktime_to_ns(times[0]),

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3871

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3879

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3880

err = nop_virtual_engine(gt, &engine, 1, 1, 0);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3883

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3935

err = igt_live_test_begin(&t, gt->i915, __func__, ve->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3957

__func__, ve->engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3962

__func__, ve->engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3971

if (request[n]->engine != siblings[nsibling - n - 1]) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3973

request[n]->engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4073

__func__, rq->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

415

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

418

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

42

static int wait_for_submit(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

420

engine->name, n,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4220

err = igt_live_test_begin(&t, gt->i915, __func__, ve->engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4225

struct intel_engine_cs *engine = siblings[n % nsibling];

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4245

*cs++ = CS_GPR(engine, n);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4250

*cs++ = CS_GPR(engine, (n + 1) % NUM_GPR_DW);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4257

rq->execution_mask = engine->mask;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4334

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4372

engine = rq->engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4373

GEM_BUG_ON(engine == ve->engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4376

err = engine_lock_reset_tasklet(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4380

engine->sched_engine->tasklet.callback(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4381

GEM_BUG_ON(execlists_active(&engine->execlists) != rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4384

spin_lock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4385

__unwind_incomplete_requests(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4386

spin_unlock_irq(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4387

GEM_BUG_ON(rq->engine != engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4390

execlists_hold(engine, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4393

__intel_engine_reset_bh(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4397

engine_unlock_reset_tasklet(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4403

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

441

err = wait_for_submit(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4411

execlists_unhold(engine, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

4414

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

445

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

450

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

455

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

464

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

47

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

478

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

491

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

497

if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

502

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

553

static int engine_lock_reset_tasklet(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

555

tasklet_disable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

558

if (test_and_set_bit(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

559

&engine->gt->reset.flags)) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

561

tasklet_enable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

563

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

57

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

570

static void engine_unlock_reset_tasklet(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

572

clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

573

&engine->gt->reset.flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

576

tasklet_enable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

58

if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

582

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

599

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

603

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

609

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

626

err = engine_lock_reset_tasklet(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

630

engine->sched_engine->tasklet.callback(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

631

GEM_BUG_ON(execlists_active(&engine->execlists) != rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

634

execlists_hold(engine, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

637

__intel_engine_reset_bh(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

640

engine_unlock_reset_tasklet(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

645

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

653

execlists_unhold(engine, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

656

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

663

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

68

static int wait_for_reset(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

689

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

706

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

710

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

722

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

735

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

736

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

76

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

762

err = wait_for_submit(engine, client[0], HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

765

engine->name);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

773

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

778

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

78

if (READ_ONCE(engine->execlists.pending[0]))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

785

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

788

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

803

engine->name, p - phases,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

809

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

857

semaphore_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

863

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

872

if (rq->engine->emit_init_breadcrumb)

sys/dev/pci/drm/i915/gt/selftest_execlists.c

873

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

888

release_queue(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

898

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

90

engine->name,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

919

engine->sched_engine->schedule(rq, &attr);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

932

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_execlists.c

941

for_each_engine(engine, outer->gt, id) {

sys/dev/pci/drm/i915/gt/selftest_execlists.c

942

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

948

rq = semaphore_queue(engine, vma, n++);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

980

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

104

if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

107

measure_clocks(engine, &cycles, &dt);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

109

time = intel_gt_clock_interval_to_ns(engine->gt, cycles);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

110

expected = intel_gt_ns_to_clock_interval(engine->gt, dt);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

113

engine->name, cycles, time, dt, expected,

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

114

engine->gt->clock_frequency / 1000);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

118

engine->name);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

125

engine->name);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

39

static u32 read_timestamp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

41

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

44

ENGINE_READ_FW(engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

47

return ENGINE_READ_FW(engine, RING_TIMESTAMP_UDW);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

49

return ENGINE_READ_FW(engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

52

static void measure_clocks(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

61

cycles[i] = -read_timestamp(engine);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

66

cycles[i] += read_timestamp(engine);

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

82

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_gt_pm.c

98

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1000

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1005

if (!wait_for_idle(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1007

engine->name, test_name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1019

if (other == engine && !(flags & TEST_SELF))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1022

if (other != engine && !(flags & TEST_OTHERS))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1025

threads[tmp].engine = other;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1033

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

104

hang_create_request(struct hang *h, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1044

st_engine_heartbeat_disable_no_pm(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1052

err = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1055

pr_err("[%s] Modify policy failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1060

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1064

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1076

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1077

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1084

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1088

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1091

engine->name, test_name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1101

engine->name, rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1110

engine->name, test_name,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1127

engine->name, test_name,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1130

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1131

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1144

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1146

if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1152

engine->name, test_name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1153

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1154

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1161

err2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1163

pr_err("[%s] Restore policy failed: %d!\n", engine->name, err2);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1170

st_engine_heartbeat_enable_no_pm(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1173

engine->name, test_name, count);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1177

reported = i915_reset_engine_count(global, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1178

reported -= threads[engine->id].resets;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1181

engine->name, test_name, count, reported);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1208

if (other->uabi_class != engine->uabi_class &&

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1233

pr_err("[%s] Flush failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1299

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1306

engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1308

if (!engine || !intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1317

pr_err("[%s] Hang init failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1321

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1324

pr_err("[%s] Create hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1336

intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1431

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1443

engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1445

if (!engine || !intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1452

pr_err("[%s] Hang init failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1459

pr_err("[%s] Create object failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1474

pr_err("[%s] VMA instance failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1478

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1481

pr_err("[%s] Create hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1493

pr_err("[%s] VMA pin failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1509

pr_err("[%s] Move to active failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1525

intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1536

pr_err("[%s] Thread spawn failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1548

intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1556

fake_hangcheck(gt, rq->engine->mask);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

157

rq = igt_request_alloc(h->ctx, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1621

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1624

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1625

if (engine == exclude)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1628

if (!wait_for_idle(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1639

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1652

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1657

bool using_guc = intel_engine_uses_guc(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1659

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1663

err = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1666

pr_err("[%s] Modify policy failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1671

prev = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1674

pr_err("[%s] Create 'prev' hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1686

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1689

pr_err("[%s] Create hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1706

err = wait_for_others(gt, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1709

__func__, engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1722

__func__, engine->name,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1724

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1725

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1769

engine->name, count);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1772

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1778

int err2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1782

__func__, __LINE__, engine->name, err2);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1791

pr_err("[%s] Flush failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1811

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1817

engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1824

if (!engine || !intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1829

pr_err("[%s] Hang init failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1833

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1836

pr_err("[%s] Create hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1848

intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1859

intel_gt_handle_error(gt, engine->mask, 0, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1876

static int __igt_atomic_reset_engine(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1880

struct tasklet_struct * const t = &engine->sched_engine->tasklet;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1884

engine->name, mode, p->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1892

err = __intel_engine_reset_bh(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1904

engine->name, mode, p->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1909

static int igt_atomic_reset_engine(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1916

err = __igt_atomic_reset_engine(engine, p, "idle");

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1920

err = hang_init(&h, engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1922

pr_err("[%s] Hang init failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1926

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1929

pr_err("[%s] Create hang request failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1937

err = __igt_atomic_reset_engine(engine, p, "active");

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1940

__func__, engine->name,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1942

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1949

intel_wedge_on_timeout(&w, engine->gt, HZ / 20 /* 50ms */)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1951

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1982

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1985

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1986

err = igt_atomic_reset_engine(engine, p);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

226

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

228

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

229

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

238

err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

288

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

299

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

303

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

306

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

310

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

317

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

333

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

343

static bool wait_for_idle(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

345

return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

352

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

363

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

367

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

370

pr_err("[%s] Create context failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

381

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

396

pr_err("[%s] GT is wedged!\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

403

engine->name, i915_reset_count(global), reset_count, count);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

410

pr_err("[%s] Flush failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

428

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

436

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

442

if (intel_engine_uses_guc(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

450

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

452

pr_err("[%s] Create context failed: %pe!\n", engine->name, ce);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

457

reset_engine_count = i915_reset_engine_count(global, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

460

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

466

if (!wait_for_idle(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

468

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

480

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

483

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

487

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

498

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

501

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

511

if (i915_reset_engine_count(global, engine) !=

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

514

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

520

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

522

pr_info("%s(%s): %d resets\n", __func__, engine->name, count);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

534

static void force_reset_timeout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

536

engine->reset_timeout.probability = 999;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

537

atomic_set(&engine->reset_timeout.times, -1);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

540

static void cancel_reset_timeout(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

542

memset(&engine->reset_timeout, 0, sizeof(engine->reset_timeout));

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

548

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

556

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

563

if (intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

566

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

568

pr_err("[%s] Create context failed: %pe!\n", engine->name, ce);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

572

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

576

force_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

577

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

578

cancel_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

587

if (!wait_for_idle(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

589

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

601

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

604

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

608

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

626

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

629

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

635

force_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

636

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

637

cancel_reset_timeout(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

640

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

652

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

655

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

659

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

669

pr_info("%s(%s): %d resets\n", __func__, engine->name, count);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

672

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

687

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

703

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

706

bool using_guc = intel_engine_uses_guc(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

712

if (active && !intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

715

if (!wait_for_idle(engine)) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

717

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

723

reset_engine_count = i915_reset_engine_count(global, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

725

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

734

err = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

737

pr_err("[%s] Modify policy failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

742

rq = hang_create_request(&h, engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

746

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

758

intel_engine_dump(engine, &p,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

759

"%s\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

768

err = intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

771

engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

781

engine->name, rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

797

if (i915_reset_engine_count(global, engine) !=

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

800

engine->name);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

809

err2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

811

pr_err("[%s] Restore policy failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

818

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

820

engine->name, count, active ? "active" : "idle");

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

827

pr_err("[%s] Flush failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

856

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

877

rq->engine->name,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

882

intel_gt_set_wedged(rq->engine->gt);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

895

struct intel_engine_cs *engine = arg->engine;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

902

ce[count] = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

906

engine->name, count, arg->result);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

922

pr_err("[%s] Create request #%d failed: %d!\n", engine->name, idx, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

929

if (engine->sched_engine->schedule && arg->flags & TEST_PRIORITY) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

934

engine->sched_engine->schedule(rq[idx], &attr);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

939

pr_err("[%s] Request put failed: %d!\n", engine->name, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

950

pr_err("[%s] Request put #%ld failed: %d!\n", engine->name, count, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

967

struct intel_engine_cs *engine, *other;

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

993

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

996

bool using_guc = intel_engine_uses_guc(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1030

ce->engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1051

shmem_unpin_map(ce->engine->default_state, defaults);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1117

*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

115

rq = intel_engine_create_kernel_request(ce->engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1160

defaults = shmem_pin_map(ce->engine->default_state);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1189

ce->engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1199

*cs++ = safe_poison(hw[dw] & get_lri_mask(ce->engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1209

shmem_unpin_map(ce->engine->default_state, defaults);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1250

*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1270

static int compare_isolation(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1304

intel_gt_coherent_map_type(engine->gt,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1313

defaults = shmem_pin_map(ce->engine->default_state);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1342

engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

135

static int get_lri_mask(struct intel_engine_cs *engine, u32 lri)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1359

engine->name, dw,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1372

shmem_unpin_map(ce->engine->default_state, defaults);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

140

if (GRAPHICS_VER(engine->i915) < 12)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1410

static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1412

u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1418

A = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1422

B = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

143

switch (engine->class) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1477

__func__, engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1487

err = compare_isolation(engine, ref, result, A, poison);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1504

static bool skip_isolation(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1506

if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1509

if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1518

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1537

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1542

skip_isolation(engine))

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1545

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1549

result = __lrc_isolation(engine, poison[i]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1553

result = __lrc_isolation(engine, ~poison[i]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1557

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

159

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1627

setup_per_ctx_bb(ce, ce->engine, emit_per_ctx_bb_canary);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1629

setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1662

static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1667

a = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1674

b = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1686

GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1721

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1725

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1726

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1727

err = __lrc_wabb_ctx(engine, per_ctx);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1728

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

175

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1750

static void garbage_reset(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1753

const unsigned int bit = I915_RESET_ENGINE + engine->id;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1754

unsigned long *lock = &engine->gt->reset.flags;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1758

tasklet_disable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1761

__intel_engine_reset_bh(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1763

tasklet_enable(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1781

ce->engine->context_size -

sys/dev/pci/drm/i915/gt/selftest_lrc.c

179

if (!engine->default_state)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1799

static int __lrc_garbage(struct intel_engine_cs *engine, struct rnd_state *prng)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1805

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1815

if (wait_for_submit(engine, hang, HZ / 2)) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

182

hw = shmem_pin_map(engine->default_state);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1822

garbage_reset(engine, hang);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1824

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1828

engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1835

engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1850

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1861

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1865

if (!intel_has_reset_engine(engine->gt))

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1868

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1870

err = __lrc_garbage(engine, &prng);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1874

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1885

static int __live_pphwsp_runtime(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1892

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

190

engine->kernel_context, engine, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1923

pr_err("%s: request not completed!\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1927

igt_flush_test(engine->i915);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1930

engine->name,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1937

engine->name,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1954

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1963

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1964

err = __live_pphwsp_runtime(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

204

engine->name, lri, dw);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

211

engine->name, dw, lri);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

218

engine->name, dw, lri, lrc[dw]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

233

lri_mask = get_lri_mask(engine, lri);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

244

engine->name, dw, offset, lrc[dw]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

259

pr_info("%s: HW register image:\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

262

pr_info("%s: SW register image:\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

266

shmem_unpin_map(engine->default_state, hw);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

27

#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

289

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

298

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

305

i915_mmio_reg_offset(RING_START(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

310

i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

315

i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

320

i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

325

i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

326

lrc_ring_mi_mode(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

330

i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

335

i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

336

lrc_ring_wa_bb_per_ctx(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

340

i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

341

lrc_ring_indirect_ptr(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

345

i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

346

lrc_ring_indirect_offset(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

350

i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

355

i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

356

lrc_ring_gpr0(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

360

i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

361

lrc_ring_cmd_buf_cctl(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

365

i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

366

lrc_ring_bb_offset(engine),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

373

if (!engine->default_state)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

376

hw = shmem_pin_map(engine->default_state);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

388

engine->name,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

397

shmem_unpin_map(engine->default_state, hw);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

403

static int __live_lrc_state(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

419

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

445

*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

452

*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

463

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

480

engine->name, n, cs[n], expected[n]);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

506

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

520

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

521

err = __live_lrc_state(engine, scratch);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

53

static int wait_for_submit(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

551

*cs++ = CS_GPR(ce->engine, n);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

568

i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

58

tasklet_hi_schedule(&engine->sched_engine->tasklet);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

598

*cs++ = CS_GPR(ce->engine, n);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

615

static int __live_lrc_gpr(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

619

u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

626

if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/gt/selftest_lrc.c

629

err = gpr_make_dirty(engine->kernel_context);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

633

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

643

err = wait_for_submit(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

648

err = gpr_make_dirty(engine->kernel_context);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

652

err = emit_semaphore_signal(engine->kernel_context, slot);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

656

err = wait_for_submit(engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

678

engine->name,

sys/dev/pci/drm/i915/gt/selftest_lrc.c

68

intel_engine_flush_submission(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

69

if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq))

sys/dev/pci/drm/i915/gt/selftest_lrc.c

700

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

714

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

715

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

717

err = __live_lrc_gpr(engine, scratch, false);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

721

err = __live_lrc_gpr(engine, scratch, true);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

726

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

741

i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

788

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_lrc.c

800

u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

810

err = wait_for_submit(rq->engine, rq, HZ / 2);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

82

i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/gt/selftest_lrc.c

831

arg->engine->name, preempt ? "preempt" : "simple",

sys/dev/pci/drm/i915/gt/selftest_lrc.c

839

arg->engine->name, preempt ? "preempt" : "simple",

sys/dev/pci/drm/i915/gt/selftest_lrc.c

879

for_each_engine(data.engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_lrc.c

882

st_engine_heartbeat_disable(data.engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

887

tmp = intel_context_create(data.engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

915

st_engine_heartbeat_enable(data.engine);

sys/dev/pci/drm/i915/gt/selftest_lrc.c

989

defaults = shmem_pin_map(ce->engine->default_state);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

151

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

157

if (HAS_64K_PAGES(ce->engine->i915))

sys/dev/pci/drm/i915/gt/selftest_migrate.c

174

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/selftest_migrate.c

175

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

194

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

203

err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

263

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

44

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

492

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

514

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

550

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

877

ce->engine->name, sz >> 10,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

960

ce->engine->name, sz >> 10,

sys/dev/pci/drm/i915/gt/selftest_mocs.c

134

struct intel_gt *gt = rq->engine->gt;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

143

addr = mocs_offset(rq->engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

160

static int check_mocs_table(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_mocs.c

173

engine->name, i, **vaddr, expect);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

192

static int check_l3cc_table(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_mocs.c

205

if (!mcr_range(engine->i915, reg) && **vaddr != expect) {

sys/dev/pci/drm/i915/gt/selftest_mocs.c

207

engine->name, i, **vaddr, expect);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

238

if (!err && ce->engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

24

static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

250

err = check_mocs_table(ce->engine, arg->mocs, &vaddr);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

251

if (!err && ce->engine->class == RENDER_CLASS)

sys/dev/pci/drm/i915/gt/selftest_mocs.c

252

err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

263

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

274

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_mocs.c

275

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

276

err = check_mocs_engine(&mocs, engine->kernel_context);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

277

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

28

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

289

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

300

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_mocs.c

303

ce = mocs_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

327

err = igt_spinner_init(&spin, ce->engine->gt);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

339

err = intel_engine_reset(ce->engine, reason);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

354

struct intel_gt *gt = ce->engine->gt;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

359

err = intel_engine_reset(ce->engine, "mocs");

sys/dev/pci/drm/i915/gt/selftest_mocs.c

378

intel_gt_reset(gt, ce->engine->mask, "mocs");

sys/dev/pci/drm/i915/gt/selftest_mocs.c

391

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_mocs.c

403

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_mocs.c

404

bool using_guc = intel_engine_uses_guc(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

409

err = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_mocs.c

414

ce = mocs_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

420

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

424

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_mocs.c

428

err2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

194

struct intel_engine_cs *engine, **engines;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

199

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/selftest_rc6.c

209

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/selftest_rc6.c

210

engines[n++] = engine;

sys/dev/pci/drm/i915/gt/selftest_rc6.c

235

struct intel_engine_cs *engine = engines[n];

sys/dev/pci/drm/i915/gt/selftest_rc6.c

242

i915_reset_engine_count(error, engine);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

246

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

252

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

254

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_rc6.c

269

engine->name, READ_ONCE(*res));

sys/dev/pci/drm/i915/gt/selftest_rc6.c

272

i915_reset_engine_count(error, engine)) {

sys/dev/pci/drm/i915/gt/selftest_rc6.c

274

engine->name);

sys/dev/pci/drm/i915/gt/selftest_reset.c

116

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_reset.c

117

if (mask & engine->mask)

sys/dev/pci/drm/i915/gt/selftest_reset.c

118

intel_engine_reset(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_reset.c

193

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_reset.c

200

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_reset.c

201

err = __igt_reset_stolen(gt, engine->mask, engine->name);

sys/dev/pci/drm/i915/gt/selftest_reset.c

25

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_reset.c

309

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_reset.c

329

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_reset.c

330

struct tasklet_struct *t = &engine->sched_engine->tasklet;

sys/dev/pci/drm/i915/gt/selftest_reset.c

334

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_reset.c

338

engine->name, p->name);

sys/dev/pci/drm/i915/gt/selftest_reset.c

343

err = __intel_engine_reset_bh(engine, NULL);

sys/dev/pci/drm/i915/gt/selftest_reset.c

351

engine->name, p->name);

sys/dev/pci/drm/i915/gt/selftest_reset.c

356

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_reset.c

58

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_reset.c

62

if (!(mask & engine->mask))

sys/dev/pci/drm/i915/gt/selftest_reset.c

65

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_reset.c

68

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

104

static int mixed_contexts_sync(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

111

err = context_sync(engine->kernel_context);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

122

err = new_context_sync(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

133

err = new_context_sync(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

147

static int double_context_sync_00(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

152

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

16

obj = i915_gem_object_create_internal(engine->i915, 4096);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

174

static int kernel_context_sync_00(struct intel_engine_cs *engine, u32 *result)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

179

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

189

err = context_sync(engine->kernel_context);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

20

vma = i915_vma_instance(obj, engine->gt->vm, NULL);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

205

static int __live_ctx_switch_wa(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

211

bb = create_wally(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

223

engine->wa_ctx.vma = bb;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

225

err = mixed_contexts_sync(engine, result);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

229

err = double_context_sync_00(engine, result);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

233

err = kernel_context_sync_00(engine, result);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

238

intel_context_put(engine->wa_ctx.vma->private);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

239

i915_vma_unpin_and_release(&engine->wa_ctx.vma, I915_VMA_RELEASE_MAP);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

246

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

262

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

266

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

272

saved_wa = fetch_and_zero(&engine->wa_ctx.vma);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

274

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

275

err = __live_ctx_switch_wa(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

276

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

280

engine->wa_ctx.vma = saved_wa;

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

44

if (GRAPHICS_VER(engine->i915) >= 6) {

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

47

} else if (GRAPHICS_VER(engine->i915) >= 4) {

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

61

vma->private = intel_context_create(engine); /* dummy residuals */

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

89

static int new_context_sync(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

9

static struct i915_vma *create_wally(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_ring_submission.c

94

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1001

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1008

engine->name, rps->pm_iir,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1026

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1055

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

1058

intel_gt_pm_wait_for_idle(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1061

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1063

err = __rps_up_interrupt(rps, engine, &spin);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1065

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1069

intel_gt_pm_wait_for_idle(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1074

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1077

err = __rps_down_interrupt(rps, engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1080

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1138

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1162

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

1169

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_rps.c

1172

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1175

engine->kernel_context,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1178

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1187

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1189

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1190

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1202

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1205

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1218

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1241

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

1264

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

1271

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_rps.c

1278

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1283

engine->kernel_context,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1303

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

1310

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

1316

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

224

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

245

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

250

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_rps.c

253

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

256

engine->kernel_context,

sys/dev/pci/drm/i915/gt/selftest_rps.c

259

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

268

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

270

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

271

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

294

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

326

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

334

engine->name, cycles, time, dt, expected,

sys/dev/pci/drm/i915/gt/selftest_rps.c

340

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

347

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

377

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

404

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

410

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_rps.c

413

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

416

engine->kernel_context,

sys/dev/pci/drm/i915/gt/selftest_rps.c

427

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

429

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

430

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

437

engine->name, rps->min_freq, read_cagf(rps));

sys/dev/pci/drm/i915/gt/selftest_rps.c

439

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

454

engine->name, rps->min_freq, read_cagf(rps));

sys/dev/pci/drm/i915/gt/selftest_rps.c

456

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

471

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

474

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

485

engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK);

sys/dev/pci/drm/i915/gt/selftest_rps.c

568

static u64 __measure_cs_frequency(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

57

create_spin_counter(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

573

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));

sys/dev/pci/drm/i915/gt/selftest_rps.c

576

dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;

sys/dev/pci/drm/i915/gt/selftest_rps.c

583

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

591

x[i] = __measure_cs_frequency(engine, 2);

sys/dev/pci/drm/i915/gt/selftest_rps.c

609

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

633

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

642

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

644

vma = create_spin_counter(engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

645

engine->kernel_context->vm, false,

sys/dev/pci/drm/i915/gt/selftest_rps.c

649

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

653

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

661

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_rps.c

668

if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)),

sys/dev/pci/drm/i915/gt/selftest_rps.c

671

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

676

min.count = measure_cs_frequency_at(rps, engine, &min.freq);

sys/dev/pci/drm/i915/gt/selftest_rps.c

679

max.count = measure_cs_frequency_at(rps, engine, &max.freq);

sys/dev/pci/drm/i915/gt/selftest_rps.c

68

#define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)

sys/dev/pci/drm/i915/gt/selftest_rps.c

682

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

694

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

703

count = measure_cs_frequency_at(rps, engine, &act);

sys/dev/pci/drm/i915/gt/selftest_rps.c

708

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

727

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

748

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_rps.c

772

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_rps.c

781

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

783

vma = create_spin_counter(engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

784

engine->kernel_context->vm, true,

sys/dev/pci/drm/i915/gt/selftest_rps.c

788

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

792

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

800

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_rps.c

809

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

820

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

832

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

846

engine->name,

sys/dev/pci/drm/i915/gt/selftest_rps.c

865

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_rps.c

896

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_rps.c

899

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/selftest_rps.c

903

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_rps.c

908

rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);

sys/dev/pci/drm/i915/gt/selftest_rps.c

917

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

919

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_rps.c

925

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

933

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

940

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

946

timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);

sys/dev/pci/drm/i915/gt/selftest_rps.c

957

engine->name, intel_rps_read_actual_frequency(rps));

sys/dev/pci/drm/i915/gt/selftest_rps.c

963

engine->name, rps->pm_iir,

sys/dev/pci/drm/i915/gt/selftest_rps.c

974

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_rps.c

976

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gt/selftest_rps.c

983

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

989

engine->name);

sys/dev/pci/drm/i915/gt/selftest_rps.c

994

timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

198

static int slpc_power(struct intel_gt *gt, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_slpc.c

228

engine->name,

sys/dev/pci/drm/i915/gt/selftest_slpc.c

239

engine->name);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

282

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_slpc.c

331

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_slpc.c

335

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_slpc.c

338

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

341

engine->kernel_context,

sys/dev/pci/drm/i915/gt/selftest_slpc.c

345

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

353

engine->name);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

355

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

356

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

373

if (gt->type != GT_MEDIA && (engine->class == VIDEO_DECODE_CLASS ||

sys/dev/pci/drm/i915/gt/selftest_slpc.c

374

engine->class == VIDEO_ENHANCEMENT_CLASS)) {

sys/dev/pci/drm/i915/gt/selftest_slpc.c

376

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

385

err = slpc_power(gt, engine);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

391

engine->name, max_act_freq);

sys/dev/pci/drm/i915/gt/selftest_slpc.c

404

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1019

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1025

err = create_watcher(&watcher[1], engine, SZ_512K);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1040

err = create_watcher(&watcher[0], engine, SZ_4K);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1044

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1159

pr_info("%s: simulated %lu wraps\n", engine->name, count);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1182

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1191

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1192

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1197

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1217

engine->name,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1246

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1260

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1269

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1275

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1304

engine->name,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1348

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1360

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1363

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1366

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1378

rq = checked_tl_write(tl, engine, count);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

1409

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

485

checked_tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)

sys/dev/pci/drm/i915/gt/selftest_timeline.c

503

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

529

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

546

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

547

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

550

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

562

rq = checked_tl_write(tl, engine, count);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

573

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

603

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

622

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

626

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

635

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

636

rq = checked_tl_write(tl, engine, count);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

637

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

673

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_timeline.c

694

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_timeline.c

699

if (!intel_engine_can_store_dword(engine))

sys/dev/pci/drm/i915/gt/selftest_timeline.c

702

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

782

const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));

sys/dev/pci/drm/i915/gt/selftest_timeline.c

874

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

879

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

987

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

130

err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

143

if (ce->engine->class == OTHER_CLASS)

sys/dev/pci/drm/i915/gt/selftest_tlb.c

151

ce->engine->name, va->obj->mm.region->name ?: "smem",

sys/dev/pci/drm/i915/gt/selftest_tlb.c

175

ce->engine->name);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

233

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_tlb.c

296

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_tlb.c

301

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_tlb.c

95

ce->engine->name, va->obj->mm.region->name ?: "smem",

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1006

static bool result_neq(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1009

if (a == b && !writeonly_reg(engine->i915, reg)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

101

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1019

check_whitelisted_registers(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

102

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1022

bool (*fn)(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1040

for (i = 0; i < engine->whitelist.count; i++) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1041

const struct i915_wa *wa = &engine->whitelist.list[i];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1047

if (!fn(engine, a[i], b[i], wa->reg))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1063

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1092

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1095

if (!engine->kernel_context->vm)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1098

if (!whitelist_writable_count(engine))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

110

result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1101

ce[0] = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1106

ce[1] = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1129

err = check_whitelisted_registers(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1142

err = check_whitelisted_registers(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1169

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1175

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1178

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1183

&lists->engine[id].wa_list,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1187

&lists->engine[id].ctx_wa_list,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1239

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

125

vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1260

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1262

bool using_guc = intel_engine_uses_guc(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1266

pr_info("Verifying after %s reset...\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1267

ret = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1272

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1285

ret = intel_engine_reset(engine, "live_workarounds:idle");

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1287

pr_err("%s: Reset failed while idle\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1298

ret = igt_spinner_init(&spin, engine->gt);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1311

pr_err("%s: Spinner failed to start\n", engine->name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1323

ret = intel_engine_reset(engine, "live_workarounds:active");

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1326

engine->name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1348

ret2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

146

if (GRAPHICS_VER(engine->i915) >= 8)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

178

get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

180

i915_reg_t reg = i < engine->whitelist.count ?

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

181

engine->whitelist.list[i].reg :

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

182

RING_NOPID(engine->mmio_base);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

188

print_results(const struct intel_engine_cs *engine, const u32 *results)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

193

u32 expected = get_whitelist_reg(engine, i);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

203

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

216

intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

219

if (intel_gt_is_wedged(engine->gt))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

231

u32 expected = get_whitelist_reg(engine, i);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

235

print_results(engine, vaddr);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

251

static int do_device_reset(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

253

intel_gt_reset(engine->gt, engine->mask, "live_workarounds");

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

257

static int do_engine_reset(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

259

return intel_engine_reset(engine, "live_workarounds");

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

262

static int do_guc_reset(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

269

switch_to_scratch_context(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

276

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

297

static int check_whitelist_across_reset(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

308

engine->whitelist.count, engine->name, name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

310

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

314

err = igt_spinner_init(&spin, engine->gt);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

324

err = switch_to_scratch_context(engine, &spin, &rq);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

335

with_intel_runtime_pm(engine->uncore->rpm, wakeref)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

336

err = reset(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

34

} engine[I915_NUM_ENGINES];

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

356

tmp = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

418

static bool wo_register(struct intel_engine_cs *engine, u32 reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

420

enum intel_platform platform = INTEL_INFO(engine->i915)->platform;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

436

static bool timestamp(const struct intel_engine_cs *engine, u32 reg)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

438

reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

459

static int whitelist_writable_count(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

461

int count = engine->whitelist.count;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

464

for (i = 0; i < engine->whitelist.count; i++) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

465

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

502

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

519

for (i = 0; i < engine->whitelist.count; i++) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

520

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

529

if (wo_register(engine, reg))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

532

if (timestamp(engine, reg))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

565

if (GRAPHICS_VER(engine->i915) >= 8)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

569

engine->name, reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

616

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

625

if (engine->emit_init_breadcrumb) { /* Be nice if we hang */

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

626

err = engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

64

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

640

err = engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

650

engine->name, reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

651

intel_gt_set_wedged(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

661

engine->name, reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

693

engine->name, err, reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

697

engine->name, reg, results[0]);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

700

engine->name, reg, results[0], rsvd);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

73

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

74

struct i915_wa_list *wal = &lists->engine[id].wa_list;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

747

if (igt_flush_test(engine->i915))

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

759

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

76

wa_init_start(wal, gt, "REF", engine->name);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

767

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

77

engine_init_workarounds(engine, wal);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

771

if (engine->whitelist.count == 0)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

774

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

790

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

797

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

798

if (engine->whitelist.count == 0)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

80

__intel_engine_init_ctx_wa(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

802

if (intel_engine_uses_guc(engine)) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

806

err = intel_selftest_modify_policy(engine, &saved,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

81

&lists->engine[id].ctx_wa_list,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

811

err = check_whitelist_across_reset(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

815

err2 = intel_selftest_restore_policy(engine, &saved);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

819

err = check_whitelist_across_reset(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

829

err = check_whitelist_across_reset(engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

845

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

859

if (GRAPHICS_VER(engine->i915) >= 8)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

862

cs = intel_ring_begin(rq, 4 * engine->whitelist.count);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

868

for (i = 0; i < engine->whitelist.count; i++) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

870

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

888

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

89

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

904

*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

905

for (i = 0; i < engine->whitelist.count; i++) {

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

906

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

92

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

920

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

928

if (engine->emit_init_breadcrumb) { /* Be nice if we hang */

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

929

err = engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

93

intel_wa_list_free(&lists->engine[id].wa_list);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

939

err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

984

static bool result_eq(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

987

if (a != b && !pardon_reg(engine->i915, reg)) {

sys/dev/pci/drm/i915/gt/sysfs_engines.c

126

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

128

return __caps_show(engine, engine->uabi_capabilities, buf, true);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

147

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

172

clamped = intel_clamp_max_busywait_duration_ns(engine, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

176

WRITE_ONCE(engine->props.max_busywait_duration_ns, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

184

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

186

return sysfs_emit(buf, "%lu\n", engine->props.max_busywait_duration_ns);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

19

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/sysfs_engines.c

195

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

197

return sysfs_emit(buf, "%lu\n", engine->defaults.max_busywait_duration_ns);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

207

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

223

clamped = intel_clamp_timeslice_duration_ms(engine, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

227

WRITE_ONCE(engine->props.timeslice_duration_ms, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

229

if (execlists_active(&engine->execlists))

sys/dev/pci/drm/i915/gt/sysfs_engines.c

230

set_timer_ms(&engine->execlists.timer, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

238

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

24

return container_of(kobj, struct kobj_engine, base)->engine;

sys/dev/pci/drm/i915/gt/sysfs_engines.c

240

return sysfs_emit(buf, "%lu\n", engine->props.timeslice_duration_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

249

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

251

return sysfs_emit(buf, "%lu\n", engine->defaults.timeslice_duration_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

261

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

278

clamped = intel_clamp_stop_timeout_ms(engine, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

282

WRITE_ONCE(engine->props.stop_timeout_ms, duration);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

289

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

291

return sysfs_emit(buf, "%lu\n", engine->props.stop_timeout_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

300

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

302

return sysfs_emit(buf, "%lu\n", engine->defaults.stop_timeout_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

312

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

329

clamped = intel_clamp_preempt_timeout_ms(engine, timeout);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

333

WRITE_ONCE(engine->props.preempt_timeout_ms, timeout);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

335

if (READ_ONCE(engine->execlists.pending[0]))

sys/dev/pci/drm/i915/gt/sysfs_engines.c

336

set_timer_ms(&engine->execlists.preempt, timeout);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

345

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

347

return sysfs_emit(buf, "%lu\n", engine->props.preempt_timeout_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

357

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

359

return sysfs_emit(buf, "%lu\n", engine->defaults.preempt_timeout_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

369

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

387

clamped = intel_clamp_heartbeat_interval_ms(engine, delay);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

391

err = intel_engine_set_heartbeat(engine, delay);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

401

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

403

return sysfs_emit(buf, "%lu\n", engine->props.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

412

struct intel_engine_cs *engine = kobj_to_engine(kobj);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

414

return sysfs_emit(buf, "%lu\n", engine->defaults.heartbeat_interval_ms);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

431

kobj_engine(struct kobject *dir, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/sysfs_engines.c

440

ke->engine = engine;

sys/dev/pci/drm/i915/gt/sysfs_engines.c

442

if (kobject_add(&ke->base, dir, "%s", engine->name)) {

sys/dev/pci/drm/i915/gt/sysfs_engines.c

468

ke->engine = parent->engine;

sys/dev/pci/drm/i915/gt/sysfs_engines.c

478

if (intel_engine_has_timeslices(ke->engine) &&

sys/dev/pci/drm/i915/gt/sysfs_engines.c

482

if (intel_engine_has_preempt_reset(ke->engine) &&

sys/dev/pci/drm/i915/gt/sysfs_engines.c

508

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/sysfs_engines.c

515

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/gt/sysfs_engines.c

518

kobj = kobj_engine(dir, engine);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

525

if (intel_engine_has_timeslices(engine) &&

sys/dev/pci/drm/i915/gt/sysfs_engines.c

529

if (intel_engine_has_preempt_reset(engine) &&

sys/dev/pci/drm/i915/gt/sysfs_engines.c

540

engine->name);

sys/dev/pci/drm/i915/gt/sysfs_engines.c

84

__caps_show(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/sysfs_engines.c

91

switch (engine->class) {

sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h

100

u32 engine; /* as per MAX_ENGINE_CLASS */

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

295

if (ce->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

296

err = ce->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c

305

err = ce->engine->emit_flush(rq, 0);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

214

struct intel_engine_cs *engine = gt->engine[GSC0];

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

226

ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

295

if (!gsc_uc_to_gt(gsc)->engine[GSC0]->default_state)

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

143

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

175

engine = rq->context->engine;

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

176

if (engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

177

err = engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

182

err = engine->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

186

err = ce->engine->emit_flush(rq, 0);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

65

if (ce->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

66

err = ce->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

76

err = ce->engine->emit_flush(rq, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc.h

529

void intel_guc_find_hung_context(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1069

struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1071

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1072

u8 guc_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1074

engine_usage.engines[guc_class][ilog2(engine->logical_mask)]);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

232

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

241

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

242

u8 guc_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

244

info_map_write(info_map, mapping_table[guc_class][ilog2(engine->logical_mask)],

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

245

engine->instance);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

388

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

390

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

391

const u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

392

struct i915_wa_list *wal = &engine->wa_list;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

407

if ((engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

408

CCS_MASK(engine->gt))

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

427

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

432

if (GRAPHICS_VER(engine->i915) >= 12) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

448

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

454

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

457

ret = guc_mmio_regset_init(&temp_set, engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

480

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

490

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

495

GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

497

guc_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

501

ads.reg_state_list[guc_class][engine->instance].address,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

504

ads.reg_state_list[guc_class][engine->instance].count,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

510

ads.reg_state_list[guc_class][engine->instance].address,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

513

ads.reg_state_list[guc_class][engine->instance].count,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

530

if (gt->engine[GSC0])

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

532

BIT(gt->engine[GSC0]->instance));

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

614

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

617

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

618

if (engine->class != engine_class)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

621

if (!engine->default_state)

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

624

return engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

632

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

659

engine = find_engine_state(gt, engine_class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

660

if (!engine) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

674

uao_read_to_iosys_map(engine->default_state, 0, &guc->ads_map,

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.h

22

struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1437

if (!cap || !ee->engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1440

guc = gt_to_guc(ee->engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1443

ee->engine->name);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1534

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1539

if (!gt || !ce || !engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1552

if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(engine->guc_id) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1553

n->eng_class == GUC_ID_TO_ENGINE_CLASS(engine->guc_id) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1584

if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

1585

n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

212

(reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL))

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

230

(reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL))

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

285

newlist->engine = rootlist->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

614

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

633

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

641

engine->class, &tmp, true)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

645

engine->class, &tmp, true)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.h

25

struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1065

static void cs_irq_handler(struct intel_engine_cs *engine, u16 iir)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1068

intel_engine_signal_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1136

intel_engine_signal_breadcrumbs(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1228

static void __get_engine_usage_record(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1231

struct iosys_map rec_map = intel_guc_engine_usage_record_map(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1246

static void __set_engine_usage_record(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1249

struct iosys_map rec_map = intel_guc_engine_usage_record_map(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1261

static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1263

struct intel_engine_guc_stats *stats = &engine->stats.guc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1264

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1269

__get_engine_usage_record(engine, &last_switch, &ctx_id, &total);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1321

static ktime_t guc_engine_busyness(struct intel_engine_cs *engine, ktime_t *now)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1323

struct intel_engine_guc_stats stats_saved, *stats = &engine->stats.guc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1324

struct i915_gpu_error *gpu_error = &engine->i915->gpu_error;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1325

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1362

guc_update_engine_gt_clks(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1440

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1448

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1449

struct intel_engine_guc_stats *stats = &engine->stats.guc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1451

guc_update_engine_gt_clks(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1472

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1477

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1478

engine->stats.guc.running = false;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1485

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1495

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1496

guc_update_engine_gt_clks(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1588

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1597

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1598

__set_engine_usage_record(engine, 0, 0xffffffff, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1755

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1759

for_each_engine_masked(engine, ve->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1761

return engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1769

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1771

if (intel_engine_is_virtual(engine))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1772

engine = guc_virtual_get_sibling(engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1774

return engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1779

struct intel_engine_cs *engine = __context_to_physical_engine(ce);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1795

lrc_init_regs(ce, engine, true);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1798

lrc_update_regs(ce, engine, head);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1801

static void guc_engine_reset_prepare(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1807

if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1808

intel_engine_stop_cs(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1809

intel_engine_wait_for_pending_mi_fw(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1813

static void guc_reset_nop(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1817

static void guc_rewind_nop(struct intel_engine_cs *engine, bool stalled)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1828

ce->engine->sched_engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1895

guilty = stalled & ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2240

struct i915_sched_engine *sched_engine = rq->engine->sched_engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2250

struct i915_sched_engine *sched_engine = rq->engine->sched_engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2251

struct intel_guc *guc = gt_to_guc(rq->engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2424

ce->engine->props.timeslice_duration_ms <<

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2716

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2717

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2726

GEM_BUG_ON(overflows_type(engine->props.timeslice_duration_ms * 1000,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2728

GEM_BUG_ON(overflows_type(engine->props.preempt_timeout_ms * 1000,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2730

execution_quantum = engine->props.timeslice_duration_ms * 1000;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2731

preemption_timeout = engine->props.preempt_timeout_ms * 1000;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2743

if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2758

static void guc_context_policy_init_v69(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2763

if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2767

GEM_BUG_ON(overflows_type(engine->props.timeslice_duration_ms * 1000,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2769

GEM_BUG_ON(overflows_type(engine->props.preempt_timeout_ms * 1000,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2771

desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2772

desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2797

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2798

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2803

GEM_BUG_ON(!engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2814

desc->engine_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2815

desc->engine_submit_mask = engine->logical_mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2819

guc_context_policy_init_v69(engine, desc);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2852

engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2856

guc_context_policy_init_v69(engine, desc);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2866

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2867

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2870

GEM_BUG_ON(!engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2881

info->engine_class = engine_class_to_guc_class(engine->class);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2882

info->engine_submit_mask = engine->logical_mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2889

if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2928

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2929

struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2930

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2994

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2998

return lrc_pre_pin(ce, engine, ww, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3002

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3014

return lrc_pin(ce, engine, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3021

return __guc_context_pre_pin(ce, ce->engine, ww, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3026

int ret = __guc_context_pin(ce, ce->engine, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3029

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3043

intel_engine_pm_put_async(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3125

struct intel_runtime_pm *runtime_pm = ce->engine->uncore->rpm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3181

struct intel_runtime_pm *runtime_pm = ce->engine->uncore->rpm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3260

&ce->engine->gt->i915->runtime_pm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3276

intel_engine_signal_breadcrumbs(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3313

struct intel_runtime_pm *runtime_pm = &ce->engine->gt->i915->runtime_pm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3484

if (intel_engine_is_virtual(ce->engine)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3619

return lrc_alloc(ce, ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3700

struct intel_guc *guc = &ce->engine->gt->uc.guc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3813

might_lock(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3902

ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3993

struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3995

return __guc_context_pre_pin(ce, engine, ww, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4000

struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4001

int ret = __guc_context_pin(ce, engine, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4002

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4005

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4006

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

401

return gt_to_guc(ce->engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4013

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4014

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4023

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4024

intel_engine_pm_put_async(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4029

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4030

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4032

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4033

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4040

intel_engine_mask_t tmp, mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4041

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4043

for_each_engine_masked(engine, ce->engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4044

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4051

struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4053

return lrc_alloc(ce, engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4084

struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4089

GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4095

return __guc_context_pin(ce, engine, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4100

struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4103

GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4106

return __guc_context_pin(ce, engine, vaddr);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4116

GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4127

GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4136

GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4253

parent->engine->emit_bb_start =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4255

parent->engine->emit_fini_breadcrumb =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4257

parent->engine->emit_fini_breadcrumb_dw =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4260

ce->engine->emit_bb_start =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4262

ce->engine->emit_fini_breadcrumb =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4264

ce->engine->emit_fini_breadcrumb_dw = 16;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4300

static void guc_init_breadcrumbs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4314

engine->gt->engine_class[engine->class][i];

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4317

if (engine->breadcrumbs != sibling->breadcrumbs) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4318

intel_breadcrumbs_put(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4319

engine->breadcrumbs =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4326

if (engine->breadcrumbs) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4327

engine->breadcrumbs->engine_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4328

engine->breadcrumbs->irq_enable = guc_irq_enable_breadcrumbs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4329

engine->breadcrumbs->irq_disable = guc_irq_disable_breadcrumbs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4371

static void sanitize_hwsp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4375

list_for_each_entry(tl, &engine->status_page.timelines, engine_link)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4379

static void guc_sanitize(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4391

memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4398

sanitize_hwsp(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4401

drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4403

intel_engine_reset_pinned_contexts(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4406

static void setup_hwsp(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4408

intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4410

ENGINE_WRITE_FW(engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4412

i915_ggtt_offset(engine->status_page.vma));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4415

static void start_engine(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4417

ENGINE_WRITE_FW(engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4421

ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4422

ENGINE_POSTING_READ(engine, RING_MI_MODE);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4425

static int guc_resume(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4427

assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4429

intel_mocs_init_engine(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4431

intel_breadcrumbs_reset(engine->breadcrumbs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4433

setup_hwsp(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4434

start_engine(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4436

if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4437

xehp_enable_ccs_engines(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4447

static void guc_set_default_submission(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4449

engine->submit_request = guc_submit_request;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4484

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4504

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4507

list_for_each_entry(ce, &engine->pinned_contexts_list,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4521

static void guc_release(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4523

engine->sanitize = NULL; /* no longer in control, nothing to sanitize */

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4525

intel_engine_cleanup_common(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4526

lrc_fini_wa_ctx(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4529

static void virtual_guc_bump_serial(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4532

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4534

for_each_engine_masked(e, engine->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4538

static void guc_default_vfuncs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4542

engine->resume = guc_resume;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4544

engine->cops = &guc_context_ops;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4545

engine->request_alloc = guc_request_alloc;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4546

engine->add_active_request = add_to_context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4547

engine->remove_active_request = remove_from_context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4549

engine->sched_engine->schedule = i915_schedule;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4551

engine->reset.prepare = guc_engine_reset_prepare;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4552

engine->reset.rewind = guc_rewind_nop;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4553

engine->reset.cancel = guc_reset_nop;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4554

engine->reset.finish = guc_reset_nop;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4556

engine->emit_flush = gen8_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4557

engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4558

engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4559

if (GRAPHICS_VER(engine->i915) >= 12) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4560

engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4561

engine->emit_flush = gen12_emit_flush_xcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4563

engine->set_default_submission = guc_set_default_submission;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4564

engine->busyness = guc_engine_busyness;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4566

engine->flags |= I915_ENGINE_SUPPORTS_STATS;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4567

engine->flags |= I915_ENGINE_HAS_PREEMPTION;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4568

engine->flags |= I915_ENGINE_HAS_TIMESLICES;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4571

if (engine->class == COMPUTE_CLASS)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4572

if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4573

IS_DG2(engine->i915))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4574

engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4578

if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4579

IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4580

engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4590

engine->emit_bb_start = gen8_emit_bb_start;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4591

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4592

engine->emit_bb_start = xehp_emit_bb_start;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4595

static void rcs_submission_override(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4597

switch (GRAPHICS_VER(engine->i915)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4599

engine->emit_flush = gen12_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4600

engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4603

engine->emit_flush = gen11_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4604

engine->emit_fini_breadcrumb = gen11_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4607

engine->emit_flush = gen8_emit_flush_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4608

engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4613

static inline void guc_default_irqs(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4615

engine->irq_keep_mask = GT_RENDER_USER_INTERRUPT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4616

intel_engine_set_irq_handler(engine, cs_irq_handler);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4630

int intel_guc_submission_setup(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4632

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4633

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4657

i915_sched_engine_put(engine->sched_engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4658

engine->sched_engine = i915_sched_engine_get(guc->sched_engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4660

guc_default_vfuncs(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4661

guc_default_irqs(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4662

guc_init_breadcrumbs(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4664

if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4665

rcs_submission_override(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4667

lrc_init_wa_ctx(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4670

engine->sanitize = guc_sanitize;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

4671

engine->release = guc_release;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5081

&ce->engine->gt->i915->runtime_pm;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5172

intel_engine_signal_breadcrumbs(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5190

if (intel_engine_is_virtual(ce->engine)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5192

intel_engine_mask_t tmp, virtual_mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5195

for_each_engine_masked(e, ce->engine->gt, virtual_mask, tmp) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5208

ce->guc_id.id, ce->engine->name);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5212

intel_engine_set_hung_context(ce->engine, ce);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5213

engine_mask = ce->engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5214

i915_increase_reset_engine_count(&i915->gpu_error, ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5223

struct i915_sched_engine *sched_engine = ce->engine->sched_engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5225

__guc_reset_context(ce, ce->engine->mask);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5238

ce->guc_id.id, ce->engine->name,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5328

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5337

for_each_engine_masked(engine, gt, reset_fail_mask, id)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5338

intel_guc_find_hung_context(engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5350

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5364

engine = intel_guc_lookup_engine(guc, guc_class, instance);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5365

if (unlikely(!engine)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5375

guc_class, instance, engine->name, reason);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5378

guc->submission_state.reset_fail_mask |= engine->mask;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5390

void intel_guc_find_hung_context(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5392

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5414

if (intel_engine_is_virtual(ce->engine)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5415

if (!(ce->engine->mask & engine->mask))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5418

if (ce->engine != engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5434

intel_engine_set_hung_context(engine, ce);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5450

void intel_guc_dump_active_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5454

struct intel_guc *guc = gt_to_guc(engine->gt);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5473

if (intel_engine_is_virtual(ce->engine)) {

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5474

if (!(ce->engine->mask & engine->mask))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5477

if (ce->engine != engine)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5597

if (ce->engine->emit_bb_start ==

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5795

(ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5796

cs += ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5816

ce->engine->emit_fini_breadcrumb_dw != cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5871

(ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5872

cs += ce->engine->emit_fini_breadcrumb_dw - NON_SKIP_LEN;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5892

ce->engine->emit_fini_breadcrumb_dw != cs);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6004

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6007

for_each_engine_masked(engine, ve->gt, mask, tmp)

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

6008

if (READ_ONCE(engine->props.heartbeat_interval_ms))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

705

lockdep_assert_held(&rq->engine->sched_engine->lock);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

713

intel_engine_signal_breadcrumbs(ce->engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h

23

int intel_guc_submission_setup(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.h

28

void intel_guc_dump_active_requests(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

113

intel_gt_handle_error(engine->gt, -1, 0, "selftest reset");

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

150

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

163

engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

168

ce[context_index] = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

175

ret = igt_spinner_init(&spin, engine->gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

195

ce[++context_index] = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

317

struct intel_engine_cs *engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

321

if (!engine)

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

326

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

333

ret = igt_spinner_init(&spin, engine->gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

56

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

63

engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc.c

67

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

124

intel_engine_set_heartbeat(engine, old_beat);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

127

rq = nop_request(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

15

static struct i915_request *nop_request(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

19

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

39

struct intel_engine_cs *engine = intel_selftest_find_any_engine(gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

44

if (!engine)

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

55

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

64

old_beat = engine->props.heartbeat_interval_ms;

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

65

ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_hangcheck.c

71

ret = igt_spinner_init(&spin, engine->gt);

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

35

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

39

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

40

if (engine->class != class)

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

43

siblings[i++] = engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1016

if (GRAPHICS_VER(s->engine->i915) == 9 &&

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1054

if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1055

if (s->engine->id == BCS0 &&

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1076

if (IS_BROADWELL(s->engine->i915))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1104

if (IS_BROADWELL(s->engine->i915))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1216

hws_pga = s->vgpu->hws_pga[s->engine->id];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1230

set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1237

set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1290

struct drm_i915_private *dev_priv = s->engine->i915;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1337

struct drm_i915_private *dev_priv = s->engine->i915;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1402

if (GRAPHICS_VER(s->engine->i915) >= 9) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1425

struct drm_i915_private *dev_priv = s->engine->i915;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1457

if (IS_BROADWELL(s->engine->i915))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1459

if (GRAPHICS_VER(s->engine->i915) >= 9)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1744

hws_pga = s->vgpu->hws_pga[s->engine->id];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1753

set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1803

!(s->vgpu->scan_nonprivbb & s->engine->mask))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1836

info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1839

cmd, get_opcode(cmd, s->engine),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1841

s->engine->name, s->workload);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1848

info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1851

cmd, get_opcode(cmd, s->engine),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1853

s->engine->name, s->workload);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1882

info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1885

cmd, get_opcode(cmd, s->engine),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1887

s->engine->name, s->workload);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1941

bb->obj = i915_gem_object_create_shmem(s->engine->i915,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2742

info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2746

cmd, get_opcode(cmd, s->engine),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2748

s->engine->name, s->workload);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2754

trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2857

s.engine = workload->engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2866

if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2904

s.engine = workload->engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2941

if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2945

p = krealloc(s->ring_scan_buffer[workload->engine->id],

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2951

s->ring_scan_buffer[workload->engine->id] = p;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2952

s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

2955

shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3013

obj = i915_gem_object_create_shmem(workload->engine->i915,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3111

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3118

for_each_engine(engine, gvt->gt, id) {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3123

if (!engine->default_state)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3126

vaddr = shmem_pin_map(engine->default_state);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3129

engine->name);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3136

s.engine = engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3138

s.ring_size = engine->context_size - start;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3154

shmem_unpin_map(engine->default_state, vaddr);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3167

int ring_id = workload->engine->id;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3173

ctx_size = workload->engine->context_size - PAGE_SIZE;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

3188

s.engine = workload->engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

482

const struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/cmd_parser.c

656

static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

660

d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

669

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

675

e->info->rings & engine->mask)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

683

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

687

opcode = get_opcode(cmd, engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

691

return find_cmd_entry(gvt, opcode, engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

699

static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

704

d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];

sys/dev/pci/drm/i915/gvt/cmd_parser.c

740

s->vgpu->id, s->engine->name,

sys/dev/pci/drm/i915/gvt/cmd_parser.c

760

print_opcode(cmd_val(s, 0), s->engine);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

856

u32 base = s->workload->engine->mmio_base;

sys/dev/pci/drm/i915/gvt/execlist.c

135

execlist_ring_mmio(execlist->engine, _EL_OFFSET_STATUS_PTR);

sys/dev/pci/drm/i915/gvt/execlist.c

137

execlist_ring_mmio(execlist->engine, _EL_OFFSET_STATUS_BUF);

sys/dev/pci/drm/i915/gvt/execlist.c

160

vgpu->hws_pga[execlist->engine->id]);

sys/dev/pci/drm/i915/gvt/execlist.c

166

hwsp_gpa + INTEL_HWS_CSB_WRITE_INDEX(execlist->engine->i915) * 4,

sys/dev/pci/drm/i915/gvt/execlist.c

177

to_context_switch_event(execlist->engine));

sys/dev/pci/drm/i915/gvt/execlist.c

259

execlist_ring_mmio(execlist->engine, _EL_OFFSET_STATUS);

sys/dev/pci/drm/i915/gvt/execlist.c

383

ret = emulate_execlist_schedule_in(&s->execlist[workload->engine->id],

sys/dev/pci/drm/i915/gvt/execlist.c

397

&s->execlist[workload->engine->id];

sys/dev/pci/drm/i915/gvt/execlist.c

399

struct list_head *next = workload_q_head(vgpu, workload->engine)->next;

sys/dev/pci/drm/i915/gvt/execlist.c

406

if (workload->status || vgpu->resetting_eng & workload->engine->mask)

sys/dev/pci/drm/i915/gvt/execlist.c

409

if (!list_empty(workload_q_head(vgpu, workload->engine))) {

sys/dev/pci/drm/i915/gvt/execlist.c

431

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gvt/execlist.c

438

workload = intel_vgpu_create_workload(vgpu, engine, desc);

sys/dev/pci/drm/i915/gvt/execlist.c

447

workload->elsp_dwords = s->execlist[engine->id].elsp_dwords;

sys/dev/pci/drm/i915/gvt/execlist.c

457

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/execlist.c

460

struct intel_vgpu_execlist *execlist = &s->execlist[engine->id];

sys/dev/pci/drm/i915/gvt/execlist.c

485

ret = submit_context(vgpu, engine, desc[i], i == 0);

sys/dev/pci/drm/i915/gvt/execlist.c

501

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/execlist.c

504

struct intel_vgpu_execlist *execlist = &s->execlist[engine->id];

sys/dev/pci/drm/i915/gvt/execlist.c

511

execlist->engine = engine;

sys/dev/pci/drm/i915/gvt/execlist.c

515

ctx_status_ptr_reg = execlist_ring_mmio(engine, _EL_OFFSET_STATUS_PTR);

sys/dev/pci/drm/i915/gvt/execlist.c

526

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/execlist.c

529

for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gvt/execlist.c

530

kfree(s->ring_scan_buffer[engine->id]);

sys/dev/pci/drm/i915/gvt/execlist.c

531

s->ring_scan_buffer[engine->id] = NULL;

sys/dev/pci/drm/i915/gvt/execlist.c

532

s->ring_scan_buffer_size[engine->id] = 0;

sys/dev/pci/drm/i915/gvt/execlist.c

539

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/execlist.c

542

for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp)

sys/dev/pci/drm/i915/gvt/execlist.c

543

init_vgpu_execlist(vgpu, engine);

sys/dev/pci/drm/i915/gvt/execlist.c

56

static int to_context_switch_event(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/execlist.c

58

if (WARN_ON(engine->id >= ARRAY_SIZE(context_switch_events)))

sys/dev/pci/drm/i915/gvt/execlist.c

61

return context_switch_events[engine->id];

sys/dev/pci/drm/i915/gvt/execlist.c

96

execlist_ring_mmio(execlist->engine, _EL_OFFSET_STATUS);

sys/dev/pci/drm/i915/gvt/execlist.h

175

const struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/execlist.h

183

const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gvt/gtt.c

2266

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/gtt.c

2279

for_each_engine(engine, vgpu->gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/handlers.c

168

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/handlers.c

172

for_each_engine(engine, gvt->gt, id)

sys/dev/pci/drm/i915/gvt/handlers.c

173

if (engine->mmio_base == offset)

sys/dev/pci/drm/i915/gvt/handlers.c

174

return engine;

sys/dev/pci/drm/i915/gvt/handlers.c

1761

const struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gvt/handlers.c

1776

if (unlikely(!engine)) {

sys/dev/pci/drm/i915/gvt/handlers.c

1781

vgpu->hws_pga[engine->id] = value;

sys/dev/pci/drm/i915/gvt/handlers.c

1968

const struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gvt/handlers.c

1978

if (!engine ||

sys/dev/pci/drm/i915/gvt/handlers.c

1979

vgpu == gvt->scheduler.engine_owner[engine->id] ||

sys/dev/pci/drm/i915/gvt/handlers.c

1980

offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||

sys/dev/pci/drm/i915/gvt/handlers.c

1981

offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {

sys/dev/pci/drm/i915/gvt/handlers.c

1997

const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);

sys/dev/pci/drm/i915/gvt/handlers.c

2002

if (drm_WARN_ON(&i915->drm, !engine))

sys/dev/pci/drm/i915/gvt/handlers.c

2020

execlist = &vgpu->submission.execlist[engine->id];

sys/dev/pci/drm/i915/gvt/handlers.c

2024

ret = intel_vgpu_submit_execlist(vgpu, engine);

sys/dev/pci/drm/i915/gvt/handlers.c

2027

engine->name);

sys/dev/pci/drm/i915/gvt/handlers.c

2039

const struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gvt/handlers.c

2078

engine->name);

sys/dev/pci/drm/i915/gvt/handlers.c

2084

engine->mask,

sys/dev/pci/drm/i915/gvt/handlers.c

789

const struct intel_engine_cs *engine =

sys/dev/pci/drm/i915/gvt/handlers.c

792

if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {

sys/dev/pci/drm/i915/gvt/handlers.c

799

reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {

sys/dev/pci/drm/i915/gvt/mmio_context.c

176

static void load_render_mocs(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/mmio_context.c

178

struct intel_gvt *gvt = engine->i915->gvt;

sys/dev/pci/drm/i915/gvt/mmio_context.c

179

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gvt/mmio_context.c

190

if (!HAS_ENGINE(engine->gt, ring_id))

sys/dev/pci/drm/i915/gvt/mmio_context.c

218

int ring_id = req->engine->id;

sys/dev/pci/drm/i915/gvt/mmio_context.c

224

ret = req->engine->emit_flush(req, EMIT_BARRIER);

sys/dev/pci/drm/i915/gvt/mmio_context.c

247

ret = req->engine->emit_flush(req, EMIT_BARRIER);

sys/dev/pci/drm/i915/gvt/mmio_context.c

271

*(cs-2), *(cs-1), vgpu->id, req->engine->id);

sys/dev/pci/drm/i915/gvt/mmio_context.c

298

*(cs-2), *(cs-1), vgpu->id, req->engine->id);

sys/dev/pci/drm/i915/gvt/mmio_context.c

332

if (req->engine->id != RCS0)

sys/dev/pci/drm/i915/gvt/mmio_context.c

364

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/mmio_context.c

366

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gvt/mmio_context.c

376

if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt))

sys/dev/pci/drm/i915/gvt/mmio_context.c

379

if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending))

sys/dev/pci/drm/i915/gvt/mmio_context.c

382

reg = _MMIO(regs[engine->id]);

sys/dev/pci/drm/i915/gvt/mmio_context.c

391

if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gvt/mmio_context.c

400

engine->name);

sys/dev/pci/drm/i915/gvt/mmio_context.c

406

gvt_dbg_core("invalidate TLB for ring %s\n", engine->name);

sys/dev/pci/drm/i915/gvt/mmio_context.c

410

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/mmio_context.c

419

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gvt/mmio_context.c

424

if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs)))

sys/dev/pci/drm/i915/gvt/mmio_context.c

427

if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9)

sys/dev/pci/drm/i915/gvt/mmio_context.c

431

load_render_mocs(engine);

sys/dev/pci/drm/i915/gvt/mmio_context.c

433

offset.reg = regs[engine->id];

sys/dev/pci/drm/i915/gvt/mmio_context.c

438

old_v = gen9_render_mocs.control_table[engine->id][i];

sys/dev/pci/drm/i915/gvt/mmio_context.c

442

new_v = gen9_render_mocs.control_table[engine->id][i];

sys/dev/pci/drm/i915/gvt/mmio_context.c

450

if (engine->id == RCS0) {

sys/dev/pci/drm/i915/gvt/mmio_context.c

485

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/mmio_context.c

487

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gvt/mmio_context.c

492

if (GRAPHICS_VER(engine->i915) >= 9)

sys/dev/pci/drm/i915/gvt/mmio_context.c

493

switch_mocs(pre, next, engine);

sys/dev/pci/drm/i915/gvt/mmio_context.c

495

for (mmio = engine->i915->gvt->engine_mmio_list.mmio;

sys/dev/pci/drm/i915/gvt/mmio_context.c

497

if (mmio->id != engine->id)

sys/dev/pci/drm/i915/gvt/mmio_context.c

504

if (GRAPHICS_VER(engine->i915) == 9 && mmio->in_context)

sys/dev/pci/drm/i915/gvt/mmio_context.c

529

!is_inhibit_context(s->shadow[engine->id]))

sys/dev/pci/drm/i915/gvt/mmio_context.c

556

handle_tlb_pending_event(next, engine);

sys/dev/pci/drm/i915/gvt/mmio_context.c

570

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/mmio_context.c

573

engine->name))

sys/dev/pci/drm/i915/gvt/mmio_context.c

576

gvt_dbg_render("switch ring %s from %s to %s\n", engine->name,

sys/dev/pci/drm/i915/gvt/mmio_context.c

584

intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gvt/mmio_context.c

585

switch_mmio(pre, next, engine);

sys/dev/pci/drm/i915/gvt/mmio_context.c

586

intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);

sys/dev/pci/drm/i915/gvt/mmio_context.h

51

const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/gvt/sched_policy.c

136

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/sched_policy.c

155

for_each_engine(engine, gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/sched_policy.c

156

if (scheduler->current_workload[engine->id])

sys/dev/pci/drm/i915/gvt/sched_policy.c

172

for_each_engine(engine, gvt->gt, i)

sys/dev/pci/drm/i915/gvt/sched_policy.c

173

wake_up(&scheduler->waitq[engine->id]);

sys/dev/pci/drm/i915/gvt/sched_policy.c

40

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/sched_policy.c

42

for_each_engine(engine, vgpu->gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/sched_policy.c

43

if (!list_empty(workload_q_head(vgpu, engine)))

sys/dev/pci/drm/i915/gvt/sched_policy.c

448

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/sched_policy.c

471

for_each_engine(engine, vgpu->gvt->gt, id) {

sys/dev/pci/drm/i915/gvt/sched_policy.c

472

if (scheduler->engine_owner[engine->id] == vgpu) {

sys/dev/pci/drm/i915/gvt/sched_policy.c

473

intel_gvt_switch_mmio(vgpu, NULL, engine);

sys/dev/pci/drm/i915/gvt/sched_policy.c

474

scheduler->engine_owner[engine->id] = NULL;

sys/dev/pci/drm/i915/gvt/scheduler.c

101

if (workload->engine->id != RCS0)

sys/dev/pci/drm/i915/gvt/scheduler.c

1052

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1057

for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1059

&s->workload_q_head[engine->id], list) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1063

clear_bit(engine->id, s->shadow_ctx_desc_updated);

sys/dev/pci/drm/i915/gvt/scheduler.c

1153

struct intel_engine_cs *engine = arg;

sys/dev/pci/drm/i915/gvt/scheduler.c

1154

const bool need_force_wake = GRAPHICS_VER(engine->i915) >= 9;

sys/dev/pci/drm/i915/gvt/scheduler.c

1155

struct intel_gvt *gvt = engine->i915->gvt;

sys/dev/pci/drm/i915/gvt/scheduler.c

1162

gvt_dbg_core("workload thread for ring %s started\n", engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

1167

add_wait_queue(&scheduler->waitq[engine->id], &wait);

sys/dev/pci/drm/i915/gvt/scheduler.c

1169

workload = pick_next_workload(gvt, engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

1175

remove_wait_queue(&scheduler->waitq[engine->id], &wait);

sys/dev/pci/drm/i915/gvt/scheduler.c

1181

engine->name, workload,

sys/dev/pci/drm/i915/gvt/scheduler.c

1184

wakeref = intel_runtime_pm_get(engine->uncore->rpm);

sys/dev/pci/drm/i915/gvt/scheduler.c

1187

engine->name, workload);

sys/dev/pci/drm/i915/gvt/scheduler.c

1190

intel_uncore_forcewake_get(engine->uncore,

sys/dev/pci/drm/i915/gvt/scheduler.c

1209

engine->name, workload);

sys/dev/pci/drm/i915/gvt/scheduler.c

1216

complete_current_workload(gvt, engine->id);

sys/dev/pci/drm/i915/gvt/scheduler.c

1219

intel_uncore_forcewake_put(engine->uncore,

sys/dev/pci/drm/i915/gvt/scheduler.c

1222

intel_runtime_pm_put(engine->uncore->rpm, wakeref);

sys/dev/pci/drm/i915/gvt/scheduler.c

1246

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1251

for_each_engine(engine, gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1253

&engine->context_status_notifier,

sys/dev/pci/drm/i915/gvt/scheduler.c

1262

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1270

for_each_engine(engine, gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1273

scheduler->thread[i] = kthread_run(workload_thread, engine,

sys/dev/pci/drm/i915/gvt/scheduler.c

1274

"gvt:%s", engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

1283

atomic_notifier_chain_register(&engine->context_status_notifier,

sys/dev/pci/drm/i915/gvt/scheduler.c

1322

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1328

for_each_engine(engine, vgpu->gvt->gt, id)

sys/dev/pci/drm/i915/gvt/scheduler.c

1387

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1398

for_each_engine(engine, vgpu->gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1404

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

141

int ring_id = workload->engine->id;

sys/dev/pci/drm/i915/gvt/scheduler.c

1415

if (!intel_uc_wants_guc_submission(&engine->gt->uc))

sys/dev/pci/drm/i915/gvt/scheduler.c

1445

for_each_engine(engine, vgpu->gvt->gt, i) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1522

intel_context_unpin(s->shadow[workload->engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

1629

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gvt/scheduler.c

1633

struct list_head *q = workload_q_head(vgpu, engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

165

if (workload->engine->id == RCS0) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1663

engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

1675

gvt_dbg_el("ring %s begin a new workload\n", engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

169

} else if (workload->engine->id == BCS0)

sys/dev/pci/drm/i915/gvt/scheduler.c

1695

workload->engine = engine;

sys/dev/pci/drm/i915/gvt/scheduler.c

1704

if (engine->id == RCS0) {

sys/dev/pci/drm/i915/gvt/scheduler.c

1743

workload, engine->name, head, tail, start, ctl);

sys/dev/pci/drm/i915/gvt/scheduler.c

1757

with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)

sys/dev/pci/drm/i915/gvt/scheduler.c

1768

ret = intel_context_pin(s->shadow[engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

1784

workload_q_head(workload->vgpu, workload->engine));

sys/dev/pci/drm/i915/gvt/scheduler.c

1786

wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

191

workload->engine->name, workload->ctx_desc.lrca,

sys/dev/pci/drm/i915/gvt/scheduler.c

215

context_page_num = workload->engine->context_size;

sys/dev/pci/drm/i915/gvt/scheduler.c

218

if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)

sys/dev/pci/drm/i915/gvt/scheduler.c

268

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/scheduler.c

270

struct intel_uncore *uncore = engine->uncore;

sys/dev/pci/drm/i915/gvt/scheduler.c

273

reg = RING_INSTDONE(engine->mmio_base);

sys/dev/pci/drm/i915/gvt/scheduler.c

277

reg = RING_ACTHD(engine->mmio_base);

sys/dev/pci/drm/i915/gvt/scheduler.c

281

reg = RING_ACTHD_UDW(engine->mmio_base);

sys/dev/pci/drm/i915/gvt/scheduler.c

291

shadow_ctx_notifier_block[rq->engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

293

enum intel_engine_id ring_id = rq->engine->id;

sys/dev/pci/drm/i915/gvt/scheduler.c

303

NULL, rq->engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

321

workload->vgpu, rq->engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

330

save_ring_hw_state(workload->vgpu, rq->engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

334

save_ring_hw_state(workload->vgpu, rq->engine);

sys/dev/pci/drm/i915/gvt/scheduler.c

369

if (GRAPHICS_VER(req->engine->i915) == 9 && is_inhibit_context(req->context))

sys/dev/pci/drm/i915/gvt/scheduler.c

382

if (req->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gvt/scheduler.c

383

err = req->engine->emit_init_breadcrumb(req);

sys/dev/pci/drm/i915/gvt/scheduler.c

468

rq = i915_request_create(s->shadow[workload->engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

497

if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))

sys/dev/pci/drm/i915/gvt/scheduler.c

498

shadow_context_descriptor_update(s->shadow[workload->engine->id],

sys/dev/pci/drm/i915/gvt/scheduler.c

505

if (workload->engine->id == RCS0 &&

sys/dev/pci/drm/i915/gvt/scheduler.c

653

vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =

sys/dev/pci/drm/i915/gvt/scheduler.c

752

set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);

sys/dev/pci/drm/i915/gvt/scheduler.c

807

workload->engine->name, workload);

sys/dev/pci/drm/i915/gvt/scheduler.c

837

workload->engine->name, workload->req);

sys/dev/pci/drm/i915/gvt/scheduler.c

849

pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/gvt/scheduler.c

861

gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

866

gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);

sys/dev/pci/drm/i915/gvt/scheduler.c

872

list_empty(workload_q_head(scheduler->current_vgpu, engine)))

sys/dev/pci/drm/i915/gvt/scheduler.c

879

if (scheduler->current_workload[engine->id]) {

sys/dev/pci/drm/i915/gvt/scheduler.c

880

workload = scheduler->current_workload[engine->id];

sys/dev/pci/drm/i915/gvt/scheduler.c

882

engine->name, workload);

sys/dev/pci/drm/i915/gvt/scheduler.c

892

scheduler->current_workload[engine->id] =

sys/dev/pci/drm/i915/gvt/scheduler.c

894

engine),

sys/dev/pci/drm/i915/gvt/scheduler.c

897

workload = scheduler->current_workload[engine->id];

sys/dev/pci/drm/i915/gvt/scheduler.c

899

gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);

sys/dev/pci/drm/i915/gvt/scheduler.c

953

gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,

sys/dev/pci/drm/i915/gvt/scheduler.c

971

ring_base = rq->engine->mmio_base;

sys/dev/pci/drm/i915/gvt/scheduler.c

975

context_page_num = rq->engine->context_size;

sys/dev/pci/drm/i915/gvt/scheduler.c

978

if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)

sys/dev/pci/drm/i915/gvt/scheduler.h

161

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/gvt/scheduler.h

87

const struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_active.c

1000

GEM_BUG_ON(i915_request_timeline(rq) != engine->kernel_context->timeline);

sys/dev/pci/drm/i915/i915_active.c

1002

node = llist_del_all(&engine->barrier_tasks);

sys/dev/pci/drm/i915/i915_active.c

378

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_active.c

384

GEM_BUG_ON(node->timeline != engine->kernel_context->timeline->fence_context);

sys/dev/pci/drm/i915/i915_active.c

401

llist_for_each_safe(pos, next, llist_del_all(&engine->barrier_tasks)) {

sys/dev/pci/drm/i915/i915_active.c

413

llist_add_batch(head, tail, &engine->barrier_tasks);

sys/dev/pci/drm/i915/i915_active.c

564

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_active.c

569

engine = __barrier_to_engine(it);

sys/dev/pci/drm/i915/i915_active.c

574

return intel_engine_flush_barriers(engine);

sys/dev/pci/drm/i915/i915_active.c

817

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_active.c

835

engine = __barrier_to_engine(node);

sys/dev/pci/drm/i915/i915_active.c

838

____active_del_barrier(ref, node, engine))

sys/dev/pci/drm/i915/i915_active.c

855

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_active.c

857

intel_engine_mask_t tmp, mask = engine->mask;

sys/dev/pci/drm/i915/i915_active.c

859

struct intel_gt *gt = engine->gt;

sys/dev/pci/drm/i915/i915_active.c

874

for_each_engine_masked(engine, gt, mask, tmp) {

sys/dev/pci/drm/i915/i915_active.c

875

u64 idx = engine->kernel_context->timeline->fence_context;

sys/dev/pci/drm/i915/i915_active.c

908

node->base.cb.node.prev = (void *)engine;

sys/dev/pci/drm/i915/i915_active.c

913

GEM_BUG_ON(barrier_to_engine(node) != engine);

sys/dev/pci/drm/i915/i915_active.c

918

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/i915_active.c

959

struct intel_engine_cs *engine = barrier_to_engine(node);

sys/dev/pci/drm/i915/i915_active.c

981

GEM_BUG_ON(!intel_engine_pm_is_awake(engine));

sys/dev/pci/drm/i915/i915_active.c

982

llist_add(barrier_to_ll(node), &engine->barrier_tasks);

sys/dev/pci/drm/i915/i915_active.c

983

intel_engine_pm_put_delay(engine, 2);

sys/dev/pci/drm/i915/i915_active.c

994

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/i915_active.c

999

GEM_BUG_ON(intel_engine_is_virtual(engine));

sys/dev/pci/drm/i915/i915_active.h

208

struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1000

} else if (IS_HASWELL(engine->i915)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1008

if (GRAPHICS_VER(engine->i915) == 9) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1009

engine->reg_tables = gen9_blt_reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1010

engine->reg_table_count =

sys/dev/pci/drm/i915/i915_cmd_parser.c

1012

} else if (IS_HASWELL(engine->i915)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1013

engine->reg_tables = hsw_blt_reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1014

engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1016

engine->reg_tables = ivb_blt_reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1017

engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1024

engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1027

MISSING_CASE(engine->class);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1031

if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1032

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1034

engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1037

if (!validate_regs_sorted(engine)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1038

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1039

"%s: registers are not sorted\n", engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1043

ret = init_hash_table(engine, cmd_tables, cmd_table_count);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1045

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1046

"%s: initialised failed!\n", engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1047

fini_hash_table(engine);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1051

engine->flags |= I915_ENGINE_USING_CMD_PARSER;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1054

if (intel_engine_requires_cmd_parser(engine) &&

sys/dev/pci/drm/i915/i915_cmd_parser.c

1055

!intel_engine_using_cmd_parser(engine))

sys/dev/pci/drm/i915/i915_cmd_parser.c

1068

void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1070

if (!intel_engine_using_cmd_parser(engine))

sys/dev/pci/drm/i915/i915_cmd_parser.c

1073

fini_hash_table(engine);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1077

find_cmd_in_table(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1082

hash_for_each_possible(engine->cmd_hash, desc_node, node,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1101

find_cmd(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1111

desc = find_cmd_in_table(engine, cmd_header);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1115

mask = engine->get_cmd_length_mask(cmd_header);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1144

find_reg(const struct intel_engine_cs *engine, u32 addr)

sys/dev/pci/drm/i915/i915_cmd_parser.c

1146

const struct drm_i915_reg_table *table = engine->reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1148

int count = engine->reg_table_count;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1247

static bool check_cmd(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1272

find_reg(engine, reg_addr);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1276

reg_addr, *cmd, engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1329

*cmd, engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1341

dword, engine->name);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1445

int intel_engine_cmd_parser(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

1494

desc = find_cmd(engine, *cmd, desc, &default_desc);

sys/dev/pci/drm/i915/i915_cmd_parser.c

1515

if (!check_cmd(engine, desc, cmd, length)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1564

if (IS_HASWELL(engine->i915))

sys/dev/pci/drm/i915/i915_cmd_parser.c

1567

GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7));

sys/dev/pci/drm/i915/i915_cmd_parser.c

1596

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_cmd_parser.c

1600

for_each_uabi_engine(engine, dev_priv) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

1601

if (intel_engine_using_cmd_parser(engine)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

802

static bool validate_cmds_sorted(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

823

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_cmd_parser.c

826

engine->name, engine->id,

sys/dev/pci/drm/i915/i915_cmd_parser.c

838

static bool check_sorted(const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

850

drm_err(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_cmd_parser.c

853

engine->name, engine->id,

sys/dev/pci/drm/i915/i915_cmd_parser.c

864

static bool validate_regs_sorted(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_cmd_parser.c

869

for (i = 0; i < engine->reg_table_count; i++) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

870

table = &engine->reg_tables[i];

sys/dev/pci/drm/i915/i915_cmd_parser.c

871

if (!check_sorted(engine, table->regs, table->num_regs))

sys/dev/pci/drm/i915/i915_cmd_parser.c

906

static int init_hash_table(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_cmd_parser.c

912

hash_init(engine->cmd_hash);

sys/dev/pci/drm/i915/i915_cmd_parser.c

927

hash_add(engine->cmd_hash, &desc_node->node,

sys/dev/pci/drm/i915/i915_cmd_parser.c

935

static void fini_hash_table(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_cmd_parser.c

941

hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

955

int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_cmd_parser.c

961

if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 &&

sys/dev/pci/drm/i915/i915_cmd_parser.c

962

engine->class == COPY_ENGINE_CLASS))

sys/dev/pci/drm/i915/i915_cmd_parser.c

965

switch (engine->class) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

967

if (IS_HASWELL(engine->i915)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

976

if (IS_HASWELL(engine->i915)) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

977

engine->reg_tables = hsw_render_reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

978

engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);

sys/dev/pci/drm/i915/i915_cmd_parser.c

980

engine->reg_tables = ivb_render_reg_tables;

sys/dev/pci/drm/i915/i915_cmd_parser.c

981

engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);

sys/dev/pci/drm/i915/i915_cmd_parser.c

983

engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

988

engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

991

engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;

sys/dev/pci/drm/i915/i915_cmd_parser.c

992

if (GRAPHICS_VER(engine->i915) == 9) {

sys/dev/pci/drm/i915/i915_cmd_parser.c

995

engine->get_cmd_length_mask =

sys/dev/pci/drm/i915/i915_cmd_parser.c

999

engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;

sys/dev/pci/drm/i915/i915_cmd_parser.h

16

int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/i915_cmd_parser.h

17

void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/i915_cmd_parser.h

18

int intel_engine_cmd_parser(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_debugfs.c

438

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_debugfs.c

453

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/i915_debugfs.c

454

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/i915_debugfs.c

466

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_debugfs.c

468

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/i915_debugfs.c

469

const struct i915_wa_list *wal = &engine->ctx_wa_list;

sys/dev/pci/drm/i915/i915_debugfs.c

478

engine->name, count);

sys/dev/pci/drm/i915/i915_drm_client.c

126

if (ce->engine->uabi_class != class)

sys/dev/pci/drm/i915/i915_drm_client.c

217

if (ce->ring != ce->engine->legacy.ring && ce->ring->vma)

sys/dev/pci/drm/i915/i915_gpu_error.c

1153

while (gt->engine) {

sys/dev/pci/drm/i915/i915_gpu_error.c

1154

struct intel_engine_coredump *ee = gt->engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1156

gt->engine = ee->next;

sys/dev/pci/drm/i915/i915_gpu_error.c

1342

const struct intel_engine_cs *engine = ee->engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1343

struct drm_i915_private *i915 = engine->i915;

sys/dev/pci/drm/i915/i915_gpu_error.c

1346

ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1353

if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)

sys/dev/pci/drm/i915/i915_gpu_error.c

1354

ee->fault_reg = intel_uncore_read(engine->uncore,

sys/dev/pci/drm/i915/i915_gpu_error.c

1357

ee->fault_reg = intel_gt_mcr_read_any(engine->gt,

sys/dev/pci/drm/i915/i915_gpu_error.c

1360

ee->fault_reg = intel_uncore_read(engine->uncore,

sys/dev/pci/drm/i915/i915_gpu_error.c

1363

ee->fault_reg = intel_uncore_read(engine->uncore,

sys/dev/pci/drm/i915/i915_gpu_error.c

1366

ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);

sys/dev/pci/drm/i915/i915_gpu_error.c

1370

ee->esr = ENGINE_READ(engine, RING_ESR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1371

ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);

sys/dev/pci/drm/i915/i915_gpu_error.c

1372

ee->ipeir = ENGINE_READ(engine, RING_IPEIR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1373

ee->ipehr = ENGINE_READ(engine, RING_IPEHR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1374

ee->instps = ENGINE_READ(engine, RING_INSTPS);

sys/dev/pci/drm/i915/i915_gpu_error.c

1375

ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1376

ee->ccid = ENGINE_READ(engine, CCID);

sys/dev/pci/drm/i915/i915_gpu_error.c

1378

ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;

sys/dev/pci/drm/i915/i915_gpu_error.c

1379

ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;

sys/dev/pci/drm/i915/i915_gpu_error.c

1381

ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);

sys/dev/pci/drm/i915/i915_gpu_error.c

1383

ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);

sys/dev/pci/drm/i915/i915_gpu_error.c

1384

ee->ipeir = ENGINE_READ(engine, IPEIR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1385

ee->ipehr = ENGINE_READ(engine, IPEHR);

sys/dev/pci/drm/i915/i915_gpu_error.c

1389

ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1390

ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);

sys/dev/pci/drm/i915/i915_gpu_error.c

1391

ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1392

ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);

sys/dev/pci/drm/i915/i915_gpu_error.c

1393

ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);

sys/dev/pci/drm/i915/i915_gpu_error.c

1394

ee->nopid = ENGINE_READ(engine, RING_NOPID);

sys/dev/pci/drm/i915/i915_gpu_error.c

1395

ee->excc = ENGINE_READ(engine, RING_EXCC);

sys/dev/pci/drm/i915/i915_gpu_error.c

1398

intel_engine_get_instdone(engine, &ee->instdone);

sys/dev/pci/drm/i915/i915_gpu_error.c

1400

ee->instpm = ENGINE_READ(engine, RING_INSTPM);

sys/dev/pci/drm/i915/i915_gpu_error.c

1401

ee->acthd = intel_engine_get_active_head(engine);

sys/dev/pci/drm/i915/i915_gpu_error.c

1402

ee->start = ENGINE_READ(engine, RING_START);

sys/dev/pci/drm/i915/i915_gpu_error.c

1403

ee->head = ENGINE_READ(engine, RING_HEAD);

sys/dev/pci/drm/i915/i915_gpu_error.c

1404

ee->tail = ENGINE_READ(engine, RING_TAIL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1405

ee->ctl = ENGINE_READ(engine, RING_CTL);

sys/dev/pci/drm/i915/i915_gpu_error.c

1407

ee->mode = ENGINE_READ(engine, RING_MI_MODE);

sys/dev/pci/drm/i915/i915_gpu_error.c

1413

switch (engine->id) {

sys/dev/pci/drm/i915/i915_gpu_error.c

1415

MISSING_CASE(engine->id);

sys/dev/pci/drm/i915/i915_gpu_error.c

1430

} else if (GRAPHICS_VER(engine->i915) == 6) {

sys/dev/pci/drm/i915/i915_gpu_error.c

1431

mmio = RING_HWS_PGA_GEN6(engine->mmio_base);

sys/dev/pci/drm/i915/i915_gpu_error.c

1434

mmio = RING_HWS_PGA(engine->mmio_base);

sys/dev/pci/drm/i915/i915_gpu_error.c

1437

ee->hws = intel_uncore_read(engine->uncore, mmio);

sys/dev/pci/drm/i915/i915_gpu_error.c

1440

ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);

sys/dev/pci/drm/i915/i915_gpu_error.c

1445

ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);

sys/dev/pci/drm/i915/i915_gpu_error.c

1449

ENGINE_READ(engine, RING_PP_DIR_BASE_READ);

sys/dev/pci/drm/i915/i915_gpu_error.c

1452

ENGINE_READ(engine, RING_PP_DIR_BASE);

sys/dev/pci/drm/i915/i915_gpu_error.c

1454

u32 base = engine->mmio_base;

sys/dev/pci/drm/i915/i915_gpu_error.c

1458

intel_uncore_read(engine->uncore,

sys/dev/pci/drm/i915/i915_gpu_error.c

1462

intel_uncore_read(engine->uncore,

sys/dev/pci/drm/i915/i915_gpu_error.c

1497

const struct intel_engine_execlists * const el = &ee->engine->execlists;

sys/dev/pci/drm/i915/i915_gpu_error.c

1656

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.c

1664

ee->engine = engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1727

const struct intel_engine_cs *engine = ee->engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1734

i915_vma_coredump_create(engine->gt, vma_res,

sys/dev/pci/drm/i915/i915_gpu_error.c

1744

add_vma_coredump(ee, engine->gt, engine->status_page.vma,

sys/dev/pci/drm/i915/i915_gpu_error.c

1747

add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,

sys/dev/pci/drm/i915/i915_gpu_error.c

1752

capture_engine(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_gpu_error.c

1761

ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.c

1765

intel_engine_get_hung_entity(engine, &ce, &rq);

sys/dev/pci/drm/i915/i915_gpu_error.c

1773

drm_info(&engine->gt->i915->drm,

sys/dev/pci/drm/i915/i915_gpu_error.c

1775

engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id);

sys/dev/pci/drm/i915/i915_gpu_error.c

1777

drm_info(&engine->gt->i915->drm,

sys/dev/pci/drm/i915/i915_gpu_error.c

1779

engine->name, rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/i915_gpu_error.c

1793

intel_guc_capture_get_matching_node(engine->gt, ee, ce);

sys/dev/pci/drm/i915/i915_gpu_error.c

1808

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1811

for_each_engine(engine, gt->_gt, id) {

sys/dev/pci/drm/i915/i915_gpu_error.c

1817

ee = capture_engine(engine, compress, dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.c

1821

ee->hung = engine->mask & engine_mask;

sys/dev/pci/drm/i915/i915_gpu_error.c

1831

ee->next = gt->engine;

sys/dev/pci/drm/i915/i915_gpu_error.c

1832

gt->engine = ee;

sys/dev/pci/drm/i915/i915_gpu_error.c

2097

for (cs = gt->engine; cs; cs = cs->next) {

sys/dev/pci/drm/i915/i915_gpu_error.c

2099

hung_classes |= BIT(cs->engine->uabi_class);

sys/dev/pci/drm/i915/i915_gpu_error.c

478

if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)

sys/dev/pci/drm/i915/i915_gpu_error.c

487

for_each_ss_steering(iter, ee->engine->gt, slice, subslice)

sys/dev/pci/drm/i915/i915_gpu_error.c

492

for_each_ss_steering(iter, ee->engine->gt, slice, subslice)

sys/dev/pci/drm/i915/i915_gpu_error.c

501

for_each_ss_steering(iter, ee->engine->gt, slice, subslice)

sys/dev/pci/drm/i915/i915_gpu_error.c

565

err_printf(m, "%s command stream:\n", ee->engine->name);

sys/dev/pci/drm/i915/i915_gpu_error.c

643

const struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_gpu_error.c

655

engine ? engine->name : "global", vma->name,

sys/dev/pci/drm/i915/i915_gpu_error.c

906

for (ee = gt->engine; ee; ee = ee->next) {

sys/dev/pci/drm/i915/i915_gpu_error.c

914

ee->engine->name);

sys/dev/pci/drm/i915/i915_gpu_error.c

924

intel_gpu_error_print_vma(m, ee->engine, vma);

sys/dev/pci/drm/i915/i915_gpu_error.c

960

for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)

sys/dev/pci/drm/i915/i915_gpu_error.c

962

ee->engine->name,

sys/dev/pci/drm/i915/i915_gpu_error.h

171

struct intel_engine_coredump *engine;

sys/dev/pci/drm/i915/i915_gpu_error.h

250

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_gpu_error.h

252

return atomic_read(&error->reset_engine_count[engine->class]);

sys/dev/pci/drm/i915/i915_gpu_error.h

257

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_gpu_error.h

259

atomic_inc(&error->reset_engine_count[engine->class]);

sys/dev/pci/drm/i915/i915_gpu_error.h

290

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);

sys/dev/pci/drm/i915/i915_gpu_error.h

360

intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)

sys/dev/pci/drm/i915/i915_gpu_error.h

60

const struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_irq.c

1092

intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],

sys/dev/pci/drm/i915/i915_irq.c

1096

intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],

sys/dev/pci/drm/i915/i915_irq.c

975

intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);

sys/dev/pci/drm/i915/i915_perf.c

1302

if (ce->engine != stream->engine) /* first match! */

sys/dev/pci/drm/i915/i915_perf.c

1387

scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);

sys/dev/pci/drm/i915/i915_perf.c

1395

err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),

sys/dev/pci/drm/i915/i915_perf.c

1430

if (intel_engine_uses_guc(stream->engine)) {

sys/dev/pci/drm/i915/i915_perf.c

1437

} else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) {

sys/dev/pci/drm/i915/i915_perf.c

1476

u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;

sys/dev/pci/drm/i915/i915_perf.c

1479

if (drm_WARN_ON(&ce->engine->i915->drm, !state))

sys/dev/pci/drm/i915/i915_perf.c

1488

drm_WARN_ON(&ce->engine->i915->drm,

sys/dev/pci/drm/i915/i915_perf.c

1503

i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);

sys/dev/pci/drm/i915/i915_perf.c

1504

struct i915_perf *perf = &ce->engine->i915->perf;

sys/dev/pci/drm/i915/i915_perf.c

1514

drm_dbg(&ce->engine->i915->drm,

sys/dev/pci/drm/i915/i915_perf.c

1516

ce->engine->name, offset);

sys/dev/pci/drm/i915/i915_perf.c

1522

static bool engine_supports_mi_query(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

1524

return engine->class == RENDER_CLASS;

sys/dev/pci/drm/i915/i915_perf.c

1546

if (engine_supports_mi_query(stream->engine) &&

sys/dev/pci/drm/i915/i915_perf.c

1557

stream->engine->name);

sys/dev/pci/drm/i915/i915_perf.c

1562

switch (GRAPHICS_VER(ce->engine->i915)) {

sys/dev/pci/drm/i915/i915_perf.c

1575

if (intel_engine_uses_guc(ce->engine)) {

sys/dev/pci/drm/i915/i915_perf.c

1607

MISSING_CASE(GRAPHICS_VER(ce->engine->i915));

sys/dev/pci/drm/i915/i915_perf.c

1668

static bool engine_supports_oa(const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

1670

return engine->oa_group;

sys/dev/pci/drm/i915/i915_perf.c

1673

static bool engine_supports_oa_format(struct intel_engine_cs *engine, int type)

sys/dev/pci/drm/i915/i915_perf.c

1675

return engine->oa_group && engine->oa_group->type == type;

sys/dev/pci/drm/i915/i915_perf.c

1683

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

1684

struct i915_perf_group *g = stream->engine->oa_group;

sys/dev/pci/drm/i915/i915_perf.c

1702

intel_engine_pm_put(stream->engine);

sys/dev/pci/drm/i915/i915_perf.c

1874

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

1958

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

1964

const u32 base = stream->engine->mmio_base;

sys/dev/pci/drm/i915/i915_perf.c

2273

&stream->engine->gt->ggtt->vm,

sys/dev/pci/drm/i915/i915_perf.c

2351

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/i915_perf.c

2353

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/i915_perf.c

2375

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/i915_perf.c

2399

return stream->pinned_ctx ?: stream->engine->kernel_context;

sys/dev/pci/drm/i915/i915_perf.c

2559

rq = intel_engine_create_kernel_request(ce->engine);

sys/dev/pci/drm/i915/i915_perf.c

2580

intel_engine_pm_get(ce->engine);

sys/dev/pci/drm/i915/i915_perf.c

2582

intel_engine_pm_put(ce->engine);

sys/dev/pci/drm/i915/i915_perf.c

2610

GEM_BUG_ON(ce == ce->engine->kernel_context);

sys/dev/pci/drm/i915/i915_perf.c

2612

if (ce->engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/i915_perf.c

2619

flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);

sys/dev/pci/drm/i915/i915_perf.c

2657

RING_CONTEXT_CONTROL(ce->engine->mmio_base),

sys/dev/pci/drm/i915/i915_perf.c

2713

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_perf.c

2714

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

2760

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/i915_perf.c

2761

struct intel_context *ce = engine->kernel_context;

sys/dev/pci/drm/i915/i915_perf.c

2763

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/i915_perf.c

2766

regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);

sys/dev/pci/drm/i915/i915_perf.c

3185

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

3187

const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;

sys/dev/pci/drm/i915/i915_perf.c

3191

if (GRAPHICS_VER(engine->i915) == 11) {

sys/dev/pci/drm/i915/i915_perf.c

3207

struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_perf.c

3210

if (drm_sseu->engine.engine_class != engine->uabi_class ||

sys/dev/pci/drm/i915/i915_perf.c

3211

drm_sseu->engine.engine_instance != engine->uabi_instance)

sys/dev/pci/drm/i915/i915_perf.c

3214

return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);

sys/dev/pci/drm/i915/i915_perf.c

3272

if (!props->engine) {

sys/dev/pci/drm/i915/i915_perf.c

3277

g = props->engine->oa_group;

sys/dev/pci/drm/i915/i915_perf.c

3320

stream->engine = props->engine;

sys/dev/pci/drm/i915/i915_perf.c

3321

stream->uncore = stream->engine->gt->uncore;

sys/dev/pci/drm/i915/i915_perf.c

3374

intel_engine_pm_get(stream->engine);

sys/dev/pci/drm/i915/i915_perf.c

3383

stream->engine->gt->perf.sseu = props->sseu;

sys/dev/pci/drm/i915/i915_perf.c

3413

intel_engine_pm_put(stream->engine);

sys/dev/pci/drm/i915/i915_perf.c

3430

const struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

3434

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/i915_perf.c

3438

stream = READ_ONCE(engine->oa_group->exclusive_stream);

sys/dev/pci/drm/i915/i915_perf.c

3772

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

378

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_perf.c

3899

get_default_sseu_config(&props->sseu, props->engine);

sys/dev/pci/drm/i915/i915_perf.c

4183

props->engine = intel_engine_lookup_user(perf->i915, class, instance);

sys/dev/pci/drm/i915/i915_perf.c

4184

if (!props->engine) {

sys/dev/pci/drm/i915/i915_perf.c

4191

if (!engine_supports_oa(props->engine)) {

sys/dev/pci/drm/i915/i915_perf.c

4203

if (IS_MEDIA_GT_IP_STEP(props->engine->gt, IP_VER(13, 0), STEP_A0, STEP_C0) &&

sys/dev/pci/drm/i915/i915_perf.c

4204

props->engine->oa_group->type == TYPE_OAM &&

sys/dev/pci/drm/i915/i915_perf.c

4205

intel_check_bios_c6_setup(&props->engine->gt->rc6)) {

sys/dev/pci/drm/i915/i915_perf.c

4213

if (!engine_supports_oa_format(props->engine, f->type)) {

sys/dev/pci/drm/i915/i915_perf.c

4216

f->type, props->engine->class);

sys/dev/pci/drm/i915/i915_perf.c

4221

ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);

sys/dev/pci/drm/i915/i915_perf.c

4286

gt = props.engine->gt;

sys/dev/pci/drm/i915/i915_perf.c

439

return &stream->engine->oa_group->regs;

sys/dev/pci/drm/i915/i915_perf.c

4888

static u32 __oam_engine_group(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

4890

if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) {

sys/dev/pci/drm/i915/i915_perf.c

4895

drm_WARN_ON(&engine->i915->drm,

sys/dev/pci/drm/i915/i915_perf.c

4896

engine->gt->type != GT_MEDIA);

sys/dev/pci/drm/i915/i915_perf.c

4904

static u32 __oa_engine_group(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_perf.c

4906

switch (engine->class) {

sys/dev/pci/drm/i915/i915_perf.c

4912

return __oam_engine_group(engine);

sys/dev/pci/drm/i915/i915_perf.c

4973

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_perf.c

4981

for_each_engine_masked(engine, gt, ALL_ENGINES, tmp) {

sys/dev/pci/drm/i915/i915_perf.c

4982

u32 index = __oa_engine_group(engine);

sys/dev/pci/drm/i915/i915_perf.c

4984

engine->oa_group = NULL;

sys/dev/pci/drm/i915/i915_perf.c

4987

engine->oa_group = &g[index];

sys/dev/pci/drm/i915/i915_perf.c

833

GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) {

sys/dev/pci/drm/i915/i915_perf.h

37

const struct intel_engine_cs *engine);

sys/dev/pci/drm/i915/i915_perf_types.h

183

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

1006

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

1020

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/i915_pmu.c

1022

if (!engine_event_status(engine,

sys/dev/pci/drm/i915/i915_pmu.c

1084

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/i915_pmu.c

1088

if (engine_event_status(engine,

sys/dev/pci/drm/i915/i915_pmu.c

1093

engine->name, engine_events[i].name);

sys/dev/pci/drm/i915/i915_pmu.c

1100

__I915_PMU_ENGINE(engine->uabi_class,

sys/dev/pci/drm/i915/i915_pmu.c

1101

engine->uabi_instance,

sys/dev/pci/drm/i915/i915_pmu.c

1105

engine->name, engine_events[i].name);

sys/dev/pci/drm/i915/i915_pmu.c

356

static void gen3_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)

sys/dev/pci/drm/i915/i915_pmu.c

358

struct intel_engine_pmu *pmu = &engine->pmu;

sys/dev/pci/drm/i915/i915_pmu.c

362

val = ENGINE_READ_FW(engine, RING_CTL);

sys/dev/pci/drm/i915/i915_pmu.c

372

if (intel_engine_supports_stats(engine))

sys/dev/pci/drm/i915/i915_pmu.c

384

val = ENGINE_READ_FW(engine, RING_MI_MODE);

sys/dev/pci/drm/i915/i915_pmu.c

391

static void gen2_engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)

sys/dev/pci/drm/i915/i915_pmu.c

393

struct intel_engine_pmu *pmu = &engine->pmu;

sys/dev/pci/drm/i915/i915_pmu.c

396

tail = ENGINE_READ_FW(engine, RING_TAIL);

sys/dev/pci/drm/i915/i915_pmu.c

397

head = ENGINE_READ_FW(engine, RING_HEAD);

sys/dev/pci/drm/i915/i915_pmu.c

398

acthd = ENGINE_READ_FW(engine, ACTHD);

sys/dev/pci/drm/i915/i915_pmu.c

408

static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)

sys/dev/pci/drm/i915/i915_pmu.c

410

if (GRAPHICS_VER(engine->i915) >= 3)

sys/dev/pci/drm/i915/i915_pmu.c

411

gen3_engine_sample(engine, period_ns);

sys/dev/pci/drm/i915/i915_pmu.c

413

gen2_engine_sample(engine, period_ns);

sys/dev/pci/drm/i915/i915_pmu.c

420

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

430

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/i915_pmu.c

431

if (!engine->pmu.enable)

sys/dev/pci/drm/i915/i915_pmu.c

434

if (!intel_engine_pm_get_if_awake(engine))

sys/dev/pci/drm/i915/i915_pmu.c

438

spin_lock_irqsave(&engine->uncore->lock, flags);

sys/dev/pci/drm/i915/i915_pmu.c

439

engine_sample(engine, period_ns);

sys/dev/pci/drm/i915/i915_pmu.c

440

spin_unlock_irqrestore(&engine->uncore->lock, flags);

sys/dev/pci/drm/i915/i915_pmu.c

442

engine_sample(engine, period_ns);

sys/dev/pci/drm/i915/i915_pmu.c

445

intel_engine_pm_put_async(engine);

sys/dev/pci/drm/i915/i915_pmu.c

550

engine_event_status(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/i915_pmu.c

558

if (GRAPHICS_VER(engine->i915) < 6)

sys/dev/pci/drm/i915/i915_pmu.c

610

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

612

engine = intel_engine_lookup_user(i915, engine_event_class(event),

sys/dev/pci/drm/i915/i915_pmu.c

614

if (!engine)

sys/dev/pci/drm/i915/i915_pmu.c

617

return engine_event_status(engine, engine_event_sample(event));

sys/dev/pci/drm/i915/i915_pmu.c

665

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

667

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/i915_pmu.c

671

if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {

sys/dev/pci/drm/i915/i915_pmu.c

674

intel_engine_supports_stats(engine)) {

sys/dev/pci/drm/i915/i915_pmu.c

677

val = ktime_to_ns(intel_engine_get_busy_time(engine,

sys/dev/pci/drm/i915/i915_pmu.c

680

val = engine->pmu.sample[sample].cur;

sys/dev/pci/drm/i915/i915_pmu.c

767

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

769

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/i915_pmu.c

773

BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=

sys/dev/pci/drm/i915/i915_pmu.c

775

BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=

sys/dev/pci/drm/i915/i915_pmu.c

777

GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));

sys/dev/pci/drm/i915/i915_pmu.c

778

GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));

sys/dev/pci/drm/i915/i915_pmu.c

779

GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);

sys/dev/pci/drm/i915/i915_pmu.c

781

engine->pmu.enable |= BIT(sample);

sys/dev/pci/drm/i915/i915_pmu.c

782

engine->pmu.enable_count[sample]++;

sys/dev/pci/drm/i915/i915_pmu.c

810

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_pmu.c

812

engine = intel_engine_lookup_user(i915,

sys/dev/pci/drm/i915/i915_pmu.c

816

GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));

sys/dev/pci/drm/i915/i915_pmu.c

817

GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));

sys/dev/pci/drm/i915/i915_pmu.c

818

GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);

sys/dev/pci/drm/i915/i915_pmu.c

824

if (--engine->pmu.enable_count[sample] == 0)

sys/dev/pci/drm/i915/i915_pmu.c

825

engine->pmu.enable &= ~BIT(sample);

sys/dev/pci/drm/i915/i915_query.c

105

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_query.c

113

engine = intel_engine_lookup_user(i915, (u8)classinstance.engine_class,

sys/dev/pci/drm/i915/i915_query.c

116

if (!engine)

sys/dev/pci/drm/i915/i915_query.c

119

if (engine->class != RENDER_CLASS)

sys/dev/pci/drm/i915/i915_query.c

122

sseu = &engine->gt->info.sseu;

sys/dev/pci/drm/i915/i915_query.c

137

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_query.c

143

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/i915_query.c

158

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/i915_query.c

159

info.engine.engine_class = engine->uabi_class;

sys/dev/pci/drm/i915/i915_query.c

160

info.engine.engine_instance = engine->uabi_instance;

sys/dev/pci/drm/i915/i915_query.c

162

info.capabilities = engine->uabi_capabilities;

sys/dev/pci/drm/i915/i915_query.c

163

info.logical_instance = ilog2(engine->logical_mask);

sys/dev/pci/drm/i915/i915_request.c

1018

rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);

sys/dev/pci/drm/i915/i915_request.c

1026

rq->engine = ce->engine;

sys/dev/pci/drm/i915/i915_request.c

1028

rq->execution_mask = ce->engine->mask;

sys/dev/pci/drm/i915/i915_request.c

1029

rq->i915 = ce->engine->i915;

sys/dev/pci/drm/i915/i915_request.c

1072

2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);

sys/dev/pci/drm/i915/i915_request.c

1082

ret = rq->engine->request_alloc(rq);

sys/dev/pci/drm/i915/i915_request.c

1223

return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);

sys/dev/pci/drm/i915/i915_request.c

1231

const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;

sys/dev/pci/drm/i915/i915_request.c

1236

GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);

sys/dev/pci/drm/i915/i915_request.c

1280

return to->engine->gt->ggtt == from->engine->gt->ggtt;

sys/dev/pci/drm/i915/i915_request.c

1288

const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;

sys/dev/pci/drm/i915/i915_request.c

1398

intel_engine_has_semaphores(to->engine) &&

sys/dev/pci/drm/i915/i915_request.c

1406

if (to->engine->sched_engine->schedule) {

sys/dev/pci/drm/i915/i915_request.c

1543

if (to->engine == READ_ONCE(from->engine))

sys/dev/pci/drm/i915/i915_request.c

1564

if (to->engine->sched_engine->schedule) {

sys/dev/pci/drm/i915/i915_request.c

1572

if (!intel_engine_uses_guc(to->engine) &&

sys/dev/pci/drm/i915/i915_request.c

1706

struct intel_huc *huc = &rq->context->engine->gt->uc.huc;

sys/dev/pci/drm/i915/i915_request.c

1733

if (rq->engine->sched_engine->schedule)

sys/dev/pci/drm/i915/i915_request.c

174

!cmpxchg(&rq->engine->request_pool, NULL, rq))

sys/dev/pci/drm/i915/i915_request.c

1765

bool uses_guc = intel_engine_uses_guc(rq->engine);

sys/dev/pci/drm/i915/i915_request.c

1766

bool pow2 = is_power_of_2(READ_ONCE(prev->engine)->mask |

sys/dev/pci/drm/i915/i915_request.c

1767

rq->engine->mask);

sys/dev/pci/drm/i915/i915_request.c

1788

if (rq->engine->sched_engine->schedule)

sys/dev/pci/drm/i915/i915_request.c

1815

if (rq->engine->class == VIDEO_DECODE_CLASS)

sys/dev/pci/drm/i915/i915_request.c

1872

struct intel_engine_cs *engine = rq->engine;

sys/dev/pci/drm/i915/i915_request.c

1893

cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);

sys/dev/pci/drm/i915/i915_request.c

1920

if (attr && rq->engine->sched_engine->schedule)

sys/dev/pci/drm/i915/i915_request.c

1921

rq->engine->sched_engine->schedule(rq, attr);

sys/dev/pci/drm/i915/i915_request.c

2015

timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);

sys/dev/pci/drm/i915/i915_request.c

2093

mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);

sys/dev/pci/drm/i915/i915_request.c

2161

__intel_engine_flush_submission(rq->engine, false);

sys/dev/pci/drm/i915/i915_request.c

2188

mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);

sys/dev/pci/drm/i915/i915_request.c

2244

return intel_engine_is_virtual(rq->engine) ? 'V' : 'R';

sys/dev/pci/drm/i915/i915_request.c

2329

static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq)

sys/dev/pci/drm/i915/i915_request.c

2331

u32 ring = ENGINE_READ(engine, RING_START);

sys/dev/pci/drm/i915/i915_request.c

2338

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_request.c

2342

if (!intel_engine_is_virtual(rq->engine))

sys/dev/pci/drm/i915/i915_request.c

2343

return engine_match_ring(rq->engine, rq);

sys/dev/pci/drm/i915/i915_request.c

2347

while ((engine = intel_engine_get_sibling(rq->engine, i++))) {

sys/dev/pci/drm/i915/i915_request.c

2348

found = engine_match_ring(engine, rq);

sys/dev/pci/drm/i915/i915_request.c

266

struct intel_engine_cs *engine, *locked;

sys/dev/pci/drm/i915/i915_request.c

276

locked = READ_ONCE(rq->engine);

sys/dev/pci/drm/i915/i915_request.c

278

while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {

sys/dev/pci/drm/i915/i915_request.c

280

locked = engine;

sys/dev/pci/drm/i915/i915_request.c

301

struct intel_gt *gt = rq->engine->gt;

sys/dev/pci/drm/i915/i915_request.c

319

struct intel_gt *gt = rq->engine->gt;

sys/dev/pci/drm/i915/i915_request.c

439

intel_rps_dec_waiters(&rq->engine->gt->rps);

sys/dev/pci/drm/i915/i915_request.c

451

rq->engine->remove_active_request(rq);

sys/dev/pci/drm/i915/i915_request.c

480

__engine_active(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/i915_request.c

482

return READ_ONCE(engine->execlists.active);

sys/dev/pci/drm/i915/i915_request.c

533

for (port = __engine_active(signal->engine);

sys/dev/pci/drm/i915/i915_request.c

658

struct intel_engine_cs *engine = request->engine;

sys/dev/pci/drm/i915/i915_request.c

664

lockdep_assert_held(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/i915_request.c

711

engine->saturated |= request->sched.semaphores;

sys/dev/pci/drm/i915/i915_request.c

713

engine->emit_fini_breadcrumb(request,

sys/dev/pci/drm/i915/i915_request.c

717

if (engine->bump_serial)

sys/dev/pci/drm/i915/i915_request.c

718

engine->bump_serial(engine);

sys/dev/pci/drm/i915/i915_request.c

720

engine->serial++;

sys/dev/pci/drm/i915/i915_request.c

725

engine->add_active_request(request);

sys/dev/pci/drm/i915/i915_request.c

751

struct intel_engine_cs *engine = request->engine;

sys/dev/pci/drm/i915/i915_request.c

755

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/i915_request.c

759

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/i915_request.c

764

struct intel_engine_cs *engine = request->engine;

sys/dev/pci/drm/i915/i915_request.c

773

lockdep_assert_held(&engine->sched_engine->lock);

sys/dev/pci/drm/i915/i915_request.c

802

struct intel_engine_cs *engine = request->engine;

sys/dev/pci/drm/i915/i915_request.c

806

spin_lock_irqsave(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/i915_request.c

810

spin_unlock_irqrestore(&engine->sched_engine->lock, flags);

sys/dev/pci/drm/i915/i915_request.c

847

request->engine->submit_request(request);

sys/dev/pci/drm/i915/i915_request.h

212

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_request.h

67

ENGINE_TRACE(rq__->engine, "fence %llx:%lld, current %d " fmt, \

sys/dev/pci/drm/i915/i915_request.h

694

lockdep_is_held(&rq->engine->sched_engine->lock));

sys/dev/pci/drm/i915/i915_scheduler.c

152

while (locked != (sched_engine = READ_ONCE(rq->engine)->sched_engine)) {

sys/dev/pci/drm/i915/i915_scheduler.c

242

sched_engine = node_to_request(node)->engine->sched_engine;

sys/dev/pci/drm/i915/i915_scheduler.c

261

GEM_BUG_ON(node_to_request(node)->engine->sched_engine !=

sys/dev/pci/drm/i915/i915_vma.c

1654

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/i915_vma.c

1657

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/i915_vma.c

1658

intel_engine_flush_barriers(engine);

sys/dev/pci/drm/i915/pxp/intel_pxp.c

100

ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

sys/dev/pci/drm/i915/pxp/intel_pxp.c

87

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/pxp/intel_pxp.c

95

for (i = 0, engine = NULL; !engine; i++)

sys/dev/pci/drm/i915/pxp/intel_pxp.c

96

engine = gt->engine_class[VIDEO_DECODE_CLASS][i];

sys/dev/pci/drm/i915/pxp/intel_pxp.c

98

GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

111

if (ce->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/pxp/intel_pxp_cmd.c

112

err = ce->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

373

struct intel_engine_cs *engine = gt->engine[GSC0];

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

381

if (!engine)

sys/dev/pci/drm/i915/pxp/intel_pxp_gsccs.c

401

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_active.c

100

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_active.c

103

rq = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/selftests/i915_active.c

208

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_active.c

222

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_active.c

224

engine);

sys/dev/pci/drm/i915/selftests/i915_active.c

266

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_active.c

271

engine = __barrier_to_engine(it);

sys/dev/pci/drm/i915/selftests/i915_active.c

276

return engine;

sys/dev/pci/drm/i915/selftests/i915_active.c

290

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_active.c

292

engine = node_to_barrier(it);

sys/dev/pci/drm/i915/selftests/i915_active.c

293

if (engine) {

sys/dev/pci/drm/i915/selftests/i915_active.c

294

drm_printf(m, "\tbarrier: %s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_active.c

80

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

381

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

449

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

459

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

473

engine->name,

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

496

count, engine->name);

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

504

engine->name);

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

509

err = intel_gt_wait_for_idle(engine->gt, HZ * 3);

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

511

gt_err(engine->gt, "Failed to idle GT (on %s)",

sys/dev/pci/drm/i915/selftests/i915_gem_evict.c

512

engine->name);

sys/dev/pci/drm/i915/selftests/i915_perf.c

107

if (!props.engine)

sys/dev/pci/drm/i915/selftests/i915_perf.c

110

gt = props.engine->gt;

sys/dev/pci/drm/i915/selftests/i915_perf.c

139

struct intel_gt *gt = stream->engine->gt;

sys/dev/pci/drm/i915/selftests/i915_perf.c

190

while (!intel_read_status_page(rq->engine, slot) &&

sys/dev/pci/drm/i915/selftests/i915_perf.c

216

if (stream->engine->class != RENDER_CLASS) {

sys/dev/pci/drm/i915/selftests/i915_perf.c

222

intel_write_status_page(stream->engine, 0x100 + i, 0);

sys/dev/pci/drm/i915/selftests/i915_perf.c

224

rq = intel_engine_create_kernel_request(stream->engine);

sys/dev/pci/drm/i915/selftests/i915_perf.c

230

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/selftests/i915_perf.c

231

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/selftests/i915_perf.c

244

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/selftests/i915_perf.c

269

delay = intel_read_status_page(stream->engine, 0x102);

sys/dev/pci/drm/i915/selftests/i915_perf.c

270

delay -= intel_read_status_page(stream->engine, 0x100);

sys/dev/pci/drm/i915/selftests/i915_perf.c

271

delay = intel_gt_clock_interval_to_ns(stream->engine->gt, delay);

sys/dev/pci/drm/i915/selftests/i915_perf.c

307

gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));

sys/dev/pci/drm/i915/selftests/i915_perf.c

309

ce = intel_context_create(stream->engine);

sys/dev/pci/drm/i915/selftests/i915_perf.c

326

if (rq->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/selftests/i915_perf.c

327

err = rq->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/selftests/i915_perf.c

351

err = rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/selftests/i915_perf.c

360

store = memset32(rq->engine->status_page.addr + 512, 0, 32);

sys/dev/pci/drm/i915/selftests/i915_perf.c

378

*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +

sys/dev/pci/drm/i915/selftests/i915_perf.c

389

intel_gt_set_wedged(stream->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_perf.c

97

.engine = intel_engine_lookup_user(perf->i915,

sys/dev/pci/drm/i915/selftests/i915_request.c

1009

return rq->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/selftests/i915_request.c

1016

empty_request(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/selftests/i915_request.c

1022

request = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

1039

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1049

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1056

batch = empty_batch(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

1060

err = igt_live_test_begin(&t, i915, __func__, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1064

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1067

request = empty_request(engine, batch);

sys/dev/pci/drm/i915/selftests/i915_request.c

1070

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1080

request = empty_request(engine, batch);

sys/dev/pci/drm/i915/selftests/i915_request.c

1083

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1097

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1104

engine->name,

sys/dev/pci/drm/i915/selftests/i915_request.c

1192

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1213

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1216

batch = recursive_batch(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

1225

request[idx] = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1251

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1254

__func__, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1262

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1273

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1282

__func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

1298

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1322

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1343

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1346

batch = recursive_batch(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

1350

__func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

1355

request[idx] = intel_engine_create_kernel_request(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1359

__func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

1370

__func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

1395

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1400

__func__, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1417

__func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

1429

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1444

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

1459

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1467

struct intel_engine_cs *engine = thread->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1473

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1477

rq = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

1495

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1497

pr_info("%s: %lu request + sync\n", engine->name, count);

sys/dev/pci/drm/i915/selftests/i915_request.c

1505

struct intel_engine_cs *engine = thread->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1511

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1515

rq = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

1524

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1526

pr_info("%s: %lu requests\n", engine->name, count);

sys/dev/pci/drm/i915/selftests/i915_request.c

1557

struct intel_engine_cs *engine = thread->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1568

if (igt_spinner_init(&spin, engine->gt)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1569

wake_all(engine->i915);

sys/dev/pci/drm/i915/selftests/i915_request.c

1574

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1576

engine->kernel_context,

sys/dev/pci/drm/i915/selftests/i915_request.c

1578

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1583

wake_all(engine->i915);

sys/dev/pci/drm/i915/selftests/i915_request.c

1591

err = wait_for_all(engine->i915);

sys/dev/pci/drm/i915/selftests/i915_request.c

1593

pr_err("Failed to start spinner on %s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1618

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1644

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1648

engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1656

threads[idx].engine = engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1664

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1687

max_batches(struct i915_gem_context *ctx, struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/selftests/i915_request.c

1704

rq = igt_request_alloc(ctx, engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1730

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1790

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1792

smoke[idx].engine = engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1794

max_batches(smoke[0].contexts[0], engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1802

smoke[idx].max_batch, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

1831

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

1893

rq = intel_engine_create_kernel_request(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1909

while (!err && !intel_engine_is_idle(ce->engine))

sys/dev/pci/drm/i915/selftests/i915_request.c

1910

intel_engine_flush_submission(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

1916

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

1952

static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)

sys/dev/pci/drm/i915/selftests/i915_request.c

1954

u64 ns = intel_gt_clock_interval_to_ns(engine->gt, cycles);

sys/dev/pci/drm/i915/selftests/i915_request.c

1962

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));

sys/dev/pci/drm/i915/selftests/i915_request.c

2005

return memset32(ce->engine->status_page.addr + 1000, 0, 21);

sys/dev/pci/drm/i915/selftests/i915_request.c

2010

return (i915_ggtt_offset(ce->engine->status_page.vma) +

sys/dev/pci/drm/i915/selftests/i915_request.c

2065

cycles = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/selftests/i915_request.c

2079

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2080

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2082

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2085

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2112

err = intel_gt_wait_for_idle(ce->engine->gt, HZ / 2);

sys/dev/pci/drm/i915/selftests/i915_request.c

2135

elapsed[i] = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/selftests/i915_request.c

2141

err = intel_gt_wait_for_idle(ce->engine->gt, HZ / 2);

sys/dev/pci/drm/i915/selftests/i915_request.c

2150

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2151

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2153

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2156

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2210

elapsed[i - 1] = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/selftests/i915_request.c

2227

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2228

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2230

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2233

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2237

static int plug(struct intel_engine_cs *engine, u32 *sema, u32 mode, int value)

sys/dev/pci/drm/i915/selftests/i915_request.c

2240

i915_ggtt_offset(engine->status_page.vma) +

sys/dev/pci/drm/i915/selftests/i915_request.c

2245

rq = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

2285

err = plug(ce->engine, sema, MI_SEMAPHORE_SAD_NEQ_SDD, 0);

sys/dev/pci/drm/i915/selftests/i915_request.c

2295

intel_engine_flush_submission(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2327

intel_engine_flush_submission(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2331

err = intel_gt_wait_for_idle(ce->engine->gt, HZ / 2);

sys/dev/pci/drm/i915/selftests/i915_request.c

2340

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2341

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2343

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2350

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2376

err = plug(ce->engine, sema, MI_SEMAPHORE_SAD_NEQ_SDD, 0);

sys/dev/pci/drm/i915/selftests/i915_request.c

2382

ce, ce->engine->kernel_context

sys/dev/pci/drm/i915/selftests/i915_request.c

2423

intel_engine_flush_submission(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2426

err = intel_gt_wait_for_idle(ce->engine->gt, HZ / 2);

sys/dev/pci/drm/i915/selftests/i915_request.c

2435

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2436

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2438

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2444

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2473

if (!intel_engine_has_preemption(ce->engine))

sys/dev/pci/drm/i915/selftests/i915_request.c

2505

rq = i915_request_create(ce->engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

2524

elapsed[i - 1] = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/selftests/i915_request.c

253

request->engine->submit_request(request);

sys/dev/pci/drm/i915/selftests/i915_request.c

2538

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2539

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2546

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2547

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2549

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2552

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2614

intel_engine_flush_submission(ce->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2625

elapsed[i - 1] = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);

sys/dev/pci/drm/i915/selftests/i915_request.c

2629

err = intel_gt_wait_for_idle(ce->engine->gt, HZ / 2);

sys/dev/pci/drm/i915/selftests/i915_request.c

2640

ce->engine->name, cycles >> TF_BIAS,

sys/dev/pci/drm/i915/selftests/i915_request.c

2641

cycles_to_ns(ce->engine, cycles));

sys/dev/pci/drm/i915/selftests/i915_request.c

2643

return intel_gt_wait_for_idle(ce->engine->gt, HZ);

sys/dev/pci/drm/i915/selftests/i915_request.c

2646

intel_gt_set_wedged(ce->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2670

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2679

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2682

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2694

st_engine_heartbeat_disable(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2695

rps_pin(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2712

rps_unpin(engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

2713

st_engine_heartbeat_enable(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

282

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2831

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2855

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2858

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2888

p->engine = ps->ce[idx]->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2889

intel_engine_pm_get(p->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2891

if (intel_engine_supports_stats(p->engine))

sys/dev/pci/drm/i915/selftests/i915_request.c

2892

p->busy = intel_engine_get_busy_time(p->engine,

sys/dev/pci/drm/i915/selftests/i915_request.c

2910

p->busy = ktime_sub(intel_engine_get_busy_time(p->engine,

sys/dev/pci/drm/i915/selftests/i915_request.c

2919

intel_engine_pm_put(p->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2933

name, p->engine->name, ce->timeline->seqno,

sys/dev/pci/drm/i915/selftests/i915_request.c

2959

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2967

struct intel_engine_cs *engine = p->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

2974

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

2987

if (intel_engine_supports_stats(engine)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

2988

p->busy = intel_engine_get_busy_time(engine, &p->time);

sys/dev/pci/drm/i915/selftests/i915_request.c

3021

p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now),

sys/dev/pci/drm/i915/selftests/i915_request.c

3041

struct intel_engine_cs *engine = p->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

3049

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3062

if (intel_engine_supports_stats(engine)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

3063

p->busy = intel_engine_get_busy_time(engine, &p->time);

sys/dev/pci/drm/i915/selftests/i915_request.c

3098

p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now),

sys/dev/pci/drm/i915/selftests/i915_request.c

3118

struct intel_engine_cs *engine = p->engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

3125

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3138

if (intel_engine_supports_stats(engine)) {

sys/dev/pci/drm/i915/selftests/i915_request.c

3139

p->busy = intel_engine_get_busy_time(engine, &p->time);

sys/dev/pci/drm/i915/selftests/i915_request.c

3163

p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now),

sys/dev/pci/drm/i915/selftests/i915_request.c

3190

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

3214

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

3217

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3222

engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

3225

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3230

engines[idx].p.engine = engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

3231

engines[idx].engine = engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

3239

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

3250

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3262

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

3277

GEM_BUG_ON(engine != p->engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

3279

name, engine->name, p->count, integer, decimal,

sys/dev/pci/drm/i915/selftests/i915_request.c

369

ce = i915_gem_context_get_engine(ctx, t->engine->legacy_idx);

sys/dev/pci/drm/i915/selftests/i915_request.c

410

t->engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

413

intel_gt_set_wedged(t->engine->gt);

sys/dev/pci/drm/i915/selftests/i915_request.c

457

.engine = rcs0(i915),

sys/dev/pci/drm/i915/selftests/i915_request.c

484

t.contexts[n] = mock_context(t.engine->i915, "mock");

sys/dev/pci/drm/i915/selftests/i915_request.c

52

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

56

for_each_uabi_engine(engine, i915)

sys/dev/pci/drm/i915/selftests/i915_request.c

569

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

579

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

584

err = igt_live_test_begin(&t, i915, __func__, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

588

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

596

request = i915_request_create(engine->kernel_context);

sys/dev/pci/drm/i915/selftests/i915_request.c

627

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

634

engine->name,

sys/dev/pci/drm/i915/selftests/i915_request.c

642

static int __cancel_inactive(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/selftests/i915_request.c

649

if (igt_spinner_init(&spin, engine->gt))

sys/dev/pci/drm/i915/selftests/i915_request.c

652

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

664

pr_debug("%s: Cancelling inactive request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

670

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

672

pr_err("%s: Failed to cancel inactive request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

673

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

680

engine->name, rq->fence.error);

sys/dev/pci/drm/i915/selftests/i915_request.c

691

pr_err("%s: %s error %d\n", __func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

695

static int __cancel_active(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/selftests/i915_request.c

702

if (igt_spinner_init(&spin, engine->gt))

sys/dev/pci/drm/i915/selftests/i915_request.c

705

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

717

pr_debug("%s: Cancelling active request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

721

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

723

pr_err("Failed to start spinner on %s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

724

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

731

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

733

pr_err("%s: Failed to cancel active request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

734

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

741

engine->name, rq->fence.error);

sys/dev/pci/drm/i915/selftests/i915_request.c

752

pr_err("%s: %s error %d\n", __func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

756

static int __cancel_completed(struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/selftests/i915_request.c

763

if (igt_spinner_init(&spin, engine->gt))

sys/dev/pci/drm/i915/selftests/i915_request.c

766

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

786

pr_debug("%s: Cancelling completed request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

790

engine->name, rq->fence.error);

sys/dev/pci/drm/i915/selftests/i915_request.c

801

pr_err("%s: %s error %d\n", __func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

817

struct intel_engine_cs *engine)

sys/dev/pci/drm/i915/selftests/i915_request.c

826

!intel_has_reset_engine(engine->gt))

sys/dev/pci/drm/i915/selftests/i915_request.c

829

preempt_timeout_ms = engine->props.preempt_timeout_ms;

sys/dev/pci/drm/i915/selftests/i915_request.c

830

engine->props.preempt_timeout_ms = 100;

sys/dev/pci/drm/i915/selftests/i915_request.c

832

if (igt_spinner_init(&spin, engine->gt))

sys/dev/pci/drm/i915/selftests/i915_request.c

835

ce = intel_context_create(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

848

engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

852

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

854

pr_err("Failed to start spinner on %s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

855

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

869

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

871

pr_err("%s: Failed to cancel hung request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

872

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

879

engine->name, rq->fence.error);

sys/dev/pci/drm/i915/selftests/i915_request.c

885

struct drm_printer p = drm_info_printer(engine->i915->drm.dev);

sys/dev/pci/drm/i915/selftests/i915_request.c

887

pr_err("%s: Failed to complete nop request\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

888

intel_engine_dump(engine, &p, "%s\n", engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

895

engine->name, nop->fence.error);

sys/dev/pci/drm/i915/selftests/i915_request.c

908

engine->props.preempt_timeout_ms = preempt_timeout_ms;

sys/dev/pci/drm/i915/selftests/i915_request.c

910

pr_err("%s: %s error %d\n", __func__, engine->name, err);

sys/dev/pci/drm/i915/selftests/i915_request.c

917

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/i915_request.c

924

for_each_uabi_engine(engine, i915) {

sys/dev/pci/drm/i915/selftests/i915_request.c

928

if (!intel_engine_has_preemption(engine))

sys/dev/pci/drm/i915/selftests/i915_request.c

931

err = igt_live_test_begin(&t, i915, __func__, engine->name);

sys/dev/pci/drm/i915/selftests/i915_request.c

935

err = __cancel_inactive(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

937

err = __cancel_active(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

939

err = __cancel_completed(engine);

sys/dev/pci/drm/i915/selftests/i915_request.c

948

err = __cancel_reset(i915, engine);

sys/dev/pci/drm/i915/selftests/igt_flush_test.c

22

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/igt_flush_test.c

29

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/selftests/igt_flush_test.c

30

if (engine->props.preempt_timeout_ms > timeout_ms)

sys/dev/pci/drm/i915/selftests/igt_flush_test.c

31

timeout_ms = engine->props.preempt_timeout_ms;

sys/dev/pci/drm/i915/selftests/igt_live_test.c

20

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/igt_live_test.c

39

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/selftests/igt_live_test.c

42

engine);

sys/dev/pci/drm/i915/selftests/igt_live_test.c

53

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/igt_live_test.c

69

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/selftests/igt_live_test.c

71

i915_reset_engine_count(&i915->gpu_error, engine))

sys/dev/pci/drm/i915/selftests/igt_live_test.c

75

t->func, t->name, engine->name,

sys/dev/pci/drm/i915/selftests/igt_live_test.c

76

i915_reset_engine_count(&i915->gpu_error, engine) -

sys/dev/pci/drm/i915/selftests/igt_reset.c

16

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/igt_reset.c

25

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/selftests/igt_reset.c

35

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/igt_reset.c

38

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/selftests/igt_spinner.c

128

struct intel_engine_cs *engine = ce->engine;

sys/dev/pci/drm/i915/selftests/igt_spinner.c

137

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/selftests/igt_spinner.c

199

intel_gt_chipset_flush(engine->gt);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

201

if (engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/selftests/igt_spinner.c

202

err = engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

210

err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

257

intel_engine_flush_submission(rq->engine);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1000

for (engine = intel_engine_lookup_user(i915, class, 0);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1001

engine && engine->uabi_class == class;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1002

engine = rb_entry_safe(rb_next(&engine->uabi_node),

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1003

typeof(*engine), uabi_node))

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1026

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1035

engine = random_engine_class(i915, I915_ENGINE_CLASS_COPY, &prng);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1036

if (!engine)

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1039

pr_info("%s: using %s\n", __func__, engine->name);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1063

intel_engine_pm_get(engine);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1064

err = intel_context_migrate_clear(engine->gt->migrate.context, NULL,

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1075

intel_engine_pm_put(engine);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

726

if (!intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

758

if (!ce || !intel_engine_can_store_dword(ce->engine))

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

996

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

21

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

24

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

25

return engine;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

31

int intel_selftest_modify_policy(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

37

saved->reset = engine->i915->params.reset;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

38

saved->flags = engine->flags;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

39

saved->timeslice = engine->props.timeslice_duration_ms;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

40

saved->preempt_timeout = engine->props.preempt_timeout_ms;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

52

engine->i915->params.reset = 2;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

53

engine->flags |= I915_ENGINE_WANT_FORCED_PREEMPTION;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

54

engine->props.timeslice_duration_ms = REDUCED_TIMESLICE;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

55

engine->props.preempt_timeout_ms = REDUCED_PREEMPT;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

59

engine->props.preempt_timeout_ms = 0;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

67

if (!intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

70

err = intel_guc_global_policies_update(&engine->gt->uc.guc);

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

72

intel_selftest_restore_policy(engine, saved);

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

77

int intel_selftest_restore_policy(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

81

engine->i915->params.reset = saved->reset;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

82

engine->flags = saved->flags;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

83

engine->props.timeslice_duration_ms = saved->timeslice;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

84

engine->props.preempt_timeout_ms = saved->preempt_timeout;

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

86

if (!intel_engine_uses_guc(engine))

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.c

89

return intel_guc_global_policies_update(&engine->gt->uc.guc);

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

28

int intel_selftest_modify_policy(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/selftests/intel_scheduler_helpers.h

31

int intel_selftest_restore_policy(struct intel_engine_cs *engine,

sys/dev/pci/drm/i915/selftests/intel_uncore.c

165

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

210

for_each_engine(engine, gt, id) {

sys/dev/pci/drm/i915/selftests/intel_uncore.c

211

i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);

sys/dev/pci/drm/i915/selftests/intel_uncore.c

212

u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset;

sys/dev/pci/drm/i915/selftests/intel_uncore.c

216

if (!engine->default_state)

sys/dev/pci/drm/i915/selftests/intel_uncore.c

256

engine->name, r->name);

sys/dev/pci/drm/i915/selftests/intel_uncore.c

264

engine->name, r->name, readl(reg), fw_domains);

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

240

to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0);

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

241

if (!to_gt(i915)->engine[RCS0])

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

244

if (mock_engine_init(to_gt(i915)->engine[RCS0]))

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

51

struct intel_engine_cs *engine;

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

55

for_each_engine(engine, gt, id)

sys/dev/pci/drm/i915/selftests/mock_gem_device.c

56

mock_engine_flush(engine);

sys/dev/pci/drm/i915/selftests/mock_request.c

46

struct mock_engine *engine =

sys/dev/pci/drm/i915/selftests/mock_request.c

47

container_of(request->engine, typeof(*engine), base);

sys/dev/pci/drm/i915/selftests/mock_request.c

50

spin_lock_irq(&engine->hw_lock);

sys/dev/pci/drm/i915/selftests/mock_request.c

53

spin_unlock_irq(&engine->hw_lock);

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

2206

struct i915_engine_class_instance engine;

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

2578

struct i915_engine_class_instance engine;

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

3347

struct i915_engine_class_instance engine;

usr.bin/make/enginechoice.c

38

*engine;

usr.bin/make/enginechoice.c

43

engine = compat ? &compat_engine: &parallel_engine;

usr.bin/make/enginechoice.c

44

engine->init();

usr.bin/make/enginechoice.c

50

engine->run_list(l, has_errors, out_of_date);

usr.bin/make/enginechoice.c

56

engine->node_updated(gn);

usr.sbin/lpd/lpd.c

119

engine(debug, verbose);

usr.sbin/lpd/lpd.h

111

void engine(int, int);

usr.sbin/rad/engine.h

20

void engine(int, int);

usr.sbin/rad/rad.c

179

engine(debug, cmd_opts & OPT_VERBOSE);