sys/dev/pci/drm/i915/display/g4x_dp.c

35

static const struct dpll g4x_dpll[] = {

sys/dev/pci/drm/i915/display/g4x_dp.c

40

static const struct dpll pch_dpll[] = {

sys/dev/pci/drm/i915/display/g4x_dp.c

45

static const struct dpll vlv_dpll[] = {

sys/dev/pci/drm/i915/display/g4x_dp.c

50

static const struct dpll chv_dpll[] = {

sys/dev/pci/drm/i915/display/g4x_dp.c

56

const struct dpll *vlv_get_dpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/g4x_dp.c

65

const struct dpll *divisor = NULL;

sys/dev/pci/drm/i915/display/g4x_dp.c

85

pipe_config->dpll = divisor[i];

sys/dev/pci/drm/i915/display/g4x_dp.h

21

const struct dpll *vlv_get_dpll(struct intel_display *display);

sys/dev/pci/drm/i915/display/g4x_dp.h

28

static inline const struct dpll *vlv_get_dpll(struct intel_display *display)

sys/dev/pci/drm/i915/display/icl_dsi.c

629

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

635

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

645

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

651

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

681

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/icl_dsi.c

697

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1555

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1565

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1571

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1575

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1850

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1855

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1864

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1869

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1954

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1962

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1970

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_ddi.c

1975

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_display.c

1331

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_display.c

3091

tmp = pipe_config->dpll_hw_state.i9xx.dpll;

sys/dev/pci/drm/i915/display/intel_display.c

5348

if (display->dpll.mgr)

sys/dev/pci/drm/i915/display/intel_display.c

5352

if (display->dpll.mgr || HAS_GMCH(display))

sys/dev/pci/drm/i915/display/intel_display.c

8237

struct dpll clock = {

sys/dev/pci/drm/i915/display/intel_display.c

8244

u32 dpll, fp;

sys/dev/pci/drm/i915/display/intel_display.c

8255

dpll = DPLL_DVO_2X_MODE |

sys/dev/pci/drm/i915/display/intel_display.c

8286

dpll & ~DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_display.c

8287

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8298

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display.c

8302

intel_de_write(display, DPLL(display, pipe), dpll);

sys/dev/pci/drm/i915/display/intel_display_core.h

303

const struct intel_dpll_global_funcs *dpll;

sys/dev/pci/drm/i915/display/intel_display_core.h

587

struct intel_dpll_global dpll;

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

629

display->dpll.ref_clks.nssc,

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

630

display->dpll.ref_clks.ssc);

sys/dev/pci/drm/i915/display/intel_display_types.h

1087

struct dpll dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1003

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1004

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1007

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1009

dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;

sys/dev/pci/drm/i915/display/intel_dpll.c

1012

dpll |= DPLLB_MODE_LVDS;

sys/dev/pci/drm/i915/display/intel_dpll.c

1014

dpll |= DPLLB_MODE_DAC_SERIAL;

sys/dev/pci/drm/i915/display/intel_dpll.c

1018

dpll |= (crtc_state->pixel_multiplier - 1)

sys/dev/pci/drm/i915/display/intel_dpll.c

1024

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/pci/drm/i915/display/intel_dpll.c

1027

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/pci/drm/i915/display/intel_dpll.c

1031

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1032

dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1034

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

sys/dev/pci/drm/i915/display/intel_dpll.c

1037

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1043

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

sys/dev/pci/drm/i915/display/intel_dpll.c

1046

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

sys/dev/pci/drm/i915/display/intel_dpll.c

1049

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

sys/dev/pci/drm/i915/display/intel_dpll.c

1052

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

sys/dev/pci/drm/i915/display/intel_dpll.c

1058

dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

sys/dev/pci/drm/i915/display/intel_dpll.c

1061

dpll |= PLL_REF_INPUT_TVCLKINBC;

sys/dev/pci/drm/i915/display/intel_dpll.c

1064

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/pci/drm/i915/display/intel_dpll.c

1066

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/pci/drm/i915/display/intel_dpll.c

1068

return dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1072

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1073

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1086

hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1093

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1094

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1097

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1099

dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;

sys/dev/pci/drm/i915/display/intel_dpll.c

1102

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1105

dpll |= PLL_P1_DIVIDE_BY_TWO;

sys/dev/pci/drm/i915/display/intel_dpll.c

1107

dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1109

dpll |= PLL_P2_DIVIDE_BY_4;

sys/dev/pci/drm/i915/display/intel_dpll.c

1128

dpll |= DPLL_DVO_2X_MODE;

sys/dev/pci/drm/i915/display/intel_dpll.c

1132

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/pci/drm/i915/display/intel_dpll.c

1134

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/pci/drm/i915/display/intel_dpll.c

1136

return dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1140

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1141

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1148

hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1250

static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)

sys/dev/pci/drm/i915/display/intel_dpll.c

1252

return dpll->m < factor * dpll->n;

sys/dev/pci/drm/i915/display/intel_dpll.c

1255

static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)

sys/dev/pci/drm/i915/display/intel_dpll.c

1267

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1268

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1271

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1273

dpll = DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_dpll.c

1276

dpll |= DPLLB_MODE_LVDS;

sys/dev/pci/drm/i915/display/intel_dpll.c

1278

dpll |= DPLLB_MODE_DAC_SERIAL;

sys/dev/pci/drm/i915/display/intel_dpll.c

1280

dpll |= (crtc_state->pixel_multiplier - 1)

sys/dev/pci/drm/i915/display/intel_dpll.c

1285

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/pci/drm/i915/display/intel_dpll.c

1288

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/pci/drm/i915/display/intel_dpll.c

1306

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/pci/drm/i915/display/intel_dpll.c

1309

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1311

dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1315

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

sys/dev/pci/drm/i915/display/intel_dpll.c

1318

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

sys/dev/pci/drm/i915/display/intel_dpll.c

1321

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

sys/dev/pci/drm/i915/display/intel_dpll.c

1324

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

sys/dev/pci/drm/i915/display/intel_dpll.c

1331

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/pci/drm/i915/display/intel_dpll.c

1333

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/pci/drm/i915/display/intel_dpll.c

1335

return dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1339

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1340

const struct dpll *reduced_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

1348

hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1390

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1393

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1395

ilk_compute_dpll(crtc_state, &crtc_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll.c

1396

&crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1402

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1424

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1426

dpll = DPLL_INTEGRATED_REF_CLK_VLV |

sys/dev/pci/drm/i915/display/intel_dpll.c

1430

dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

sys/dev/pci/drm/i915/display/intel_dpll.c

1434

dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;

sys/dev/pci/drm/i915/display/intel_dpll.c

1436

return dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1443

hw_state->dpll = vlv_dpll(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1450

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1452

dpll = DPLL_SSC_REF_CLK_CHV |

sys/dev/pci/drm/i915/display/intel_dpll.c

1456

dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

sys/dev/pci/drm/i915/display/intel_dpll.c

1460

dpll |= DPLL_VCO_ENABLE;

sys/dev/pci/drm/i915/display/intel_dpll.c

1462

return dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1469

hw_state->dpll = chv_dpll(crtc_state);

sys/dev/pci/drm/i915/display/intel_dpll.c

1483

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1486

chv_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1494

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1510

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1513

vlv_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1521

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1560

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1563

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1565

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll.c

1566

&crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1568

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1600

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1603

pnv_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1605

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll.c

1606

&crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1608

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1638

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1641

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1643

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll.c

1644

&crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1646

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1680

refclk, NULL, &crtc_state->dpll))

sys/dev/pci/drm/i915/display/intel_dpll.c

1683

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1685

i8xx_compute_dpll(crtc_state, &crtc_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll.c

1686

&crtc_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1688

crtc_state->port_clock = crtc_state->dpll.dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

1752

ret = display->funcs.dpll->crtc_compute_clock(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1776

if (!display->funcs.dpll->crtc_get_dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

1779

ret = display->funcs.dpll->crtc_get_dpll(state, crtc);

sys/dev/pci/drm/i915/display/intel_dpll.c

1793

display->funcs.dpll = &mtl_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1795

display->funcs.dpll = &dg2_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1797

display->funcs.dpll = &hsw_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1799

display->funcs.dpll = &ilk_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1801

display->funcs.dpll = &chv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1803

display->funcs.dpll = &vlv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1805

display->funcs.dpll = &g4x_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1807

display->funcs.dpll = &pnv_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1809

display->funcs.dpll = &i9xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1811

display->funcs.dpll = &i8xx_dpll_funcs;

sys/dev/pci/drm/i915/display/intel_dpll.c

1845

hw_state->dpll & ~DPLL_VGA_MODE_DIS);

sys/dev/pci/drm/i915/display/intel_dpll.c

1846

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1861

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1866

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

1905

const struct dpll *clock = &crtc_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1989

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

2011

hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));

sys/dev/pci/drm/i915/display/intel_dpll.c

2013

if (hw_state->dpll & DPLL_VCO_ENABLE) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2026

const struct dpll *clock = &crtc_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

2136

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll.c

2157

hw_state->dpll & ~DPLL_VCO_ENABLE);

sys/dev/pci/drm/i915/display/intel_dpll.c

2159

if (hw_state->dpll & DPLL_VCO_ENABLE) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2202

const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

2213

crtc_state->dpll = *dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

318

static int pnv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

331

static u32 i9xx_dpll_compute_m(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

333

return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);

sys/dev/pci/drm/i915/display/intel_dpll.c

336

int i9xx_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

349

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

362

int chv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

380

if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)

sys/dev/pci/drm/i915/display/intel_dpll.c

409

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

sys/dev/pci/drm/i915/display/intel_dpll.c

416

hw_state->dpll &= ~(DPLL_LOCK_VLV |

sys/dev/pci/drm/i915/display/intel_dpll.c

428

u32 dpll = hw_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

430

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

434

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

sys/dev/pci/drm/i915/display/intel_dpll.c

450

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

453

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

456

switch (dpll & DPLL_MODE_MASK) {

sys/dev/pci/drm/i915/display/intel_dpll.c

458

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

sys/dev/pci/drm/i915/display/intel_dpll.c

462

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

sys/dev/pci/drm/i915/display/intel_dpll.c

468

"mode\n", (int)(dpll & DPLL_MODE_MASK));

sys/dev/pci/drm/i915/display/intel_dpll.c

484

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

492

if (dpll & PLL_P1_DIVIDE_BY_TWO)

sys/dev/pci/drm/i915/display/intel_dpll.c

495

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

498

if (dpll & PLL_P2_DIVIDE_BY_4)

sys/dev/pci/drm/i915/display/intel_dpll.c

523

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

527

if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_dpll.c

550

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

555

if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/pci/drm/i915/display/intel_dpll.c

583

const struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

657

const struct dpll *match_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

658

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

661

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

715

const struct dpll *match_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

716

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

719

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

771

const struct dpll *match_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

772

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

775

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

822

const struct dpll *calculated_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

823

const struct dpll *best_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

865

const struct dpll *match_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

866

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

869

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

922

const struct dpll *match_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

923

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

927

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

977

struct dpll *best_clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

987

u32 i9xx_dpll_compute_fp(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

989

return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;

sys/dev/pci/drm/i915/display/intel_dpll.c

992

static u32 pnv_dpll_compute_fp(const struct dpll *dpll)

sys/dev/pci/drm/i915/display/intel_dpll.c

994

return (1 << dpll->n) << 16 | dpll->m2;

sys/dev/pci/drm/i915/display/intel_dpll.h

12

struct dpll;

sys/dev/pci/drm/i915/display/intel_dpll.h

24

int i9xx_calc_dpll_params(int refclk, struct dpll *clock);

sys/dev/pci/drm/i915/display/intel_dpll.h

25

u32 i9xx_dpll_compute_fp(const struct dpll *dpll);

sys/dev/pci/drm/i915/display/intel_dpll.h

32

const struct dpll *dpll);

sys/dev/pci/drm/i915/display/intel_dpll.h

42

struct dpll *best_clock);

sys/dev/pci/drm/i915/display/intel_dpll.h

43

int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1011

refclk = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1021

refclk = display->dpll.ref_clks.ssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1246

display->dpll.ref_clks.ssc = 135000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1249

display->dpll.ref_clks.nssc = 24000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1251

display->dpll.ref_clks.nssc = 135000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1743

int ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1818

display->dpll.ref_clks.nssc, &wrpll_params);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1984

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2252

static const struct dpll bxt_dp_clk_val[] = {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2265

struct dpll *clk_div)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2283

struct dpll *clk_div)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2296

chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2303

const struct dpll *clk_div)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2375

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2386

return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2392

struct dpll clk_div = {};

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2403

struct dpll clk_div = {};

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2460

display->dpll.ref_clks.ssc = 100000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2461

display->dpll.ref_clks.nssc = 100000;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2618

display->dpll.ref_clks.nssc == 38400;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

269

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2712

display->dpll.ref_clks.nssc == 24000 ?

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2735

switch (display->dpll.ref_clks.nssc) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2737

MISSING_CASE(display->dpll.ref_clks.nssc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2748

switch (display->dpll.ref_clks.nssc) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2750

MISSING_CASE(display->dpll.ref_clks.nssc);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2780

int ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

295

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3010

int refclk_khz = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

318

mutex_lock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3217

ref_clock = display->dpll.ref_clks.nssc;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

341

mutex_unlock(&display->dpll.lock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3598

if (display->dpll.ref_clks.nssc == 38400) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4090

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4321

rw_init(&display->dpll.lock, "dplllk");

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4356

i >= ARRAY_SIZE(display->dpll.dplls)))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4363

display->dpll.dplls[i].info = &dpll_info[i];

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4364

display->dpll.dplls[i].index = i;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4367

display->dpll.mgr = dpll_mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4368

display->dpll.num_dpll = i;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4390

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4423

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4446

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4475

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4543

if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4544

display->dpll.mgr->update_ref_clks(display);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4597

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4598

display->dpll.mgr->dump_hw_state(p, dpll_hw_state);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4621

if (display->dpll.mgr) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

4622

return display->dpll.mgr->compare_hw_state(a, b);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

543

hw_state->dpll = val;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

577

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

588

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

655

hw_state->dpll,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

667

return a->dpll == b->dpll &&

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

729

if (display->dpll.pch_ssc_use & BIT(id))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

745

if (display->dpll.pch_ssc_use & BIT(id))

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

191

u32 dpll;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

34

for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

35

((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++)

sys/dev/pci/drm/i915/display/intel_dvo.c

422

u32 dpll[I915_MAX_PIPES];

sys/dev/pci/drm/i915/display/intel_dvo.c

461

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

sys/dev/pci/drm/i915/display/intel_dvo.c

468

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

sys/dev/pci/drm/i915/display/intel_pch_display.c

539

tmp = crtc_state->dpll_hw_state.i9xx.dpll;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

473

display->dpll.pch_ssc_use = 0;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

477

display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

482

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

487

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

490

if (display->dpll.pch_ssc_use)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1286

struct dpll *clock = &pipe_config->dpll;

sys/dev/pci/drm/i915/gvt/handlers.c

555

struct dpll clock = {};