Symbol: div_u64
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1038
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
1040
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
921
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
774
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
896
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
898
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
874
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
991
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
993
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11191
res = div_u64(num, den);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
681
refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8654
target_vtotal = div_u64(num, den);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9883
bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
905
peak_kbps = div_u64(peak_kbps, 1000 * 1000);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
977
kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1546
div_u64(pixel_clk * pixel_clk_10_khz_out,
sys/dev/pci/drm/amd/display/dc/bios/command_table.c
1596
div_u64(pixel_clk * pixel_clk_10_khz_out,
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
580
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
581
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
483
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
484
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
586
frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
587
frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
588
frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
590
int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
577
phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
621
phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
619
dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
1212
*pixel_clk_khz = div_u64((uint64_t)clock_hz*
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
151
feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
162
div_u64(feedback_divider,
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
222
div_u64(actual_calc_clk_100hz,
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
245
div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
83
current_backlight = div_u64(current_backlight, bl_period);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
967
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
97
pix_dur = div_u64(10000000000ull, pix_clk_100hz);
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
97
pix_dur = div_u64(10000000000ull, pix_clk_100hz);
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
81
current_backlight = div_u64(current_backlight, bl_period);
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
981
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
491
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
322
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
270
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
302
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
285
m_vid_l = div_u64(m_vid_l,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1881
min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1004
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1005
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3405
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3406
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c
115
(uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)),
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2434
phase[i] = div_u64(phase[i], get_clock_divider(grouped_pipes[i], true));
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1005
tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1029
tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
977
unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
678
div_u64(time_taken_in_ns, 1000000));
sys/dev/pci/drm/amd/display/dc/link/link_detection.c
686
div_u64(time_taken_in_ns, 1000000));
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
303
L = div_u64(L, master_h_total);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
304
L = div_u64(L, slave_pixel_clock_100Hz);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
305
XY = div_u64(L, p);
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
307
X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
667
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
668
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
728
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
729
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
sys/dev/pci/drm/amd/display/dc/sspl/spl_os_types.h
31
return div_u64(dividend, divisor);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1018
div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1021
min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1055
refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1056
div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1185
div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
1286
nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total);
sys/dev/pci/drm/amd/display/modules/freesync/freesync.c
198
v_total = div_u64((unsigned long long)duration_in_us
sys/dev/pci/drm/drm_file.c
896
sz = div_u64(sz, SZ_1K);
sys/dev/pci/drm/drm_vblank.c
639
linedur_ns = div_u64((u64) mode->crtc_htotal * 1000000, dotclock);
sys/dev/pci/drm/drm_vblank.c
640
framedur_ns = div_u64((u64) frame_size * 1000000, dotclock);
sys/dev/pci/drm/i915/display/intel_crtc.c
607
div_u64(delta, 1000),
sys/dev/pci/drm/i915/display/intel_display.c
2509
*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
sys/dev/pci/drm/i915/display/intel_dp.c
818
return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
sys/dev/pci/drm/i915/display/intel_dpll.c
840
*error_ppm = div_u64(1000000ULL *
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1660
params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1662
div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2602
dco = div_u64((u64)dco_freq << 15, ref_freq);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3277
tmp = div_u64(tmp, 5 * div1 * div2);
sys/dev/pci/drm/i915/display/intel_psr.c
1319
hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
sys/dev/pci/drm/i915/display/intel_vblank.c
171
return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
sys/dev/pci/drm/i915/gem/i915_gem_wait.c
184
div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
1255
max = div_u64(max - size, max_page_size);
sys/dev/pci/drm/i915/gem/selftests/huge_pages.c
238
unsigned int len = min(page_size * div_u64(rem, page_size),
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
186
div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX),
sys/dev/pci/drm/i915/gt/intel_gt_clock_utils.c
203
return div_u64(nom + den - 1, den);
sys/dev/pci/drm/i915/gt/intel_rps.c
132
busy += div_u64(max_busy[i], 1 << i);
sys/dev/pci/drm/i915/gt/intel_rps.c
1523
corr = div_u64(corr * 150142 * state1, 10000) - 78642;
sys/dev/pci/drm/i915/gt/intel_rps.c
1524
corr2 = div_u64(corr, 100000) * ips->corr;
sys/dev/pci/drm/i915/gt/intel_rps.c
1526
state2 = div_u64(corr2 * state1, 10000);
sys/dev/pci/drm/i915/gt/intel_rps.c
351
result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10);
sys/dev/pci/drm/i915/gt/intel_rps.c
420
ips->gfx_power = div_u64(delta * 1181, dt * 10);
sys/dev/pci/drm/i915/gt/selftest_gt_pm.c
76
*out_dt = div_u64(dt[1] + 2 * dt[2] + dt[3], 4);
sys/dev/pci/drm/i915/gt/selftest_rps.c
1123
return div_u64(x[1] + 2 * x[2] + x[3], 4);
sys/dev/pci/drm/i915/gt/selftest_rps.c
319
dt = div_u64(dt_[1] + 2 * dt_[2] + dt_[3], 4);
sys/dev/pci/drm/i915/gt/selftest_rps.c
565
return div_u64(x[1] + 2 * x[2] + x[3], 4);
sys/dev/pci/drm/i915/gt/selftest_rps.c
596
return div_u64(x[1] + 2 * x[2] + x[3], 4);
sys/dev/pci/drm/i915/gt/selftest_slpc.c
110
return div_u64(x[1] + 2 * x[2] + x[3], 4);
sys/dev/pci/drm/i915/gvt/handlers.c
698
pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
sys/dev/pci/drm/i915/i915_perf.c
3976
return div_u64(nom + den - 1, den);
sys/dev/pci/drm/i915/i915_pmu.c
689
div_u64(read_sample(pmu, gt_id,
sys/dev/pci/drm/i915/i915_pmu.c
695
div_u64(read_sample(pmu, gt_id,
sys/dev/pci/drm/i915/selftests/i915_perf.c
278
div_u64(3 * expected, 4000),
sys/dev/pci/drm/i915/selftests/i915_perf.c
279
div_u64(3 * expected, 2000));
sys/dev/pci/drm/i915/selftests/i915_request.c
2935
div_u64(p->runtime, 1000 * 1000),
sys/dev/pci/drm/i915/selftests/i915_request.c
2936
div_u64(ktime_to_ns(p->time), 1000 * 1000));
sys/dev/pci/drm/i915/selftests/i915_request.c
3280
div_u64(p->runtime, 1000 * 1000),
sys/dev/pci/drm/i915/selftests/i915_request.c
3281
div_u64(ktime_to_ns(p->time), 1000 * 1000));
sys/dev/pci/drm/include/linux/math64.h
62
return div_u64(x + y - 1, y);
sys/dev/pci/drm/radeon/cik.c
9144
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/radeon/cik.c
9261
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/radeon/cik.c
9263
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
sys/dev/pci/drm/radeon/evergreen.c
2173
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/radeon/evergreen.c
2175
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
sys/dev/pci/drm/radeon/si.c
2211
tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
sys/dev/pci/drm/radeon/si.c
2291
active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
sys/dev/pci/drm/radeon/si.c
2293
line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,