sys/dev/fdt/rkvop.c
262
struct drm_crtc_state *crtc_state;
sys/dev/fdt/rkvop.c
269
crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
sys/dev/fdt/rkvop.c
270
if (IS_ERR(crtc_state))
sys/dev/fdt/rkvop.c
271
return PTR_ERR(crtc_state);
sys/dev/fdt/rkvop.c
273
return drm_atomic_helper_check_plane_state(state, crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10176
static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10179
stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10183
struct dm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10185
dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10390
struct dm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10425
if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10483
dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10956
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10978
crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10981
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10982
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10987
crtc_state->mode_changed = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12088
struct drm_crtc_state *crtc_state = &dm_crtc_state->base;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12117
if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12138
if (!consider_mode_change && !crtc_state->zpos_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12147
!(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12152
crtc_state->crtc->cursor);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12166
if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12190
plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12191
plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12210
struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12215
drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5977
static bool modereset_required(struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
5979
return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6155
struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6157
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6263
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
6268
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8224
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8227
struct drm_atomic_state *state = crtc_state->state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8231
const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
8262
if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9578
struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9598
if (crtc_state && crtc_state->stream) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9599
dc_stream_set_cursor_position(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9601
update->cursor_position = &crtc_state->stream->cursor_position;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9621
if (crtc_state->cm_is_degamma_srgb &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9628
if (crtc_state->stream) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9629
if (!dc_stream_set_cursor_attributes(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9633
update->cursor_attributes = &crtc_state->stream->cursor_attributes;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9635
if (!dc_stream_set_cursor_position(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9639
update->cursor_position = &crtc_state->stream->cursor_position;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h
1058
int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
860
int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
865
lut = __extract_blob_lut(crtc_state->degamma_lut, &size);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
873
lut = __extract_blob_lut(crtc_state->gamma_lut, &size);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
548
struct dm_crtc_state *crtc_state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
592
crtc_state = to_dm_crtc_state(crtc->state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
666
amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
669
if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
698
crtc_state->crc_skip_count = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
725
struct dm_crtc_state *crtc_state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
736
crtc_state = to_dm_crtc_state(crtc->state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
737
stream_state = crtc_state->stream;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
755
if (crtc_state->crc_skip_count < 2) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
756
crtc_state->crc_skip_count += 1;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
61
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
65
return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
655
struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
659
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
662
trace_amdgpu_dm_crtc_atomic_check(crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
664
amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
667
amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
677
if (crtc_state->enable &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
678
!(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
687
if (crtc_state->async_flip &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
32
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1345
struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1365
if (crtc_state && crtc_state->stream) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1367
dc_stream_program_cursor_position(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1389
if (crtc_state->cm_is_degamma_srgb &&
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1396
if (crtc_state->stream) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1398
if (!dc_stream_program_cursor_attributes(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1402
if (!dc_stream_program_cursor_position(crtc_state->stream,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
167
__field(const struct drm_crtc_state *, crtc_state)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
189
__entry->crtc_state = state;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
214
__entry->crtc_id, __entry->crtc_state, __entry->state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
44
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
48
const struct drm_display_mode *mode = &crtc_state->mode;
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
2037
enum crtc_state state)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h
277
enum crtc_state state);
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
225
enum crtc_state state)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
751
enum crtc_state state)
sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h
127
enum crtc_state state);
sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h
246
enum crtc_state state);
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
832
enum crtc_state state)
sys/dev/pci/drm/apple/apple_drv.c
105
crtc_state,
sys/dev/pci/drm/apple/apple_drv.c
194
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/apple_drv.c
195
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/apple/apple_drv.c
197
if (crtc_state->active_changed && crtc_state->active) {
sys/dev/pci/drm/apple/apple_drv.c
202
if (crtc_state->active)
sys/dev/pci/drm/apple/apple_drv.c
209
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/apple_drv.c
210
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/apple/apple_drv.c
212
if (crtc_state->active_changed && !crtc_state->active) {
sys/dev/pci/drm/apple/apple_drv.c
81
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/apple_drv.c
88
crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
sys/dev/pci/drm/apple/apple_drv.c
89
if (IS_ERR(crtc_state))
sys/dev/pci/drm/apple/apple_drv.c
90
return PTR_ERR(crtc_state);
sys/dev/pci/drm/apple/dcp.c
219
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/dcp.c
226
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/apple/dcp.c
228
needs_modeset = drm_atomic_crtc_needs_modeset(crtc_state) || !dcp->valid_mode;
sys/dev/pci/drm/apple/dcp_backlight.c
142
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/dcp_backlight.c
157
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/apple/dcp_backlight.c
158
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/apple/dcp_backlight.c
159
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/apple/dcp_backlight.c
163
crtc_state->color_mgmt_changed |= true;
sys/dev/pci/drm/apple/iomfb.c
430
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/iomfb.c
434
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/apple/iomfb.c
435
if (!crtc_state)
sys/dev/pci/drm/apple/iomfb.c
438
modeset = drm_atomic_crtc_needs_modeset(crtc_state) || !dcp->valid_mode;
sys/dev/pci/drm/apple/iomfb.c
444
if (crtc_state->mode.hdisplay == 0 && crtc_state->mode.vdisplay == 0)
sys/dev/pci/drm/apple/iomfb.c
449
ret = iomfb_modeset_v12_3(dcp, crtc_state);
sys/dev/pci/drm/apple/iomfb.c
452
ret = iomfb_modeset_v13_3(dcp, crtc_state);
sys/dev/pci/drm/apple/iomfb_template.c
1173
struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/apple/iomfb_template.c
1180
mode = lookup_mode(dcp, &crtc_state->mode);
sys/dev/pci/drm/apple/iomfb_template.c
1183
DRM_MODE_ARG(&crtc_state->mode));
sys/dev/pci/drm/apple/iomfb_template.c
1190
DRM_MODE_ARG(&crtc_state->mode));
sys/dev/pci/drm/apple/iomfb_template.c
1260
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/apple/iomfb_template.c
1265
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/apple/iomfb_template.c
1379
if (!has_surface && !crtc_state->color_mgmt_changed) {
sys/dev/pci/drm/apple/iomfb_template.c
1380
if (crtc_state->enable && crtc_state->active &&
sys/dev/pci/drm/apple/iomfb_template.c
1381
!crtc_state->planes_changed) {
sys/dev/pci/drm/apple/iomfb_template.c
1403
if (crtc_state->color_mgmt_changed && crtc_state->ctm) {
sys/dev/pci/drm/apple/iomfb_template.c
1405
struct drm_color_ctm *ctm = (struct drm_color_ctm *)crtc_state->ctm->data;
sys/dev/pci/drm/apple/iomfb_template.h
176
struct drm_crtc_state *crtc_state);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4552
struct drm_crtc_state *crtc_state =
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4556
if (!crtc_state || !drm_atomic_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4559
if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4609
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4624
for_each_new_crtc_in_state(state, crtc, crtc_state, j) {
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4627
drm_crtc_commit_get(crtc_state->commit);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4714
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4718
crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4719
if (crtc_state && drm_atomic_crtc_needs_modeset(crtc_state)) {
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4729
crtc_state = drm_atomic_get_new_crtc_state(state, old_conn_state->crtc);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
4730
if (crtc_state && drm_atomic_crtc_needs_modeset(crtc_state)) {
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5434
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5461
crtc_state = drm_atomic_get_crtc_state(mst_state->base.state, crtc);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5463
if (IS_ERR(crtc_state))
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5464
return PTR_ERR(crtc_state);
sys/dev/pci/drm/display/drm_dp_mst_topology.c
5469
crtc_state->mode_changed = true;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
333
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
344
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
345
if (!crtc_state)
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
348
return &crtc_state->mode;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
860
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
862
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
863
if (IS_ERR(crtc_state))
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
864
return PTR_ERR(crtc_state);
sys/dev/pci/drm/display/drm_hdmi_state_helper.c
866
crtc_state->mode_changed = true;
sys/dev/pci/drm/drm_atomic.c
1193
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
1195
crtc_state = drm_atomic_get_crtc_state(state,
sys/dev/pci/drm/drm_atomic.c
1197
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic.c
1198
return ERR_CAST(crtc_state);
sys/dev/pci/drm/drm_atomic.c
1378
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
1381
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic.c
1382
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic.c
1383
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic.c
1399
if (!(crtc_state->connector_mask & drm_connector_mask(connector)))
sys/dev/pci/drm/drm_atomic.c
1725
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
1731
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic.c
1732
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic.c
1733
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic.c
1743
ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);
sys/dev/pci/drm/drm_atomic.c
1747
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic.c
1761
ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
sys/dev/pci/drm/drm_atomic.c
1765
crtc_state->active = true;
sys/dev/pci/drm/drm_atomic.c
1823
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
1840
for_each_new_crtc_in_state(state, crtc, crtc_state, i)
sys/dev/pci/drm/drm_atomic.c
1841
drm_atomic_crtc_print_state(p, crtc_state);
sys/dev/pci/drm/drm_atomic.c
348
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
352
crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic.c
353
if (crtc_state)
sys/dev/pci/drm/drm_atomic.c
354
return crtc_state;
sys/dev/pci/drm/drm_atomic.c
360
crtc_state = crtc->funcs->atomic_duplicate_state(crtc);
sys/dev/pci/drm/drm_atomic.c
361
if (!crtc_state)
sys/dev/pci/drm/drm_atomic.c
364
state->crtcs[index].state = crtc_state;
sys/dev/pci/drm/drm_atomic.c
366
state->crtcs[index].new_state = crtc_state;
sys/dev/pci/drm/drm_atomic.c
368
crtc_state->state = state;
sys/dev/pci/drm/drm_atomic.c
371
crtc->base.id, crtc->name, crtc_state, state);
sys/dev/pci/drm/drm_atomic.c
373
return crtc_state;
sys/dev/pci/drm/drm_atomic.c
464
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
483
crtc_state = drm_atomic_get_existing_crtc_state(state->state,
sys/dev/pci/drm/drm_atomic.c
486
if (writeback_job->fb && !crtc_state->active) {
sys/dev/pci/drm/drm_atomic.c
559
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic.c
561
crtc_state = drm_atomic_get_crtc_state(state,
sys/dev/pci/drm/drm_atomic.c
563
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic.c
564
return ERR_CAST(crtc_state);
sys/dev/pci/drm/drm_atomic_helper.c
102
crtc_state->planes_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
166
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
198
crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
sys/dev/pci/drm/drm_atomic_helper.c
204
if (!crtc_state->connector_mask) {
sys/dev/pci/drm/drm_atomic_helper.c
205
ret = drm_atomic_set_mode_prop_for_crtc(crtc_state,
sys/dev/pci/drm/drm_atomic_helper.c
210
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic_helper.c
2115
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
2122
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_atomic_helper.c
2123
if (drm_atomic_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/drm_atomic_helper.c
224
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
239
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
241
crtc_state->encoder_mask &=
sys/dev/pci/drm/drm_atomic_helper.c
250
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
252
crtc_state->encoder_mask |=
sys/dev/pci/drm/drm_atomic_helper.c
264
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
284
crtc_state = drm_atomic_get_new_crtc_state(state, encoder_crtc);
sys/dev/pci/drm/drm_atomic_helper.c
285
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
300
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3032
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3034
crtc_state = old_plane_state->crtc->state;
sys/dev/pci/drm/drm_atomic_helper.c
3036
if (drm_atomic_crtc_needs_modeset(crtc_state) &&
sys/dev/pci/drm/drm_atomic_helper.c
307
crtc_state = drm_atomic_get_new_crtc_state(state, old_connector_state->crtc);
sys/dev/pci/drm/drm_atomic_helper.c
308
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
312
crtc_state = drm_atomic_get_new_crtc_state(state, new_connector_state->crtc);
sys/dev/pci/drm/drm_atomic_helper.c
313
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
326
crtc_state = drm_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/drm_atomic_helper.c
351
added_by_user && crtc_state->active) {
sys/dev/pci/drm/drm_atomic_helper.c
3554
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3565
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
3566
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_atomic_helper.c
3567
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_helper.c
3571
crtc_state->active = false;
sys/dev/pci/drm/drm_atomic_helper.c
3573
ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, NULL);
sys/dev/pci/drm/drm_atomic_helper.c
3630
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3639
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
3640
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_atomic_helper.c
3641
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_helper.c
3645
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
3729
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3731
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
3732
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_atomic_helper.c
3733
err = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_helper.c
3918
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
3921
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
3922
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic_helper.c
3923
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_helper.c
3925
crtc_state->event = event;
sys/dev/pci/drm/drm_atomic_helper.c
3926
crtc_state->async_flip = flags & DRM_MODE_PAGE_FLIP_ASYNC;
sys/dev/pci/drm/drm_atomic_helper.c
3939
if (!crtc_state->active) {
sys/dev/pci/drm/drm_atomic_helper.c
4018
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
403
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
4031
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
4032
if (WARN_ON(!crtc_state)) {
sys/dev/pci/drm/drm_atomic_helper.c
4036
crtc_state->target_vblank = target;
sys/dev/pci/drm/drm_atomic_helper.c
4067
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_atomic_helper.c
557
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
564
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_helper.c
565
if (!crtc_state)
sys/dev/pci/drm/drm_atomic_helper.c
567
if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
sys/dev/pci/drm/drm_atomic_helper.c
570
mode = &crtc_state->mode;
sys/dev/pci/drm/drm_atomic_helper.c
584
struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/drm_atomic_helper.c
587
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) {
sys/dev/pci/drm/drm_atomic_helper.c
593
if ((crtc_state->encoder_mask & drm_enc->possible_clones) !=
sys/dev/pci/drm/drm_atomic_helper.c
594
crtc_state->encoder_mask) {
sys/dev/pci/drm/drm_atomic_helper.c
596
crtc->base.id, crtc_state->encoder_mask);
sys/dev/pci/drm/drm_atomic_helper.c
84
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_helper.c
87
crtc_state = drm_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/drm_atomic_helper.c
899
const struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_atomic_helper.c
90
if (WARN_ON(!crtc_state))
sys/dev/pci/drm/drm_atomic_helper.c
912
WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);
sys/dev/pci/drm/drm_atomic_helper.c
928
if (!crtc_state->enable && !can_update_disabled) {
sys/dev/pci/drm/drm_atomic_helper.c
93
crtc_state->planes_changed = true;
sys/dev/pci/drm/drm_atomic_helper.c
947
if (crtc_state->enable)
sys/dev/pci/drm/drm_atomic_helper.c
948
drm_mode_get_hv_timing(&crtc_state->mode, &clip.x2, &clip.y2);
sys/dev/pci/drm/drm_atomic_helper.c
97
crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
sys/dev/pci/drm/drm_atomic_helper.c
989
int drm_atomic_helper_check_crtc_primary_plane(struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/drm_atomic_helper.c
99
if (WARN_ON(!crtc_state))
sys/dev/pci/drm/drm_atomic_helper.c
991
struct drm_crtc *crtc = crtc_state->crtc;
sys/dev/pci/drm/drm_atomic_helper.c
996
drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
sys/dev/pci/drm/drm_atomic_state_helper.c
103
crtc->state = crtc_state;
sys/dev/pci/drm/drm_atomic_state_helper.c
116
struct drm_crtc_state *crtc_state =
sys/dev/pci/drm/drm_atomic_state_helper.c
122
__drm_atomic_helper_crtc_reset(crtc, crtc_state);
sys/dev/pci/drm/drm_atomic_state_helper.c
593
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_state_helper.c
600
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_state_helper.c
601
if (!crtc_state)
sys/dev/pci/drm/drm_atomic_state_helper.c
605
crtc_state->mode_changed = true;
sys/dev/pci/drm/drm_atomic_state_helper.c
618
crtc_state->connectors_changed = true;
sys/dev/pci/drm/drm_atomic_state_helper.c
74
__drm_atomic_helper_crtc_state_reset(struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_atomic_state_helper.c
77
crtc_state->crtc = crtc;
sys/dev/pci/drm/drm_atomic_state_helper.c
95
struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/drm_atomic_state_helper.c
97
if (crtc_state)
sys/dev/pci/drm/drm_atomic_state_helper.c
98
__drm_atomic_helper_crtc_state_reset(crtc_state, crtc);
sys/dev/pci/drm/drm_atomic_uapi.c
1050
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
1052
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_uapi.c
1053
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_atomic_uapi.c
1054
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_uapi.c
1059
ret = drm_atomic_crtc_get_property(crtc, crtc_state,
sys/dev/pci/drm/drm_atomic_uapi.c
1066
crtc_state, prop, prop_value);
sys/dev/pci/drm/drm_atomic_uapi.c
1206
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
1214
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_atomic_uapi.c
1217
fence_ptr = get_out_fence_for_crtc(crtc_state->state, crtc);
sys/dev/pci/drm/drm_atomic_uapi.c
1226
crtc_state->event = e;
sys/dev/pci/drm/drm_atomic_uapi.c
1230
struct drm_pending_vblank_event *e = crtc_state->event;
sys/dev/pci/drm/drm_atomic_uapi.c
1239
crtc_state->event = NULL;
sys/dev/pci/drm/drm_atomic_uapi.c
1278
crtc_state->event->base.fence = fence;
sys/dev/pci/drm/drm_atomic_uapi.c
1350
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
1362
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_atomic_uapi.c
1363
struct drm_pending_vblank_event *event = crtc_state->event;
sys/dev/pci/drm/drm_atomic_uapi.c
1371
crtc_state->event = NULL;
sys/dev/pci/drm/drm_atomic_uapi.c
1397
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
1400
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_atomic_uapi.c
1401
crtc_state->async_flip = true;
sys/dev/pci/drm/drm_atomic_uapi.c
194
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
199
crtc_state = drm_atomic_get_crtc_state(plane_state->state,
sys/dev/pci/drm/drm_atomic_uapi.c
201
if (WARN_ON(IS_ERR(crtc_state)))
sys/dev/pci/drm/drm_atomic_uapi.c
202
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_uapi.c
204
crtc_state->plane_mask &= ~drm_plane_mask(plane);
sys/dev/pci/drm/drm_atomic_uapi.c
210
crtc_state = drm_atomic_get_crtc_state(plane_state->state,
sys/dev/pci/drm/drm_atomic_uapi.c
212
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic_uapi.c
213
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_uapi.c
214
crtc_state->plane_mask |= drm_plane_mask(plane);
sys/dev/pci/drm/drm_atomic_uapi.c
280
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
286
crtc_state = drm_atomic_get_new_crtc_state(conn_state->state,
sys/dev/pci/drm/drm_atomic_uapi.c
289
crtc_state->connector_mask &=
sys/dev/pci/drm/drm_atomic_uapi.c
297
crtc_state = drm_atomic_get_crtc_state(conn_state->state, crtc);
sys/dev/pci/drm/drm_atomic_uapi.c
298
if (IS_ERR(crtc_state))
sys/dev/pci/drm/drm_atomic_uapi.c
299
return PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_uapi.c
301
crtc_state->connector_mask |=
sys/dev/pci/drm/drm_atomic_uapi.c
951
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_atomic_uapi.c
975
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_atomic_uapi.c
976
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_atomic_uapi.c
977
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_atomic_uapi.c
990
crtc_state->active = active;
sys/dev/pci/drm/drm_blend.c
449
struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/drm_blend.c
451
struct drm_atomic_state *state = crtc_state->state;
sys/dev/pci/drm/drm_blend.c
470
drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
sys/dev/pci/drm/drm_blend.c
491
crtc_state->zpos_changed = true;
sys/dev/pci/drm/drm_bridge.c
1005
crtc_state,
sys/dev/pci/drm/drm_bridge.c
1023
crtc_state, conn_state,
sys/dev/pci/drm/drm_bridge.c
1075
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_bridge.c
1088
last_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
sys/dev/pci/drm/drm_bridge.c
1103
crtc_state,
sys/dev/pci/drm/drm_bridge.c
1124
ret = select_bus_fmt_recursive(bridge, last_bridge, crtc_state,
sys/dev/pci/drm/drm_bridge.c
1202
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_bridge.c
1213
ret = drm_atomic_bridge_chain_select_bus_fmts(bridge, crtc_state,
sys/dev/pci/drm/drm_bridge.c
1230
crtc_state->state);
sys/dev/pci/drm/drm_bridge.c
1232
ret = drm_atomic_bridge_check(iter, crtc_state, conn_state);
sys/dev/pci/drm/drm_bridge.c
924
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_bridge.c
931
bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state,
sys/dev/pci/drm/drm_bridge.c
937
crtc_state, conn_state);
sys/dev/pci/drm/drm_bridge.c
941
if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode,
sys/dev/pci/drm/drm_bridge.c
942
&crtc_state->adjusted_mode))
sys/dev/pci/drm/drm_bridge.c
951
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/drm_bridge.c
965
cur_state = drm_atomic_get_new_bridge_state(crtc_state->state,
sys/dev/pci/drm/drm_bridge.c
977
prev_bridge, crtc_state,
sys/dev/pci/drm/drm_client_modeset.c
1105
struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/drm_client_modeset.c
1107
crtc_state->active = false;
sys/dev/pci/drm/drm_color_mgmt.c
284
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_color_mgmt.c
325
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_color_mgmt.c
326
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_color_mgmt.c
327
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_color_mgmt.c
332
replaced = drm_property_replace_blob(&crtc_state->degamma_lut,
sys/dev/pci/drm/drm_color_mgmt.c
334
replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);
sys/dev/pci/drm/drm_color_mgmt.c
335
replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,
sys/dev/pci/drm/drm_color_mgmt.c
337
crtc_state->color_mgmt_changed |= replaced;
sys/dev/pci/drm/drm_crtc.c
954
bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state)
sys/dev/pci/drm/drm_crtc.c
956
if (!crtc_state)
sys/dev/pci/drm/drm_crtc.c
959
return hweight32(crtc_state->encoder_mask) > 1;
sys/dev/pci/drm/drm_damage_helper.c
72
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_damage_helper.c
75
crtc_state = drm_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/drm_damage_helper.c
78
if (WARN_ON(!crtc_state))
sys/dev/pci/drm/drm_damage_helper.c
81
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
sys/dev/pci/drm/drm_fb_helper.c
1000
crtc_state->color_mgmt_changed |= replaced;
sys/dev/pci/drm/drm_fb_helper.c
955
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_fb_helper.c
984
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_fb_helper.c
985
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_fb_helper.c
986
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_fb_helper.c
995
replaced = drm_property_replace_blob(&crtc_state->degamma_lut,
sys/dev/pci/drm/drm_fb_helper.c
997
replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);
sys/dev/pci/drm/drm_fb_helper.c
998
replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,
sys/dev/pci/drm/drm_framebuffer.c
1048
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_framebuffer.c
1055
crtc_state = drm_atomic_get_existing_crtc_state(state, plane_state->crtc);
sys/dev/pci/drm/drm_framebuffer.c
1061
crtc_state->active = false;
sys/dev/pci/drm/drm_framebuffer.c
1062
ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL);
sys/dev/pci/drm/drm_plane_helper.c
121
struct drm_crtc_state crtc_state = {
sys/dev/pci/drm/drm_plane_helper.c
128
ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
sys/dev/pci/drm/drm_self_refresh_helper.c
111
crtc_state->active = false;
sys/dev/pci/drm/drm_self_refresh_helper.c
112
crtc_state->self_refresh_active = true;
sys/dev/pci/drm/drm_self_refresh_helper.c
191
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_self_refresh_helper.c
195
for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_self_refresh_helper.c
196
if (crtc_state->self_refresh_active) {
sys/dev/pci/drm/drm_self_refresh_helper.c
204
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/drm_self_refresh_helper.c
209
if (crtc_state->self_refresh_active)
sys/dev/pci/drm/drm_self_refresh_helper.c
79
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/drm_self_refresh_helper.c
93
crtc_state = drm_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/drm_self_refresh_helper.c
94
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/drm_self_refresh_helper.c
95
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/drm_self_refresh_helper.c
99
if (!crtc_state->enable)
sys/dev/pci/drm/i915/display/g4x_dp.c
1033
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
1081
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
1133
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
1228
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
1235
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/g4x_dp.c
1237
ret = intel_dp_compute_config(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/g4x_dp.c
1241
g4x_dp_set_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/g4x_dp.c
321
static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
323
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/g4x_dp.c
325
if (crtc_state->has_pch_encoder) {
sys/dev/pci/drm/i915/display/g4x_dp.c
326
intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/g4x_dp.c
327
intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/g4x_dp.c
329
intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
sys/dev/pci/drm/i915/display/g4x_dp.c
330
&crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/g4x_dp.c
331
intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
sys/dev/pci/drm/i915/display/g4x_dp.c
332
&crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/g4x_dp.c
467
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
473
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/g4x_dp.c
480
intel_audio_codec_enable(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/g4x_dp.c
577
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
605
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
618
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
646
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
658
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
664
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
804
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
810
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
826
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
906
vlv_set_phy_signal_level(encoder, crtc_state,
sys/dev/pci/drm/i915/display/g4x_dp.c
912
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_dp.c
989
chv_set_phy_signal_level(encoder, crtc_state,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
109
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
119
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
121
if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state))
sys/dev/pci/drm/i915/display/g4x_hdmi.c
131
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
135
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
136
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
139
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
142
crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
144
crtc_state->has_hdmi_sink =
sys/dev/pci/drm/i915/display/g4x_hdmi.c
145
intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
147
return intel_hdmi_compute_config(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
233
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/g4x_hdmi.c
239
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
242
drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
247
intel_audio_codec_enable(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
29
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
32
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
34
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
40
if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
47
if (crtc_state->pipe_bpp > 24)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
52
if (crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
624
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/g4x_hdmi.c
643
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/g4x_hdmi.c
644
crtc_state->mode_changed = true;
sys/dev/pci/drm/i915/display/hsw_ips.c
19
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
192
static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
194
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
195
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/hsw_ips.c
204
if (crtc_state->pipe_bpp > 24)
sys/dev/pci/drm/i915/display/hsw_ips.c
21
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
215
crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
sys/dev/pci/drm/i915/display/hsw_ips.c
221
int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
223
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
228
if (!hsw_crtc_state_ips_capable(crtc_state))
sys/dev/pci/drm/i915/display/hsw_ips.c
232
return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
sys/dev/pci/drm/i915/display/hsw_ips.c
239
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/hsw_ips.c
24
if (!crtc_state->ips_enabled)
sys/dev/pci/drm/i915/display/hsw_ips.c
242
crtc_state->ips_enabled = false;
sys/dev/pci/drm/i915/display/hsw_ips.c
244
if (!hsw_crtc_state_ips_capable(crtc_state))
sys/dev/pci/drm/i915/display/hsw_ips.c
253
if (crtc_state->crc_enabled)
sys/dev/pci/drm/i915/display/hsw_ips.c
257
if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
sys/dev/pci/drm/i915/display/hsw_ips.c
268
if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
sys/dev/pci/drm/i915/display/hsw_ips.c
272
crtc_state->ips_enabled = true;
sys/dev/pci/drm/i915/display/hsw_ips.c
277
void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
279
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
280
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/hsw_ips.c
286
crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
sys/dev/pci/drm/i915/display/hsw_ips.c
293
crtc_state->ips_enabled = true;
sys/dev/pci/drm/i915/display/hsw_ips.c
311
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/hsw_ips.c
320
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/hsw_ips.c
322
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/hsw_ips.c
325
if (crtc_state->uapi.commit &&
sys/dev/pci/drm/i915/display/hsw_ips.c
326
!try_wait_for_completion(&crtc_state->uapi.commit->hw_done))
sys/dev/pci/drm/i915/display/hsw_ips.c
329
hsw_ips_enable(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
33
!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
sys/dev/pci/drm/i915/display/hsw_ips.c
65
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.c
67
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.c
70
if (!crtc_state->ips_enabled)
sys/dev/pci/drm/i915/display/hsw_ips.h
16
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.h
22
int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.h
25
void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/hsw_ips.h
28
static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.h
45
static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/hsw_ips.h
54
static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_plane.c
329
i9xx_plane_check(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
339
ret = intel_plane_check_clipping(plane_state, crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
375
static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_plane.c
377
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
378
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/i9xx_plane.c
381
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/i9xx_plane.c
384
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/i9xx_plane.c
393
static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
416
static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
429
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/i9xx_plane.c
431
i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/i9xx_plane.c
434
if (crtc_state->double_wide)
sys/dev/pci/drm/i915/display/i9xx_plane.c
442
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
471
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
480
dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
484
crtc_state->async_flip_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/i9xx_plane.c
526
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
535
i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
536
i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
541
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_plane.c
557
dspcntr = i9xx_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
604
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_plane.c
609
u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_plane.c
622
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1023
static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1026
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1030
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1039
static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1042
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1049
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1058
static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1062
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1065
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1071
if (!intel_wm_plane_visible(crtc_state, plane_state)) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
1072
dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1074
dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1079
struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1082
wm = g4x_compute_wm(crtc_state, plane_state, level);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1095
wm = ilk_compute_fbc_wm(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1111
dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1114
dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1121
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
sys/dev/pci/drm/i915/display/i9xx_wm.c
1122
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
sys/dev/pci/drm/i915/display/i9xx_wm.c
1123
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1128
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1129
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1135
static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1138
const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1143
static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1146
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1151
return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
sys/dev/pci/drm/i915/display/i9xx_wm.c
1152
g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
sys/dev/pci/drm/i915/display/i9xx_wm.c
1153
g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1199
static int _g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1201
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1202
struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1203
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1209
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1212
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1217
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1220
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1228
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1231
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1262
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
1277
if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1284
return _g4x_compute_pipe_wm(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1454
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
1458
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1467
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
1470
if (!crtc_state->wm.need_postvbl_update)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1474
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1510
static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1517
&crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1523
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1527
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1553
static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1555
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1556
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1558
&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1559
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1560
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1665
static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1668
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1672
struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1681
static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1684
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1690
if (!intel_wm_plane_visible(crtc_state, plane_state)) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
1691
dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1696
struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1697
int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1708
dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1715
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
sys/dev/pci/drm/i915/display/i9xx_wm.c
1716
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
sys/dev/pci/drm/i915/display/i9xx_wm.c
1717
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1722
static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
1726
&crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1728
&crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1733
static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1735
return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
sys/dev/pci/drm/i915/display/i9xx_wm.c
1736
vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
sys/dev/pci/drm/i915/display/i9xx_wm.c
1737
vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
sys/dev/pci/drm/i915/display/i9xx_wm.c
1738
vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1741
static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_wm.c
1743
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1744
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1745
struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1747
&crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1748
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1763
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
1766
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1801
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
1816
if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1829
if (intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
1842
&crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1845
ret = vlv_compute_fifo(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1849
if (intel_crtc_needs_modeset(crtc_state) ||
sys/dev/pci/drm/i915/display/i9xx_wm.c
1852
crtc_state->fifo_changed = true;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1855
return _vlv_compute_pipe_wm(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
1867
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
1870
&crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
1874
if (!crtc_state->fifo_changed)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2108
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
2112
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2121
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
2124
if (!crtc_state->wm.need_postvbl_update)
sys/dev/pci/drm/i915/display/i9xx_wm.c
2128
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2447
static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2457
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
2462
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2467
method2 = ilk_wm_method2(crtc_state->pixel_rate,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2468
crtc_state->hw.pipe_mode.crtc_htotal,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2479
static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2489
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
2494
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2495
method2 = ilk_wm_method2(crtc_state->pixel_rate,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2496
crtc_state->hw.pipe_mode.crtc_htotal,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2506
static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2515
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
2520
return ilk_wm_method2(crtc_state->pixel_rate,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2521
crtc_state->hw.pipe_mode.crtc_htotal,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2527
static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2533
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
2712
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2730
result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2732
result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2736
result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2739
result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
sys/dev/pci/drm/i915/display/i9xx_wm.c
283
static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/i9xx_wm.c
285
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
286
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
287
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2926
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
2937
pipe_wm = &crtc_state->wm.ilk.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2939
intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
2948
pipe_wm->pipe_enabled = crtc_state->hw.active;
sys/dev/pci/drm/i915/display/i9xx_wm.c
2949
pipe_wm->sprites_enabled = crtc_state->active_planes & BIT(PLANE_SPRITE0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2950
pipe_wm->sprites_scaled = crtc_state->scaled_planes & BIT(PLANE_SPRITE0);
sys/dev/pci/drm/i915/display/i9xx_wm.c
2963
ilk_compute_wm_level(display, crtc, 0, crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
2974
ilk_compute_wm_level(display, crtc, level, crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3471
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3475
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3484
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3487
if (!crtc_state->wm.need_postvbl_update)
sys/dev/pci/drm/i915/display/i9xx_wm.c
3491
crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3500
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3501
struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3544
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3546
crtc_state = intel_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3547
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
3548
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3550
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
3555
crtc_state->inherited = true;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3585
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3626
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/i9xx_wm.c
3627
crtc_state->wm.need_postvbl_update = true;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3630
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3777
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3805
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3813
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3823
raw = &crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3832
g4x_raw_plane_wm_set(crtc_state, level,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3834
g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3838
crtc_state->wm.g4x.optimal = *active;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3839
crtc_state->wm.g4x.intermediate = *active;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3870
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3882
&crtc_state->wm.g4x.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3892
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3896
ret = _g4x_compute_pipe_wm(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3899
crtc_state->wm.g4x.intermediate =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3900
crtc_state->wm.g4x.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3901
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3959
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
3963
&crtc_state->wm.vlv.fifo_state;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3968
vlv_get_fifo_size(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
3975
&crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
3991
vlv_raw_plane_wm_set(crtc_state, level,
sys/dev/pci/drm/i915/display/i9xx_wm.c
3995
crtc_state->wm.vlv.optimal = *active;
sys/dev/pci/drm/i915/display/i9xx_wm.c
3996
crtc_state->wm.vlv.intermediate = *active;
sys/dev/pci/drm/i915/display/i9xx_wm.c
4022
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
4034
&crtc_state->wm.vlv.raw[level];
sys/dev/pci/drm/i915/display/i9xx_wm.c
4041
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/i9xx_wm.c
4045
ret = _vlv_compute_pipe_wm(crtc_state);
sys/dev/pci/drm/i915/display/i9xx_wm.c
4048
crtc_state->wm.vlv.intermediate =
sys/dev/pci/drm/i915/display/i9xx_wm.c
4049
crtc_state->wm.vlv.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
4050
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
sys/dev/pci/drm/i915/display/i9xx_wm.c
967
static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/i9xx_wm.c
974
&crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/i9xx_wm.c
981
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/i9xx_wm.c
997
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/icl_dsi.c
1059
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1074
divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
sys/dev/pci/drm/i915/display/icl_dsi.c
1133
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1145
gen11_dsi_setup_dphy_timings(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1152
gen11_dsi_setup_timings(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1158
gen11_dsi_setup_timeouts(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1161
gen11_dsi_configure_transcoder(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1201
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/icl_dsi.c
1216
gen11_dsi_program_esc_clk_div(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1279
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/icl_dsi.c
1283
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/icl_dsi.c
1297
intel_backlight_enable(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1300
intel_panel_prepare(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1302
intel_crtc_vblank_on(crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1593
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1599
if (!crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1602
intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/icl_dsi.c
1615
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1618
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/icl_dsi.c
1623
use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
sys/dev/pci/drm/i915/display/icl_dsi.c
1627
if (crtc_state->pipe_bpp < 8 * 3)
sys/dev/pci/drm/i915/display/icl_dsi.c
1631
if (crtc_state->dsc.slice_count > 1)
sys/dev/pci/drm/i915/display/icl_dsi.c
1632
crtc_state->dsc.num_streams = 2;
sys/dev/pci/drm/i915/display/icl_dsi.c
1634
crtc_state->dsc.num_streams = 1;
sys/dev/pci/drm/i915/display/icl_dsi.c
1639
vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/icl_dsi.c
1641
ret = intel_dsc_compute_params(crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
1658
crtc_state->dsc.compression_enable = true;
sys/dev/pci/drm/i915/display/icl_dsi.c
1717
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1769
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
1771
if (crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/icl_dsi.c
1773
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/icl_dsi.c
226
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
228
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
232
mode_flags = crtc_state->mode_flags;
sys/dev/pci/drm/i915/display/icl_dsi.c
346
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
351
if (crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/icl_dsi.c
352
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
sys/dev/pci/drm/i915/display/icl_dsi.c
360
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
369
afe_clk_khz = afe_clk(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.c
548
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
572
if (afe_clk(encoder, crtc_state) <= 800000) {
sys/dev/pci/drm/i915/display/icl_dsi.c
589
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
612
if (afe_clk(encoder, crtc_state) <= 800000) {
sys/dev/pci/drm/i915/display/icl_dsi.c
673
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
677
struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/icl_dsi.c
870
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/icl_dsi.c
875
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/icl_dsi.c
893
if (crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/icl_dsi.c
894
mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
sys/dev/pci/drm/i915/display/icl_dsi.c
917
if (crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/icl_dsi.c
918
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
sys/dev/pci/drm/i915/display/icl_dsi.c
922
byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
sys/dev/pci/drm/i915/display/icl_dsi.h
15
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
119
static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
125
int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_alpm.c
130
return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
sys/dev/pci/drm/i915/display/intel_alpm.c
136
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
143
_lnl_compute_aux_less_wake_time(crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
144
aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_alpm.c
146
silence_period = get_silence_period_symbols(crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
148
lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
168
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
178
intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5);
sys/dev/pci/drm/i915/display/intel_alpm.c
183
if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_alpm.c
209
static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
211
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
220
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
230
io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
sys/dev/pci/drm/i915/display/intel_alpm.c
243
&crtc_state->hw.adjusted_mode, io_wake_time);
sys/dev/pci/drm/i915/display/intel_alpm.c
245
&crtc_state->hw.adjusted_mode, fast_wake_time);
sys/dev/pci/drm/i915/display/intel_alpm.c
251
if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_alpm.c
265
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_alpm.c
269
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_alpm.c
290
if (crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_alpm.c
293
if (crtc_state->vrr.vmin != crtc_state->vrr.vmax ||
sys/dev/pci/drm/i915/display/intel_alpm.c
294
crtc_state->vrr.vmin != crtc_state->vrr.flipline)
sys/dev/pci/drm/i915/display/intel_alpm.c
301
if (!intel_alpm_compute_params(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_alpm.c
313
crtc_state->has_lobf = (context_latency + guardband) >
sys/dev/pci/drm/i915/display/intel_alpm.c
318
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
321
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_alpm.c
324
if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
sys/dev/pci/drm/i915/display/intel_alpm.c
325
!crtc_state->has_lobf))
sys/dev/pci/drm/i915/display/intel_alpm.c
333
if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_alpm.c
358
if (crtc_state->has_lobf) {
sys/dev/pci/drm/i915/display/intel_alpm.c
370
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
372
lnl_alpm_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
373
intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_alpm.c
377
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
38
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
386
if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_alpm.c
40
return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
sys/dev/pci/drm/i915/display/intel_alpm.c
41
(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
sys/dev/pci/drm/i915/display/intel_alpm.c
410
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_alpm.c
414
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_alpm.c
420
if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf)
sys/dev/pci/drm/i915/display/intel_alpm.c
424
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_alpm.c
445
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
449
if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
sys/dev/pci/drm/i915/display/intel_alpm.c
454
if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
sys/dev/pci/drm/i915/display/intel_alpm.c
465
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_alpm.c
471
if (crtc_state->has_psr || !crtc_state->has_lobf ||
sys/dev/pci/drm/i915/display/intel_alpm.c
472
crtc_state->has_lobf == old_crtc_state->has_lobf)
sys/dev/pci/drm/i915/display/intel_alpm.c
476
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_alpm.c
485
intel_alpm_enable_sink(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
486
intel_alpm_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
496
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_alpm.c
511
crtc_state = to_intel_crtc_state(crtc->state);
sys/dev/pci/drm/i915/display/intel_alpm.c
512
cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_alpm.c
55
static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
57
return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
sys/dev/pci/drm/i915/display/intel_alpm.c
61
static int get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_alpm.c
64
if (crtc_state->port_clock < 540000) {
sys/dev/pci/drm/i915/display/intel_alpm.c
67
} else if (crtc_state->port_clock <= 810000) {
sys/dev/pci/drm/i915/display/intel_alpm.c
78
static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
82
ret = get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
sys/dev/pci/drm/i915/display/intel_alpm.c
90
static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_alpm.c
92
int lfps_cycle_time = get_lfps_cycle_time(crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.c
97
return lfps_cycle_time * crtc_state->port_clock / 1000 / 1000 / (2 * LFPS_CYCLE_COUNT);
sys/dev/pci/drm/i915/display/intel_alpm.h
20
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.h
22
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_alpm.h
25
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.h
27
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.h
31
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_alpm.h
38
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.c
125
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_atomic.c
132
crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
sys/dev/pci/drm/i915/display/intel_atomic.c
146
crtc_state->mode_changed = true;
sys/dev/pci/drm/i915/display/intel_atomic.c
202
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_atomic.c
205
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_atomic.c
206
if (intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_atomic.c
240
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_atomic.c
242
crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
sys/dev/pci/drm/i915/display/intel_atomic.c
243
if (!crtc_state)
sys/dev/pci/drm/i915/display/intel_atomic.c
246
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_atomic.c
249
if (crtc_state->hw.degamma_lut)
sys/dev/pci/drm/i915/display/intel_atomic.c
250
drm_property_blob_get(crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
251
if (crtc_state->hw.ctm)
sys/dev/pci/drm/i915/display/intel_atomic.c
252
drm_property_blob_get(crtc_state->hw.ctm);
sys/dev/pci/drm/i915/display/intel_atomic.c
253
if (crtc_state->hw.gamma_lut)
sys/dev/pci/drm/i915/display/intel_atomic.c
254
drm_property_blob_get(crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
256
if (crtc_state->pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_atomic.c
257
drm_property_blob_get(crtc_state->pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
258
if (crtc_state->post_csc_lut)
sys/dev/pci/drm/i915/display/intel_atomic.c
259
drm_property_blob_get(crtc_state->post_csc_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
261
if (crtc_state->dp_tunnel_ref.tunnel)
sys/dev/pci/drm/i915/display/intel_atomic.c
262
drm_dp_tunnel_ref_get(crtc_state->dp_tunnel_ref.tunnel,
sys/dev/pci/drm/i915/display/intel_atomic.c
263
&crtc_state->dp_tunnel_ref);
sys/dev/pci/drm/i915/display/intel_atomic.c
265
crtc_state->update_pipe = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
266
crtc_state->update_m_n = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
267
crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
268
crtc_state->disable_cxsr = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
269
crtc_state->update_wm_pre = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
270
crtc_state->update_wm_post = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
271
crtc_state->fifo_changed = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
272
crtc_state->preload_luts = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
273
crtc_state->wm.need_postvbl_update = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
274
crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
275
crtc_state->fb_bits = 0;
sys/dev/pci/drm/i915/display/intel_atomic.c
276
crtc_state->update_planes = 0;
sys/dev/pci/drm/i915/display/intel_atomic.c
277
crtc_state->dsb_color = NULL;
sys/dev/pci/drm/i915/display/intel_atomic.c
278
crtc_state->dsb_commit = NULL;
sys/dev/pci/drm/i915/display/intel_atomic.c
279
crtc_state->use_dsb = false;
sys/dev/pci/drm/i915/display/intel_atomic.c
281
return &crtc_state->uapi;
sys/dev/pci/drm/i915/display/intel_atomic.c
284
static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_atomic.c
286
drm_property_blob_put(crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
287
drm_property_blob_put(crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
288
drm_property_blob_put(crtc_state->hw.ctm);
sys/dev/pci/drm/i915/display/intel_atomic.c
290
drm_property_blob_put(crtc_state->pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
291
drm_property_blob_put(crtc_state->post_csc_lut);
sys/dev/pci/drm/i915/display/intel_atomic.c
294
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_atomic.c
296
intel_crtc_put_color_blobs(crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.c
311
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
sys/dev/pci/drm/i915/display/intel_atomic.c
313
drm_WARN_ON(crtc->dev, crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_atomic.c
314
drm_WARN_ON(crtc->dev, crtc_state->dsb_commit);
sys/dev/pci/drm/i915/display/intel_atomic.c
316
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_atomic.c
317
intel_crtc_free_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.c
318
if (crtc_state->dp_tunnel_ref.tunnel)
sys/dev/pci/drm/i915/display/intel_atomic.c
319
drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);
sys/dev/pci/drm/i915/display/intel_atomic.c
320
kfree(crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.c
363
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_atomic.c
364
crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
sys/dev/pci/drm/i915/display/intel_atomic.c
365
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_atomic.c
366
return ERR_CAST(crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.c
368
return to_intel_crtc_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_atomic.h
45
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
1001
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_audio.c
1009
if (intel_crtc_has_dp_encoder(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_audio.c
1010
crtc_state->port_clock >= 540000 &&
sys/dev/pci/drm/i915/display/intel_audio.c
1011
crtc_state->lane_count == 4) {
sys/dev/pci/drm/i915/display/intel_audio.c
1036
intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_audio.c
1037
min_cdclk = max(min_cdclk, crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_audio.c
199
static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
201
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
203
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_audio.c
229
static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
235
if (crtc_state->pipe_bpp == 36) {
sys/dev/pci/drm/i915/display/intel_audio.c
238
} else if (crtc_state->pipe_bpp == 30) {
sys/dev/pci/drm/i915/display/intel_audio.c
248
crtc_state->port_clock == hdmi_ncts_table[i].clock) {
sys/dev/pci/drm/i915/display/intel_audio.c
266
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
269
u32 *eld = (u32 *)crtc_state->eld;
sys/dev/pci/drm/i915/display/intel_audio.c
280
len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);
sys/dev/pci/drm/i915/display/intel_audio.c
302
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
306
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_audio.c
307
const u32 *eld = (const u32 *)crtc_state->eld;
sys/dev/pci/drm/i915/display/intel_audio.c
316
len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);
sys/dev/pci/drm/i915/display/intel_audio.c
332
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
335
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
350
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
354
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
365
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
367
n = audio_config_hdmi_get_n(crtc_state, rate);
sys/dev/pci/drm/i915/display/intel_audio.c
392
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
394
if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_audio.c
395
hsw_dp_audio_config_update(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
397
hsw_hdmi_audio_config_update(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
400
static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
403
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
404
enum transcoder trans = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
410
enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);
sys/dev/pci/drm/i915/display/intel_audio.c
452
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
462
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
sys/dev/pci/drm/i915/display/intel_audio.c
463
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
sys/dev/pci/drm/i915/display/intel_audio.c
464
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_audio.c
465
vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
sys/dev/pci/drm/i915/display/intel_audio.c
469
link_clk = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_audio.c
470
lanes = crtc_state->lane_count;
sys/dev/pci/drm/i915/display/intel_audio.c
499
static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
504
h_active = crtc_state->hw.adjusted_mode.hdisplay;
sys/dev/pci/drm/i915/display/intel_audio.c
505
h_total = crtc_state->hw.adjusted_mode.htotal;
sys/dev/pci/drm/i915/display/intel_audio.c
506
pixel_clk = crtc_state->hw.adjusted_mode.clock;
sys/dev/pci/drm/i915/display/intel_audio.c
507
link_clk = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_audio.c
508
lanes = crtc_state->lane_count;
sys/dev/pci/drm/i915/display/intel_audio.c
515
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
518
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
532
if (crtc_state->dsc.compression_enable &&
sys/dev/pci/drm/i915/display/intel_audio.c
533
crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
sys/dev/pci/drm/i915/display/intel_audio.c
534
crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
sys/dev/pci/drm/i915/display/intel_audio.c
537
hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
549
samples_room = calc_samples_room(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
560
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
564
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_audio.c
565
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
570
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
sys/dev/pci/drm/i915/display/intel_audio.c
571
enable_audio_dsc_wa(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
573
intel_audio_sdp_split_update(crtc_state, true);
sys/dev/pci/drm/i915/display/intel_audio.c
594
hsw_audio_config_update(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
662
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
666
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_audio.c
694
(intel_crtc_has_dp_encoder(crtc_state) ?
sys/dev/pci/drm/i915/display/intel_audio.c
696
audio_config_hdmi_pixel_clock(crtc_state)));
sys/dev/pci/drm/i915/display/intel_audio.c
702
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
708
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_audio.c
71
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
719
BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
720
memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
722
crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
sys/dev/pci/drm/i915/display/intel_audio.c
738
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
743
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_audio.c
745
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
749
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_audio.c
757
drm_eld_size(crtc_state->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
761
crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.c
769
BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
77
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
770
memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
777
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
sys/dev/pci/drm/i915/display/intel_audio.c
783
intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,
sys/dev/pci/drm/i915/display/intel_audio.c
784
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_audio.c
785
intel_crtc_has_dp_encoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_audio.c
845
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
848
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_audio.c
856
memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));
sys/dev/pci/drm/i915/display/intel_audio.c
862
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
866
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_audio.c
870
display->funcs.audio->audio_codec_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.c
996
int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_audio.c
998
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.h
18
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.h
21
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_audio.h
27
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_audio.h
30
int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_backlight.c
1634
static void intel_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
1640
panel->backlight.pwm_funcs->enable(crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
1672
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
1684
__intel_backlight_enable(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_backlight.c
485
static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
530
static void pch_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
536
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_backlight.c
580
static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
621
static void i965_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
658
static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
664
enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_backlight.c
690
static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
696
enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_backlight.c
742
static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
773
static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
787
static void __intel_backlight_enable(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
804
panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);
sys/dev/pci/drm/i915/display/intel_backlight.c
810
void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.c
816
enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_backlight.c
825
__intel_backlight_enable(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_backlight.h
23
void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_backlight.h
27
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_bios.c
3496
static void fill_dsc(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_bios.c
3500
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_bios.c
3501
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_bios.c
3517
crtc_state->pipe_bpp = bpc * 3;
sys/dev/pci/drm/i915/display/intel_bios.c
3519
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,
sys/dev/pci/drm/i915/display/intel_bios.c
3529
crtc_state->dsc.slice_count = 4;
sys/dev/pci/drm/i915/display/intel_bios.c
3531
crtc_state->dsc.slice_count = 2;
sys/dev/pci/drm/i915/display/intel_bios.c
3538
crtc_state->dsc.slice_count = 1;
sys/dev/pci/drm/i915/display/intel_bios.c
3541
if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
sys/dev/pci/drm/i915/display/intel_bios.c
3542
crtc_state->dsc.slice_count != 0)
sys/dev/pci/drm/i915/display/intel_bios.c
3545
crtc_state->hw.adjusted_mode.crtc_hdisplay,
sys/dev/pci/drm/i915/display/intel_bios.c
3546
crtc_state->dsc.slice_count);
sys/dev/pci/drm/i915/display/intel_bios.c
3565
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_bios.c
3581
fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
sys/dev/pci/drm/i915/display/intel_bios.h
70
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_bw.c
1324
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_bw.c
1326
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
1327
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_bw.c
1332
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_bw.c
1344
&crtc_state->wm.skl.plane_ddb[plane_id],
sys/dev/pci/drm/i915/display/intel_bw.c
1345
crtc_state->data_rate[plane_id]);
sys/dev/pci/drm/i915/display/intel_bw.c
1349
&crtc_state->wm.skl.plane_ddb_y[plane_id],
sys/dev/pci/drm/i915/display/intel_bw.c
1350
crtc_state->data_rate[plane_id]);
sys/dev/pci/drm/i915/display/intel_bw.c
1654
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_bw.c
1656
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
1657
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_bw.c
1660
intel_bw_crtc_data_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
1662
intel_bw_crtc_num_active_planes(crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
1683
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_bw.c
1687
if (crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_bw.c
1691
intel_bw_crtc_update(bw_state, crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
1693
skl_crtc_calc_dbuf_bw(&bw_state->dbuf_bw[pipe], crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
839
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_bw.c
845
return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
sys/dev/pci/drm/i915/display/intel_bw.c
848
static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_bw.c
850
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_bw.c
851
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_bw.c
863
data_rate += crtc_state->data_rate[plane_id];
sys/dev/pci/drm/i915/display/intel_bw.c
866
data_rate += crtc_state->data_rate_y[plane_id];
sys/dev/pci/drm/i915/display/intel_cdclk.c
2803
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2805
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2806
int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2808
int pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2813
static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2815
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2821
min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2826
static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2830
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2833
min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2834
min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
sys/dev/pci/drm/i915/display/intel_cdclk.c
2835
min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
sys/dev/pci/drm/i915/display/intel_cdclk.c
2836
min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
sys/dev/pci/drm/i915/display/intel_cdclk.c
2837
min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
sys/dev/pci/drm/i915/display/intel_cdclk.c
2838
min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
sys/dev/pci/drm/i915/display/intel_cdclk.c
2850
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2854
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_cdclk.c
2857
min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
sys/dev/pci/drm/i915/display/intel_cdclk.c
2932
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_cdclk.c
2937
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_cdclk.c
2940
if (crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_cdclk.c
2941
min_voltage_level = crtc_state->min_voltage_level;
sys/dev/pci/drm/i915/display/intel_cdclk.c
3028
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_cdclk.c
3035
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_cdclk.c
3036
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_cdclk.c
3039
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_cdclk.c
3046
switch (crtc_state->port_clock / 2) {
sys/dev/pci/drm/i915/display/intel_cdclk.c
3309
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_cdclk.c
3314
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_cdclk.c
3315
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_cdclk.c
3316
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_cdclk.c
3318
if (intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_cdclk.c
3388
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_cdclk.c
3392
if (crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_cdclk.c
3395
cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
sys/dev/pci/drm/i915/display/intel_cdclk.c
3396
cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
sys/dev/pci/drm/i915/display/intel_color.c
1005
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_color.c
1006
ilk_load_csc_matrix(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1010
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1012
ilk_load_csc_matrix(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1016
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1019
i9xx_set_pipeconf(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1023
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1025
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1029
ilk_set_pipeconf(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1032
crtc_state->csc_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1036
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1038
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1042
crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1045
crtc_state->csc_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1062
static void i9xx_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1064
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1065
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1073
crtc_state->gamma_enable = true;
sys/dev/pci/drm/i915/display/intel_color.c
1076
crtc_state->csc_enable = true;
sys/dev/pci/drm/i915/display/intel_color.c
1079
static void hsw_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1081
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1083
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1084
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1086
i9xx_get_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1089
static void skl_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1091
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1092
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1095
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1096
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1101
crtc_state->gamma_enable = true;
sys/dev/pci/drm/i915/display/intel_color.c
1104
crtc_state->csc_enable = true;
sys/dev/pci/drm/i915/display/intel_color.c
1108
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1110
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1111
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1115
if (crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_color.c
1116
ilk_load_csc_matrix(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1123
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_color.c
1125
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
1129
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1131
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1135
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1137
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1138
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1147
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1149
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1152
static void icl_color_post_update(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1154
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1155
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1279
static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1281
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1282
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1284
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1292
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1319
static void i965_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1321
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1322
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1324
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1332
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1337
static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1340
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1342
if (crtc_state->dsb_color)
sys/dev/pci/drm/i915/display/intel_color.c
1343
intel_dsb_reg_write(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1348
static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1351
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1353
if (crtc_state->dsb_color)
sys/dev/pci/drm/i915/display/intel_color.c
1354
intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1359
static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1362
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1390
ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
sys/dev/pci/drm/i915/display/intel_color.c
1392
if (crtc_state->dsb_color)
sys/dev/pci/drm/i915/display/intel_color.c
1393
ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
sys/dev/pci/drm/i915/display/intel_color.c
1398
static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1401
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1407
ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i),
sys/dev/pci/drm/i915/display/intel_color.c
1411
static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1413
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1414
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1417
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1419
ilk_load_lut_8(crtc_state, blob);
sys/dev/pci/drm/i915/display/intel_color.c
1422
ilk_load_lut_10(crtc_state, blob);
sys/dev/pci/drm/i915/display/intel_color.c
1425
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1443
static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1447
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1453
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1455
ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1463
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1468
static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1472
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1477
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1479
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1484
ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1491
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1495
static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1497
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1501
ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1502
ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1503
ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1506
static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1508
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1512
ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1513
ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1514
ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
sys/dev/pci/drm/i915/display/intel_color.c
1517
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1519
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1520
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1523
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1525
ilk_load_lut_8(crtc_state, blob);
sys/dev/pci/drm/i915/display/intel_color.c
1528
ivb_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |
sys/dev/pci/drm/i915/display/intel_color.c
1530
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1531
ivb_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |
sys/dev/pci/drm/i915/display/intel_color.c
1535
ivb_load_lut_10(crtc_state, blob,
sys/dev/pci/drm/i915/display/intel_color.c
1537
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1540
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1545
static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1547
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1548
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1551
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1553
ilk_load_lut_8(crtc_state, blob);
sys/dev/pci/drm/i915/display/intel_color.c
1556
bdw_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |
sys/dev/pci/drm/i915/display/intel_color.c
1558
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1559
bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |
sys/dev/pci/drm/i915/display/intel_color.c
1563
bdw_load_lut_10(crtc_state, blob,
sys/dev/pci/drm/i915/display/intel_color.c
1565
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1568
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1604
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1607
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1608
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1618
ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1620
ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1638
ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1645
ilk_lut_write_indexed(crtc_state, PRE_CSC_GAMC_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1649
ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0);
sys/dev/pci/drm/i915/display/intel_color.c
1652
static void glk_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1654
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1655
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1658
glk_load_degamma_lut(crtc_state, pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_color.c
1660
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
1662
ilk_load_lut_8(crtc_state, post_csc_lut);
sys/dev/pci/drm/i915/display/intel_color.c
1665
bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
sys/dev/pci/drm/i915/display/intel_color.c
1666
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1667
glk_load_lut_ext2_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1670
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1676
ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
1679
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1683
ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
sys/dev/pci/drm/i915/display/intel_color.c
1684
ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
sys/dev/pci/drm/i915/display/intel_color.c
1685
ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
sys/dev/pci/drm/i915/display/intel_color.c
1689
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1691
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1692
const struct drm_property_blob *blob = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1704
ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1706
ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1713
ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1715
ilk_lut_write_indexed(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1719
ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1724
icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1726
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1727
const struct drm_property_blob *blob = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1743
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1745
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1752
ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1754
ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1773
ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1775
ilk_lut_write_indexed(crtc_state, PREC_PAL_DATA(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1779
ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
sys/dev/pci/drm/i915/display/intel_color.c
1784
ivb_load_lut_max(crtc_state, entry);
sys/dev/pci/drm/i915/display/intel_color.c
1787
static void icl_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1789
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1790
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1793
glk_load_degamma_lut(crtc_state, pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_color.c
1795
switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_color.c
1797
ilk_load_lut_8(crtc_state, post_csc_lut);
sys/dev/pci/drm/i915/display/intel_color.c
1800
icl_program_gamma_superfine_segment(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1801
icl_program_gamma_multi_segment(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1802
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1803
glk_load_lut_ext2_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1806
bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
sys/dev/pci/drm/i915/display/intel_color.c
1807
ivb_load_lut_ext_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1808
glk_load_lut_ext2_max(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1811
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1816
static void vlv_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1818
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1820
if (crtc_state->wgc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
1821
vlv_load_wgc_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
1823
i965_load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1894
static void chv_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1896
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1897
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1898
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1899
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
1901
if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
sys/dev/pci/drm/i915/display/intel_color.c
1902
chv_load_cgm_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
1904
if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
1907
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
1910
i965_load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1913
crtc_state->cgm_mode);
sys/dev/pci/drm/i915/display/intel_color.c
1916
void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1918
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1920
if (crtc_state->dsb_color)
sys/dev/pci/drm/i915/display/intel_color.c
1923
display->funcs.color->load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1927
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1929
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1932
display->funcs.color->color_commit_noarm(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1936
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1938
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1940
display->funcs.color->color_commit_arm(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1943
void intel_color_post_update(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1945
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1948
display->funcs.color->color_post_update(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1951
void intel_color_modeset(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1953
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1955
intel_color_load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1956
intel_color_commit_noarm(NULL, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1957
intel_color_commit_arm(NULL, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1960
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
1964
plane->disable_arm(NULL, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1968
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1970
return crtc_state->dsb_color;
sys/dev/pci/drm/i915/display/intel_color.c
1973
bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1975
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1977
return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display);
sys/dev/pci/drm/i915/display/intel_color.c
1980
bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
1982
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
1984
return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display);
sys/dev/pci/drm/i915/display/intel_color.c
1991
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
1994
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_color.c
1995
intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
1998
if (!intel_crtc_needs_color_update(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
2001
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2005
crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
sys/dev/pci/drm/i915/display/intel_color.c
2007
crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
sys/dev/pci/drm/i915/display/intel_color.c
2009
if (!intel_color_uses_dsb(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
2012
display->funcs.color->load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2014
if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_color.c
2015
intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2016
intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2017
intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2018
intel_dsb_interrupt(crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2021
if (intel_color_uses_gosub_dsb(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
2022
intel_dsb_gosub_finish(crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2024
intel_dsb_finish(crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2027
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2029
if (crtc_state->dsb_color) {
sys/dev/pci/drm/i915/display/intel_color.c
2030
intel_dsb_cleanup(crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2031
crtc_state->dsb_color = NULL;
sys/dev/pci/drm/i915/display/intel_color.c
2035
void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2037
if (crtc_state->dsb_color)
sys/dev/pci/drm/i915/display/intel_color.c
2038
intel_dsb_wait(crtc_state->dsb_color);
sys/dev/pci/drm/i915/display/intel_color.c
2106
void intel_color_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2108
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2110
display->funcs.color->get_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2112
display->funcs.color->read_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2115
display->funcs.color->read_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2118
bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
2123
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2129
if (!is_pre_csc_lut && crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
2132
return display->funcs.color->lut_equal(crtc_state, blob1, blob2,
sys/dev/pci/drm/i915/display/intel_color.c
2137
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2146
return crtc_state->active_planes & BIT(plane->id) ||
sys/dev/pci/drm/i915/display/intel_color.c
2191
static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2193
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2194
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
sys/dev/pci/drm/i915/display/intel_color.c
2202
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2204
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2209
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2211
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2212
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
sys/dev/pci/drm/i915/display/intel_color.c
2220
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2222
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2247
static int _check_luts(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
2250
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2251
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2252
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
sys/dev/pci/drm/i915/display/intel_color.c
2253
const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
sys/dev/pci/drm/i915/display/intel_color.c
2257
if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) {
sys/dev/pci/drm/i915/display/intel_color.c
2264
degamma_length = intel_degamma_lut_size(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2265
gamma_length = intel_gamma_lut_size(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2278
static int check_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2280
return _check_luts(crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
2281
intel_degamma_lut_tests(crtc_state),
sys/dev/pci/drm/i915/display/intel_color.c
2282
intel_gamma_lut_tests(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
2285
static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2287
if (!crtc_state->gamma_enable ||
sys/dev/pci/drm/i915/display/intel_color.c
2288
lut_is_legacy(crtc_state->hw.gamma_lut))
sys/dev/pci/drm/i915/display/intel_color.c
2321
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2323
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2328
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2330
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2333
crtc_state->post_csc_lut == crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2334
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2335
crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2337
!ilk_lut_limited_range(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_color.c
2338
crtc_state->post_csc_lut != NULL &&
sys/dev/pci/drm/i915/display/intel_color.c
2339
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2340
} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
sys/dev/pci/drm/i915/display/intel_color.c
2342
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2343
crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2345
!ilk_lut_limited_range(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_color.c
2346
crtc_state->post_csc_lut != crtc_state->hw.degamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2347
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2351
static void intel_assign_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2353
drm_property_replace_blob(&crtc_state->pre_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2354
crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2355
drm_property_replace_blob(&crtc_state->post_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2356
crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2363
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2367
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2371
crtc_state->gamma_enable =
sys/dev/pci/drm/i915/display/intel_color.c
2372
crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2373
!crtc_state->c8_planes;
sys/dev/pci/drm/i915/display/intel_color.c
2375
crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2378
crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) {
sys/dev/pci/drm/i915/display/intel_color.c
2379
ret = i9xx_check_lut_10(crtc, crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2388
intel_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2390
crtc_state->preload_luts = intel_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2402
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2406
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2410
crtc_state->gamma_enable =
sys/dev/pci/drm/i915/display/intel_color.c
2411
crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2412
!crtc_state->c8_planes;
sys/dev/pci/drm/i915/display/intel_color.c
2414
crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2416
crtc_state->wgc_enable = crtc_state->hw.ctm;
sys/dev/pci/drm/i915/display/intel_color.c
2422
intel_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2424
vlv_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2426
crtc_state->preload_luts = vlv_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2431
static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2435
if (crtc_state->hw.degamma_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2437
if (crtc_state->hw.ctm)
sys/dev/pci/drm/i915/display/intel_color.c
2439
if (crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2440
!lut_is_legacy(crtc_state->hw.gamma_lut))
sys/dev/pci/drm/i915/display/intel_color.c
2464
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2468
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2476
crtc_state->gamma_enable =
sys/dev/pci/drm/i915/display/intel_color.c
2477
lut_is_legacy(crtc_state->hw.gamma_lut) &&
sys/dev/pci/drm/i915/display/intel_color.c
2478
!crtc_state->c8_planes;
sys/dev/pci/drm/i915/display/intel_color.c
2480
crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
sys/dev/pci/drm/i915/display/intel_color.c
2482
crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2488
crtc_state->wgc_enable = false;
sys/dev/pci/drm/i915/display/intel_color.c
2494
intel_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2496
chv_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2498
crtc_state->preload_luts = chv_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2503
static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2505
return (crtc_state->hw.gamma_lut ||
sys/dev/pci/drm/i915/display/intel_color.c
2506
crtc_state->hw.degamma_lut) &&
sys/dev/pci/drm/i915/display/intel_color.c
2507
!crtc_state->c8_planes;
sys/dev/pci/drm/i915/display/intel_color.c
2510
static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2512
return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
sys/dev/pci/drm/i915/display/intel_color.c
2513
ilk_csc_limited_range(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_color.c
2514
crtc_state->hw.ctm;
sys/dev/pci/drm/i915/display/intel_color.c
2517
static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2519
if (!crtc_state->gamma_enable ||
sys/dev/pci/drm/i915/display/intel_color.c
2520
lut_is_legacy(crtc_state->hw.gamma_lut))
sys/dev/pci/drm/i915/display/intel_color.c
2526
static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2534
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_color.c
2537
if (crtc_state->hw.degamma_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2544
static int ilk_assign_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2546
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2548
if (ilk_lut_limited_range(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_color.c
2551
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2552
drm_color_lut_size(crtc_state->hw.gamma_lut),
sys/dev/pci/drm/i915/display/intel_color.c
2557
drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2561
drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2566
if (crtc_state->hw.degamma_lut ||
sys/dev/pci/drm/i915/display/intel_color.c
2567
crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) {
sys/dev/pci/drm/i915/display/intel_color.c
2568
drm_property_replace_blob(&crtc_state->pre_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2569
crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2570
drm_property_replace_blob(&crtc_state->post_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2571
crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2573
drm_property_replace_blob(&crtc_state->pre_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2574
crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2575
drm_property_replace_blob(&crtc_state->post_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2586
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2590
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2594
if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
sys/dev/pci/drm/i915/display/intel_color.c
2601
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
sys/dev/pci/drm/i915/display/intel_color.c
2602
crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
2609
crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2611
crtc_state->csc_enable = ilk_csc_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2613
crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2615
crtc_state->csc_mode = ilk_csc_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2621
ret = ilk_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2625
ilk_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2627
crtc_state->preload_luts = intel_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2632
static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2634
if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2637
return ilk_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2640
static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2642
bool limited_color_range = ilk_csc_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2648
if (crtc_state->hw.degamma_lut ||
sys/dev/pci/drm/i915/display/intel_color.c
2649
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
sys/dev/pci/drm/i915/display/intel_color.c
2656
static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2658
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2661
if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT)
sys/dev/pci/drm/i915/display/intel_color.c
2662
return ilk_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2664
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
sys/dev/pci/drm/i915/display/intel_color.c
2665
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
sys/dev/pci/drm/i915/display/intel_color.c
2667
degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,
sys/dev/pci/drm/i915/display/intel_color.c
2672
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,
sys/dev/pci/drm/i915/display/intel_color.c
2673
ilk_lut_limited_range(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
2679
drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2680
drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2692
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2696
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2700
if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) {
sys/dev/pci/drm/i915/display/intel_color.c
2707
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
sys/dev/pci/drm/i915/display/intel_color.c
2708
crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
2715
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
sys/dev/pci/drm/i915/display/intel_color.c
2716
crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
sys/dev/pci/drm/i915/display/intel_color.c
2723
crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2725
crtc_state->csc_enable = ilk_csc_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2727
crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2729
crtc_state->csc_mode = ivb_csc_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2735
ret = ivb_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2739
ilk_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2741
crtc_state->preload_luts = intel_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2746
static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2748
if (!crtc_state->gamma_enable ||
sys/dev/pci/drm/i915/display/intel_color.c
2749
lut_is_legacy(crtc_state->hw.gamma_lut))
sys/dev/pci/drm/i915/display/intel_color.c
2755
static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2757
return crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2758
!crtc_state->c8_planes &&
sys/dev/pci/drm/i915/display/intel_color.c
2759
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_color.c
2762
static int glk_assign_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2764
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2766
if (glk_use_pre_csc_lut_for_gamma(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_color.c
2769
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2775
drm_property_replace_blob(&crtc_state->pre_csc_lut, gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2776
drm_property_replace_blob(&crtc_state->post_csc_lut, NULL);
sys/dev/pci/drm/i915/display/intel_color.c
2783
if (ilk_lut_limited_range(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_color.c
2786
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2787
drm_color_lut_size(crtc_state->hw.gamma_lut),
sys/dev/pci/drm/i915/display/intel_color.c
2792
drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2796
drm_property_replace_blob(&crtc_state->post_csc_lut, crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2799
drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_color.c
2807
if (crtc_state->csc_enable && !crtc_state->pre_csc_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2808
drm_property_replace_blob(&crtc_state->pre_csc_lut,
sys/dev/pci/drm/i915/display/intel_color.c
2814
static int glk_check_luts(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2816
u32 degamma_tests = intel_degamma_lut_tests(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2817
u32 gamma_tests = intel_gamma_lut_tests(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2819
if (glk_use_pre_csc_lut_for_gamma(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
2822
return _check_luts(crtc_state, degamma_tests, gamma_tests);
sys/dev/pci/drm/i915/display/intel_color.c
2829
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
2833
ret = glk_check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2837
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
sys/dev/pci/drm/i915/display/intel_color.c
2838
crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
2845
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
sys/dev/pci/drm/i915/display/intel_color.c
2846
crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
sys/dev/pci/drm/i915/display/intel_color.c
2853
crtc_state->gamma_enable =
sys/dev/pci/drm/i915/display/intel_color.c
2854
!glk_use_pre_csc_lut_for_gamma(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_color.c
2855
crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2856
!crtc_state->c8_planes;
sys/dev/pci/drm/i915/display/intel_color.c
2859
crtc_state->csc_enable =
sys/dev/pci/drm/i915/display/intel_color.c
2860
glk_use_pre_csc_lut_for_gamma(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_color.c
2861
crtc_state->hw.degamma_lut ||
sys/dev/pci/drm/i915/display/intel_color.c
2862
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
sys/dev/pci/drm/i915/display/intel_color.c
2863
crtc_state->hw.ctm || ilk_csc_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2865
crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2867
crtc_state->csc_mode = 0;
sys/dev/pci/drm/i915/display/intel_color.c
2873
ret = glk_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2877
ilk_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2879
crtc_state->preload_luts = intel_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2884
static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2886
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2889
if (crtc_state->hw.degamma_lut)
sys/dev/pci/drm/i915/display/intel_color.c
2892
if (crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
2893
!crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
2896
if (!crtc_state->hw.gamma_lut ||
sys/dev/pci/drm/i915/display/intel_color.c
2897
lut_is_legacy(crtc_state->hw.gamma_lut))
sys/dev/pci/drm/i915/display/intel_color.c
291
static void ilk_read_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2912
static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2916
if (crtc_state->hw.ctm)
sys/dev/pci/drm/i915/display/intel_color.c
2919
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
sys/dev/pci/drm/i915/display/intel_color.c
2920
crtc_state->limited_color_range)
sys/dev/pci/drm/i915/display/intel_color.c
2929
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_color.c
293
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
2933
ret = check_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2937
crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2939
crtc_state->csc_mode = icl_csc_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2941
intel_assign_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2943
icl_assign_csc(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
2945
crtc_state->preload_luts = intel_can_preload_luts(state, crtc);
sys/dev/pci/drm/i915/display/intel_color.c
295
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
2950
static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2952
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
2955
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
296
ilk_read_pipe_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
2961
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
2966
static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2971
static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
2973
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
2976
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
2982
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
299
static void skl_read_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3000
static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3002
if (crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3005
return crtc_state->gamma_enable &&
sys/dev/pci/drm/i915/display/intel_color.c
3006
(crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0;
sys/dev/pci/drm/i915/display/intel_color.c
3009
static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
301
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3011
return crtc_state->gamma_enable &&
sys/dev/pci/drm/i915/display/intel_color.c
3012
(crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0;
sys/dev/pci/drm/i915/display/intel_color.c
3015
static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3017
if (!ilk_has_post_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
3020
return ilk_gamma_mode_precision(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3023
static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3025
if (!ilk_has_pre_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
3028
return ilk_gamma_mode_precision(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3031
static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3033
if (crtc_state->gamma_enable &&
sys/dev/pci/drm/i915/display/intel_color.c
3034
crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
sys/dev/pci/drm/i915/display/intel_color.c
3037
return ilk_post_csc_lut_precision(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3040
static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3042
if (crtc_state->gamma_enable &&
sys/dev/pci/drm/i915/display/intel_color.c
3043
crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
sys/dev/pci/drm/i915/display/intel_color.c
3046
return ilk_pre_csc_lut_precision(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3049
static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3051
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
3054
return i965_post_csc_lut_precision(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3057
static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3059
if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
3065
static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3067
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3070
return ilk_gamma_mode_precision(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3073
static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3075
if (!crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
3081
static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3083
if (crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3086
return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE;
sys/dev/pci/drm/i915/display/intel_color.c
3089
static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3091
return crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE;
sys/dev/pci/drm/i915/display/intel_color.c
3094
static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3096
if (!icl_has_post_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
3099
switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_color.c
3107
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3112
static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3114
if (!icl_has_pre_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
316
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
317
ilk_read_pipe_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
3179
static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3188
i9xx_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3191
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT)
sys/dev/pci/drm/i915/display/intel_color.c
3195
i9xx_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3198
static bool i965_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3205
i9xx_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3208
i965_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3211
static bool chv_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3218
chv_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3221
chv_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3224
static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3231
ilk_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3234
ilk_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3237
static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3244
ivb_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3247
ivb_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3250
static bool glk_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3257
glk_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3260
glk_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3263
static bool icl_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
3272
icl_pre_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3275
if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
sys/dev/pci/drm/i915/display/intel_color.c
3280
icl_post_csc_lut_precision(crtc_state));
sys/dev/pci/drm/i915/display/intel_color.c
3340
static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3342
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3344
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3347
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3349
crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3352
crtc_state->post_csc_lut = i9xx_read_lut_10(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3355
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3392
static void i965_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3394
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3396
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3399
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3401
crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3404
crtc_state->post_csc_lut = i965_read_lut_10p6(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3407
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3464
static void chv_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3466
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3467
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3469
crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));
sys/dev/pci/drm/i915/display/intel_color.c
3471
i9xx_get_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3474
static void chv_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3476
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3478
if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
3479
crtc_state->pre_csc_lut = chv_read_cgm_degamma(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3481
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
sys/dev/pci/drm/i915/display/intel_color.c
3482
crtc_state->post_csc_lut = chv_read_cgm_gamma(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3484
i965_read_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3537
static void ilk_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3539
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3541
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3543
i9xx_get_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
3546
static void ilk_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3548
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3550
ilk_has_post_csc_lut(crtc_state) ?
sys/dev/pci/drm/i915/display/intel_color.c
3551
&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
3553
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3556
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3564
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3607
static void ivb_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3609
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3611
ilk_has_post_csc_lut(crtc_state) ?
sys/dev/pci/drm/i915/display/intel_color.c
3612
&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
3614
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3617
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3622
crtc_state->pre_csc_lut =
sys/dev/pci/drm/i915/display/intel_color.c
3625
crtc_state->post_csc_lut =
sys/dev/pci/drm/i915/display/intel_color.c
3633
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3674
static void bdw_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3676
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3678
ilk_has_post_csc_lut(crtc_state) ?
sys/dev/pci/drm/i915/display/intel_color.c
3679
&crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
sys/dev/pci/drm/i915/display/intel_color.c
3681
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3684
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3689
crtc_state->pre_csc_lut =
sys/dev/pci/drm/i915/display/intel_color.c
3692
crtc_state->post_csc_lut =
sys/dev/pci/drm/i915/display/intel_color.c
3700
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3747
static void glk_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3749
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3751
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
3752
crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3754
if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
3757
switch (crtc_state->gamma_mode) {
sys/dev/pci/drm/i915/display/intel_color.c
3759
crtc_state->post_csc_lut = ilk_read_lut_8(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3762
crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
sys/dev/pci/drm/i915/display/intel_color.c
3765
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
3812
static void icl_read_luts(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
3814
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3816
if (icl_has_pre_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
3817
crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3819
if (!icl_has_post_csc_lut(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
3822
switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
sys/dev/pci/drm/i915/display/intel_color.c
3824
crtc_state->post_csc_lut = ilk_read_lut_8(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3827
crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
sys/dev/pci/drm/i915/display/intel_color.c
3830
crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc);
sys/dev/pci/drm/i915/display/intel_color.c
3833
MISSING_CASE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_color.c
391
static void icl_read_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
393
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
400
if (crtc_state->csc_mode & ICL_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
401
ilk_read_pipe_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
403
if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
404
icl_read_output_csc(crtc, &crtc_state->output_csc);
sys/dev/pci/drm/i915/display/intel_color.c
407
static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
409
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
419
return crtc_state->limited_color_range;
sys/dev/pci/drm/i915/display/intel_color.c
422
static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
424
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
426
if (!ilk_limited_range(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
429
if (crtc_state->c8_planes)
sys/dev/pci/drm/i915/display/intel_color.c
433
return crtc_state->hw.gamma_lut;
sys/dev/pci/drm/i915/display/intel_color.c
435
return crtc_state->hw.gamma_lut &&
sys/dev/pci/drm/i915/display/intel_color.c
436
(crtc_state->hw.degamma_lut || crtc_state->hw.ctm);
sys/dev/pci/drm/i915/display/intel_color.c
439
static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
441
if (!ilk_limited_range(crtc_state))
sys/dev/pci/drm/i915/display/intel_color.c
444
return !ilk_lut_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
457
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
461
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
462
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
sys/dev/pci/drm/i915/display/intel_color.c
47
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
517
static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
519
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
520
bool limited_color_range = ilk_csc_limited_range(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
522
if (crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
523
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
525
ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, limited_color_range);
sys/dev/pci/drm/i915/display/intel_color.c
526
} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
sys/dev/pci/drm/i915/display/intel_color.c
527
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
529
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);
sys/dev/pci/drm/i915/display/intel_color.c
531
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
533
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);
sys/dev/pci/drm/i915/display/intel_color.c
534
} else if (crtc_state->csc_enable) {
sys/dev/pci/drm/i915/display/intel_color.c
543
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);
sys/dev/pci/drm/i915/display/intel_color.c
545
intel_csc_clear(&crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
550
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
552
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
554
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
555
ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
558
static void icl_assign_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
56
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
560
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
562
if (crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
563
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);
sys/dev/pci/drm/i915/display/intel_color.c
565
ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, false);
sys/dev/pci/drm/i915/display/intel_color.c
567
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);
sys/dev/pci/drm/i915/display/intel_color.c
569
intel_csc_clear(&crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
572
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
sys/dev/pci/drm/i915/display/intel_color.c
573
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
sys/dev/pci/drm/i915/display/intel_color.c
575
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);
sys/dev/pci/drm/i915/display/intel_color.c
576
} else if (crtc_state->limited_color_range) {
sys/dev/pci/drm/i915/display/intel_color.c
577
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
sys/dev/pci/drm/i915/display/intel_color.c
579
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);
sys/dev/pci/drm/i915/display/intel_color.c
581
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);
sys/dev/pci/drm/i915/display/intel_color.c
583
intel_csc_clear(&crtc_state->output_csc);
sys/dev/pci/drm/i915/display/intel_color.c
588
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
590
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
592
if (crtc_state->csc_mode & ICL_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
593
ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
595
if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
sys/dev/pci/drm/i915/display/intel_color.c
596
icl_update_output_csc(dsb, crtc, &crtc_state->output_csc);
sys/dev/pci/drm/i915/display/intel_color.c
61
void (*color_post_update)(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
626
static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
629
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
sys/dev/pci/drm/i915/display/intel_color.c
68
void (*load_luts)(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
687
static void vlv_read_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
689
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
691
if (crtc_state->wgc_enable)
sys/dev/pci/drm/i915/display/intel_color.c
692
vlv_read_wgc_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
695
static void vlv_assign_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
697
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
699
if (crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
700
drm_WARN_ON(display->drm, !crtc_state->wgc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
702
vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
704
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
706
intel_csc_clear(&crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
718
static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
721
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
sys/dev/pci/drm/i915/display/intel_color.c
73
void (*read_luts)(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
77
bool (*lut_equal)(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.c
783
static void chv_read_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
785
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_color.c
787
if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
sys/dev/pci/drm/i915/display/intel_color.c
788
chv_read_cgm_csc(crtc, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
791
static void chv_assign_csc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
793
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
795
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
sys/dev/pci/drm/i915/display/intel_color.c
797
if (crtc_state->hw.ctm) {
sys/dev/pci/drm/i915/display/intel_color.c
798
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
sys/dev/pci/drm/i915/display/intel_color.c
800
chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
sys/dev/pci/drm/i915/display/intel_color.c
802
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
sys/dev/pci/drm/i915/display/intel_color.c
804
crtc_state->csc = chv_cgm_csc_matrix_identity;
sys/dev/pci/drm/i915/display/intel_color.c
85
void (*read_csc)(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
89
void (*get_config)(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
979
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.c
989
icl_load_csc_matrix(dsb, crtc_state);
sys/dev/pci/drm/i915/display/intel_color.c
993
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_color.h
25
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
26
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
27
bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
28
bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
29
void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
31
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
33
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
34
void intel_color_post_update(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
35
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
36
void intel_color_modeset(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
37
void intel_color_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_color.h
38
bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_color.h
42
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
149
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crt.c
151
crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
sys/dev/pci/drm/i915/display/intel_crt.c
153
crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
sys/dev/pci/drm/i915/display/intel_crt.c
155
crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_crt.c
159
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crt.c
161
lpt_pch_get_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
163
hsw_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
165
crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
sys/dev/pci/drm/i915/display/intel_crt.c
169
crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
sys/dev/pci/drm/i915/display/intel_crt.c
175
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
180
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crt.c
181
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_crt.c
289
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
294
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
sys/dev/pci/drm/i915/display/intel_crt.c
301
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
305
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crt.c
308
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
sys/dev/pci/drm/i915/display/intel_crt.c
312
hsw_fdi_link_train(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
314
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
319
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
323
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crt.c
326
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
sys/dev/pci/drm/i915/display/intel_crt.c
328
intel_ddi_enable_transcoder_func(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
330
intel_enable_transcoder(crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
334
intel_crtc_vblank_on(crtc_state);
sys/dev/pci/drm/i915/display/intel_crt.c
336
intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
sys/dev/pci/drm/i915/display/intel_crt.c
346
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
349
intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
sys/dev/pci/drm/i915/display/intel_crt.c
399
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
403
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_crt.c
408
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_crt.c
409
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_crt.c
415
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
419
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_crt.c
424
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/intel_crt.c
425
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
sys/dev/pci/drm/i915/display/intel_crt.c
428
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_crt.c
434
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crt.c
439
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_crt.c
449
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/intel_crt.c
450
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
sys/dev/pci/drm/i915/display/intel_crt.c
453
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_crt.c
458
if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) {
sys/dev/pci/drm/i915/display/intel_crt.c
464
crtc_state->pipe_bpp = 24;
sys/dev/pci/drm/i915/display/intel_crt.c
468
crtc_state->port_clock = 135000 * 2;
sys/dev/pci/drm/i915/display/intel_crt.c
470
crtc_state->enhanced_framing = true;
sys/dev/pci/drm/i915/display/intel_crt.c
472
adjusted_mode->crtc_clock = lpt_iclkip(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.c
103
if (crtc_state->mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 |
sys/dev/pci/drm/i915/display/intel_crtc.c
112
(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
sys/dev/pci/drm/i915/display/intel_crtc.c
123
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
125
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
127
crtc->vblank_psr_notify = intel_psr_needs_vblank_notification(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.c
131
intel_crtc_max_vblank_count(crtc_state));
sys/dev/pci/drm/i915/display/intel_crtc.c
142
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
144
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.c
145
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
164
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_crtc.c
166
crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
sys/dev/pci/drm/i915/display/intel_crtc.c
168
if (crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
169
intel_crtc_state_reset(crtc_state, crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
171
return crtc_state;
sys/dev/pci/drm/i915/display/intel_crtc.c
174
void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crtc.c
177
memset(crtc_state, 0, sizeof(*crtc_state));
sys/dev/pci/drm/i915/display/intel_crtc.c
179
__drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
sys/dev/pci/drm/i915/display/intel_crtc.c
181
crtc_state->cpu_transcoder = INVALID_TRANSCODER;
sys/dev/pci/drm/i915/display/intel_crtc.c
182
crtc_state->master_transcoder = INVALID_TRANSCODER;
sys/dev/pci/drm/i915/display/intel_crtc.c
183
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
sys/dev/pci/drm/i915/display/intel_crtc.c
184
crtc_state->scaler_state.scaler_id = -1;
sys/dev/pci/drm/i915/display/intel_crtc.c
185
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
sys/dev/pci/drm/i915/display/intel_crtc.c
186
crtc_state->max_link_bpp_x16 = INT_MAX;
sys/dev/pci/drm/i915/display/intel_crtc.c
191
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_crtc.c
198
crtc_state = intel_crtc_state_alloc(crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
199
if (!crtc_state) {
sys/dev/pci/drm/i915/display/intel_crtc.c
204
crtc->base.state = &crtc_state->uapi;
sys/dev/pci/drm/i915/display/intel_crtc.c
205
crtc->config = crtc_state;
sys/dev/pci/drm/i915/display/intel_crtc.c
418
static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
420
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.c
422
return crtc_state->hw.active &&
sys/dev/pci/drm/i915/display/intel_crtc.c
423
!crtc_state->preload_luts &&
sys/dev/pci/drm/i915/display/intel_crtc.c
424
!intel_crtc_needs_modeset(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_crtc.c
425
(intel_crtc_needs_color_update(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_crtc.c
427
!intel_color_uses_dsb(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_crtc.c
428
!crtc_state->use_dsb;
sys/dev/pci/drm/i915/display/intel_crtc.c
434
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_crtc.c
435
container_of(work, typeof(*crtc_state), vblank_work);
sys/dev/pci/drm/i915/display/intel_crtc.c
436
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
440
intel_color_load_luts(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.c
442
if (crtc_state->uapi.event) {
sys/dev/pci/drm/i915/display/intel_crtc.c
444
drm_crtc_send_vblank_event(&crtc->base, crtc_state->uapi.event);
sys/dev/pci/drm/i915/display/intel_crtc.c
446
crtc_state->uapi.event = NULL;
sys/dev/pci/drm/i915/display/intel_crtc.c
452
static void intel_crtc_vblank_work_init(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
454
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
456
drm_vblank_work_init(&crtc_state->vblank_work, &crtc->base,
sys/dev/pci/drm/i915/display/intel_crtc.c
467
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_crtc.c
471
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_crtc.c
472
if (!intel_crtc_needs_vblank_work(crtc_state))
sys/dev/pci/drm/i915/display/intel_crtc.c
475
drm_vblank_work_flush(&crtc_state->vblank_work);
sys/dev/pci/drm/i915/display/intel_crtc.c
616
void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
618
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
621
if (!crtc_state->uapi.event)
sys/dev/pci/drm/i915/display/intel_crtc.c
627
drm_crtc_arm_vblank_event(&crtc->base, crtc_state->uapi.event);
sys/dev/pci/drm/i915/display/intel_crtc.c
630
crtc_state->uapi.event = NULL;
sys/dev/pci/drm/i915/display/intel_crtc.c
633
void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crtc.c
636
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_crtc.c
640
*event = crtc_state->uapi.event;
sys/dev/pci/drm/i915/display/intel_crtc.c
643
crtc_state->uapi.event = NULL;
sys/dev/pci/drm/i915/display/intel_crtc.c
93
u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_crtc.c
95
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.h
37
void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.h
38
void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crtc.h
40
u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.h
45
void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_crtc.h
48
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc.h
49
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_crtc_state_dump.h
13
void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
137
static int intel_check_cursor(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
153
ret = intel_plane_check_clipping(plane_state, crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
166
-crtc_state->pipe_src.x1,
sys/dev/pci/drm/i915/display/intel_cursor.c
167
-crtc_state->pipe_src.y1);
sys/dev/pci/drm/i915/display/intel_cursor.c
198
static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
202
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_cursor.c
226
static int i845_check_cursor(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
234
ret = intel_check_cursor(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
276
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
287
i845_cursor_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
292
pos = intel_cursor_position(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_cursor.c
317
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
319
i845_cursor_update_arm(dsb, plane, crtc_state, NULL);
sys/dev/pci/drm/i915/display/intel_cursor.c
379
static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
381
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
382
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_cursor.c
388
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_cursor.c
391
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_cursor.c
41
static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
470
static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
479
ret = intel_check_cursor(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
534
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
539
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_cursor.c
547
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
552
int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;
sys/dev/pci/drm/i915/display/intel_cursor.c
56
y - crtc_state->psr2_su_area.y1);
sys/dev/pci/drm/i915/display/intel_cursor.c
566
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
572
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_cursor.c
576
if (crtc_state->enable_psr2_su_region_et) {
sys/dev/pci/drm/i915/display/intel_cursor.c
577
u32 val = intel_cursor_position(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
586
if (crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_cursor.c
587
wa_16021440873(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
589
i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
618
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
623
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
sys/dev/pci/drm/i915/display/intel_cursor.c
625
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/intel_cursor.c
651
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
663
i9xx_cursor_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
669
pos = intel_cursor_position(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_cursor.c
693
skl_write_cursor_wm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
696
i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
698
i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
720
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cursor.c
722
i9xx_cursor_update_arm(dsb, plane, crtc_state, NULL);
sys/dev/pci/drm/i915/display/intel_cursor.c
815
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_cursor.c
830
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_cursor.c
831
intel_crtc_needs_modeset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_cursor.c
832
intel_crtc_needs_fastset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_cursor.c
833
crtc_state->joiner_pipes)
sys/dev/pci/drm/i915/display/intel_cursor.c
881
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
sys/dev/pci/drm/i915/display/intel_cursor.c
909
crtc_state->active_planes = new_crtc_state->active_planes;
sys/dev/pci/drm/i915/display/intel_cursor.c
911
intel_vblank_evade_init(crtc_state, crtc_state, &evade);
sys/dev/pci/drm/i915/display/intel_cursor.c
913
intel_psr_lock(crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
920
intel_psr_wait_for_idle_locked(crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
932
intel_plane_update_noarm(NULL, plane, crtc_state, new_plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
933
intel_plane_update_arm(NULL, plane, crtc_state, new_plane_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
935
intel_plane_disable_arm(NULL, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_cursor.c
940
intel_psr_unlock(crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2013
intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2016
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2017
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2021
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2078
static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2084
tables = intel_c10pll_tables_get(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2089
intel_crtc_has_dp_encoder(crtc_state),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2090
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2091
&crtc_state->dpll_hw_state.cx0pll);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2093
if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2097
intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2098
crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2100
&crtc_state->dpll_hw_state.cx0pll);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2101
crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2223
static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2225
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2247
static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2249
struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2261
if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2264
datarate = ((u64)crtc_state->port_clock * 1000) * 10;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2286
pll_state->clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2288
pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2317
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2320
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2322
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2323
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2337
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2345
static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2352
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2353
if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2357
tables = intel_c20_pll_tables_get(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2362
if (crtc_state->port_clock == tables[i]->clock) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2363
crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2365
&crtc_state->dpll_hw_state.cx0pll,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2366
intel_crtc_has_dp_encoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2367
crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2375
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2379
return intel_c10pll_calc_state(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2380
return intel_c20pll_calc_state(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3102
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3104
__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3105
intel_crtc_has_dp_encoder(crtc_state),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3106
crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3172
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3186
intel_mtl_tbt_clock_select(display, crtc_state->port_clock));
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3227
crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3231
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3236
intel_mtl_tbt_pll_enable(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3238
intel_cx0pll_enable(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3247
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3255
!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
3407
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
424
static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
426
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
427
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
428
(crtc_state->port_clock == 540000 ||
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
429
crtc_state->port_clock == 810000))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
438
static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
440
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
441
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
442
(crtc_state->port_clock == 540000 ||
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
443
crtc_state->port_clock == 810000))
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
453
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
469
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
480
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
484
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
488
for (ln = 0; ln < crtc_state->lane_count; ln++) {
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
489
int level = intel_ddi_level(encoder, crtc_state, ln);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
24
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
28
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
30
int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
43
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_cx0_phy.h
47
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1001
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1012
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1023
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
sys/dev/pci/drm/i915/display/intel_ddi.c
1034
main_link_aux_power_domain_get(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1038
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1040
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1041
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
1058
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1060
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1061
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
1090
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
1097
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi.c
1106
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1126
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1132
encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1154
static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
1157
if (crtc_state->port_clock > 600000)
sys/dev/pci/drm/i915/display/intel_ddi.c
1160
if (crtc_state->lane_count == 4)
sys/dev/pci/drm/i915/display/intel_ddi.c
1167
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1175
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1179
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
1200
int level = intel_ddi_level(encoder, crtc_state, ln);
sys/dev/pci/drm/i915/display/intel_ddi.c
1212
int level = intel_ddi_level(encoder, crtc_state, ln);
sys/dev/pci/drm/i915/display/intel_ddi.c
1223
int level = intel_ddi_level(encoder, crtc_state, ln);
sys/dev/pci/drm/i915/display/intel_ddi.c
1232
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1245
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi.c
1261
icl_combo_phy_loadgen_select(crtc_state, ln));
sys/dev/pci/drm/i915/display/intel_ddi.c
1274
icl_ddi_combo_vswing_program(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1283
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1293
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1308
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1314
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
sys/dev/pci/drm/i915/display/intel_ddi.c
132
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1325
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1334
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
sys/dev/pci/drm/i915/display/intel_ddi.c
1354
crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1362
crtc_state->port_clock > 500000 ?
sys/dev/pci/drm/i915/display/intel_ddi.c
1369
crtc_state->port_clock > 500000 ?
sys/dev/pci/drm/i915/display/intel_ddi.c
1384
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1394
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
140
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1405
crtc_state->port_clock == 594000) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
1407
crtc_state->port_clock == 162000)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
1418
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1428
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
sys/dev/pci/drm/i915/display/intel_ddi.c
1444
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
1484
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
1489
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
1500
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
1507
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1511
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi.c
1514
level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
1525
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1529
int level = intel_ddi_level(encoder, crtc_state, 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1534
skl_ddi_set_iboost(encoder, crtc_state, level);
sys/dev/pci/drm/i915/display/intel_ddi.c
1537
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi.c
1596
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1599
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
163
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1640
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1643
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
166
int level = intel_ddi_level(encoder, crtc_state, 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1684
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1687
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
172
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_ddi.c
1750
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1753
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
1794
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1797
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
1809
icl_ddi_combo_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
1837
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1840
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
1848
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
1945
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
1948
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
2013
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2016
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
2080
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2083
encoder->enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2167
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2169
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2195
width = crtc_state->lane_count;
sys/dev/pci/drm/i915/display/intel_ddi.c
2258
tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2260
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
sys/dev/pci/drm/i915/display/intel_ddi.c
2261
return crtc_state->mst_master_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
2263
return crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
2267
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2273
tgl_dp_tp_transcoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
2279
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2285
tgl_dp_tp_transcoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
2291
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2295
intel_de_write(display, dp_tp_status_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2300
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2304
if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2310
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2315
if (!crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2326
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2331
if (!crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2369
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2376
if (!crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2380
ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2383
ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2406
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2412
if (!crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2415
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2421
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
2428
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2431
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
2435
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2438
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
2447
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2451
if (!crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
2454
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
2456
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
2460
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2469
crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_ddi.c
2526
static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2528
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2529
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
2536
if (crtc_state->splitter.enable) {
sys/dev/pci/drm/i915/display/intel_ddi.c
2538
dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
sys/dev/pci/drm/i915/display/intel_ddi.c
2539
if (crtc_state->splitter.link_count == 2)
sys/dev/pci/drm/i915/display/intel_ddi.c
2584
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2591
val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
2593
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
2620
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2624
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
2629
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_ddi.c
2630
crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
2636
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
265
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
2654
intel_ddi_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2660
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2667
intel_ddi_config_transcoder_func(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
267
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
2672
intel_ddi_mso_configure(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
268
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_ddi.c
2680
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2684
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2691
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
2694
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2715
intel_dp_start_link_train(state, intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2718
if (!is_trans_port_sync_mode(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
2719
intel_dp_stop_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2722
intel_ddi_enable_fec(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2725
if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
2727
ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
sys/dev/pci/drm/i915/display/intel_ddi.c
2729
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2733
intel_dsc_dp_pps_write(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2738
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2744
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
2748
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_ddi.c
2749
crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
2755
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2782
intel_ddi_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2792
icl_program_mg_dp_mode(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2808
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2814
intel_ddi_config_transcoder_func(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2825
encoder->set_signal_levels(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2831
intel_ddi_power_up_lanes(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2836
intel_ddi_mso_configure(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2841
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2845
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2851
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
2854
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2863
intel_dp_start_link_train(state, intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2866
if (!is_trans_port_sync_mode(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
2867
intel_dp_stop_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2870
intel_ddi_enable_fec(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2872
if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
2874
ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);
sys/dev/pci/drm/i915/display/intel_ddi.c
2876
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2880
intel_dsc_dp_pps_write(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2885
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2892
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
2901
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_ddi.c
2902
crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
2908
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2912
intel_ddi_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2920
icl_program_mg_dp_mode(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2923
hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2925
encoder->set_signal_levels(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2927
intel_ddi_power_up_lanes(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2931
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2935
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2936
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
2937
intel_dp_start_link_train(state, intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2939
!is_trans_port_sync_mode(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
2940
intel_dp_stop_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2942
intel_ddi_enable_fec(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2945
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2946
intel_dsc_dp_pps_write(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2952
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2959
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2965
mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2967
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2969
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2974
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
sys/dev/pci/drm/i915/display/intel_ddi.c
2975
intel_ddi_set_dp_msa(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2980
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
2988
intel_ddi_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2994
icl_program_mg_dp_mode(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2996
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
2999
crtc_state->has_infoframe,
sys/dev/pci/drm/i915/display/intel_ddi.c
3000
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3023
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3027
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
3030
drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
3034
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3035
intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3040
intel_ddi_pre_enable_dp(state, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3047
crtc_state->has_infoframe,
sys/dev/pci/drm/i915/display/intel_ddi.c
3048
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3096
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3108
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3109
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
3113
intel_ddi_disable_fec(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3118
intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
3327
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3333
if (!crtc_state->sync_mode_slaves_mask)
sys/dev/pci/drm/i915/display/intel_ddi.c
3349
crtc_state->cpu_transcoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
3359
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3364
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3373
intel_dp_stop_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3376
intel_edp_backlight_on(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3378
intel_panel_prepare(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3381
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3383
trans_port_sync_stop_link_train(state, encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3407
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3417
crtc_state->hdmi_high_tmds_clock_ratio,
sys/dev/pci/drm/i915/display/intel_ddi.c
3418
crtc_state->hdmi_scrambling))
sys/dev/pci/drm/i915/display/intel_ddi.c
3424
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3429
encoder->set_signal_levels(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3466
intel_ddi_power_up_lanes(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3487
port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
3495
buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
3509
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
351
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3514
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
3515
bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_ddi.c
3519
if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3520
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_ddi.c
3529
intel_ddi_enable_transcoder_func(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3531
intel_vrr_transcoder_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3534
if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3537
intel_ddi_clear_act_sent(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3542
intel_ddi_wait_for_act_sent(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3546
intel_enable_transcoder(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3548
intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
3550
for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3558
intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3560
intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3562
intel_hdcp_enable(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
358
intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
sys/dev/pci/drm/i915/display/intel_ddi.c
3623
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3626
intel_ddi_set_dp_msa(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3628
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3630
intel_backlight_update(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3635
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3638
intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3643
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3647
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
sys/dev/pci/drm/i915/display/intel_ddi.c
3649
intel_ddi_update_pipe_dp(state, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3652
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi.c
3653
intel_ddi_update_pipe_hdmi(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3656
intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3664
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_ddi.c
367
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
3673
intel_crtc_joined_pipe_mask(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
3685
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3693
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
3695
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
3699
main_link_aux_power_domain_get(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3706
intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
3709
crtc_state->lane_lat_optim_mask);
sys/dev/pci/drm/i915/display/intel_ddi.c
3724
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3726
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3735
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
374
intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_ddi.c
3741
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
3742
intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3746
if (crtc_state->enhanced_framing)
sys/dev/pci/drm/i915/display/intel_ddi.c
3749
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
sys/dev/pci/drm/i915/display/intel_ddi.c
3750
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
3756
encoder->set_signal_levels(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3759
mtl_port_buf_ctl_program(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3772
intel_alpm_port_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3778
intel_lnl_mac_transmit_lfps(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3782
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3789
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
3794
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
3795
intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
3799
if (crtc_state->enhanced_framing)
sys/dev/pci/drm/i915/display/intel_ddi.c
380
int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_ddi.c
3802
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
sys/dev/pci/drm/i915/display/intel_ddi.c
3803
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
3814
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3821
temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
3842
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);
sys/dev/pci/drm/i915/display/intel_ddi.c
3846
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3852
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
3866
dp_tp_status_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_ddi.c
3885
static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3887
if (crtc_state->port_clock > 594000)
sys/dev/pci/drm/i915/display/intel_ddi.c
3893
static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3895
if (crtc_state->port_clock > 594000)
sys/dev/pci/drm/i915/display/intel_ddi.c
3901
static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3903
if (crtc_state->port_clock > 594000)
sys/dev/pci/drm/i915/display/intel_ddi.c
3909
void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3911
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3914
crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3916
crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3918
crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3920
crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3952
static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
3954
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
3959
crtc_state->master_transcoder =
sys/dev/pci/drm/i915/display/intel_ddi.c
3960
bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
3974
crtc_state->cpu_transcoder)
sys/dev/pci/drm/i915/display/intel_ddi.c
3975
crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
3981
crtc_state->master_transcoder != INVALID_TRANSCODER &&
sys/dev/pci/drm/i915/display/intel_ddi.c
3982
crtc_state->sync_mode_slaves_mask);
sys/dev/pci/drm/i915/display/intel_ddi.c
3986
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
3991
crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_ddi.c
3993
crtc_state->lane_count =
sys/dev/pci/drm/i915/display/intel_ddi.c
3996
crtc_state->lane_count = 4;
sys/dev/pci/drm/i915/display/intel_ddi.c
4000
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4003
crtc_state->has_hdmi_sink = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4005
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_ddi.c
4006
intel_hdmi_infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4008
if (crtc_state->infoframes.enable)
sys/dev/pci/drm/i915/display/intel_ddi.c
4009
crtc_state->has_infoframe = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4012
crtc_state->hdmi_scrambling = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4014
crtc_state->hdmi_high_tmds_clock_ratio = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4016
intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
sys/dev/pci/drm/i915/display/intel_ddi.c
4020
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4025
crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
sys/dev/pci/drm/i915/display/intel_ddi.c
4026
crtc_state->enhanced_framing =
sys/dev/pci/drm/i915/display/intel_ddi.c
4027
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
sys/dev/pci/drm/i915/display/intel_ddi.c
4032
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4036
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
4038
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
4041
crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
sys/dev/pci/drm/i915/display/intel_ddi.c
4043
crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
sys/dev/pci/drm/i915/display/intel_ddi.c
4044
crtc_state->lane_count =
sys/dev/pci/drm/i915/display/intel_ddi.c
4049
crtc_state->mst_master_transcoder =
sys/dev/pci/drm/i915/display/intel_ddi.c
4052
intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_ddi.c
4053
intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/intel_ddi.c
4055
crtc_state->enhanced_framing =
sys/dev/pci/drm/i915/display/intel_ddi.c
4056
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
sys/dev/pci/drm/i915/display/intel_ddi.c
4060
crtc_state->fec_enable =
sys/dev/pci/drm/i915/display/intel_ddi.c
4062
dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
sys/dev/pci/drm/i915/display/intel_ddi.c
4065
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_ddi.c
4066
intel_lspcon_infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4068
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_ddi.c
4069
intel_hdmi_infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4073
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4077
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
4078
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
4080
crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_ddi.c
4081
crtc_state->lane_count =
sys/dev/pci/drm/i915/display/intel_ddi.c
4085
crtc_state->mst_master_transcoder =
sys/dev/pci/drm/i915/display/intel_ddi.c
4088
intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_ddi.c
4091
crtc_state->fec_enable =
sys/dev/pci/drm/i915/display/intel_ddi.c
4093
dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
sys/dev/pci/drm/i915/display/intel_ddi.c
4095
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_ddi.c
4096
intel_hdmi_infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
417
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
420
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
421
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
4222
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4227
struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
sys/dev/pci/drm/i915/display/intel_ddi.c
4237
icl_set_active_port_dpll(crtc_state, port_dpll_id);
sys/dev/pci/drm/i915/display/intel_ddi.c
4239
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
sys/dev/pci/drm/i915/display/intel_ddi.c
424
if (!intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
4240
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4244
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4246
intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
sys/dev/pci/drm/i915/display/intel_ddi.c
4248
if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
sys/dev/pci/drm/i915/display/intel_ddi.c
4249
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
4251
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
sys/dev/pci/drm/i915/display/intel_ddi.c
4253
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4257
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4259
intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);
sys/dev/pci/drm/i915/display/intel_ddi.c
4260
crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);
sys/dev/pci/drm/i915/display/intel_ddi.c
4262
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4266
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4268
intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4269
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4273
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4275
intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4276
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4280
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4282
intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4283
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4287
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4289
intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4290
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4300
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4303
const struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_ddi.c
431
switch (crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_ddi.c
4316
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4321
return encoder->port_pll_type(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4325
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4341
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
sys/dev/pci/drm/i915/display/intel_ddi.c
4347
icl_set_active_port_dpll(crtc_state, port_dpll_id);
sys/dev/pci/drm/i915/display/intel_ddi.c
4349
if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
sys/dev/pci/drm/i915/display/intel_ddi.c
4350
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
sys/dev/pci/drm/i915/display/intel_ddi.c
4352
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
sys/dev/pci/drm/i915/display/intel_ddi.c
4353
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4357
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4359
icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4360
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4364
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4366
intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4367
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4371
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4373
intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4374
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4378
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4380
intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
sys/dev/pci/drm/i915/display/intel_ddi.c
4381
intel_ddi_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4385
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4389
crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4391
if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
4392
(!crtc_state && intel_encoder_is_dp(encoder)))
sys/dev/pci/drm/i915/display/intel_ddi.c
4393
intel_dp_sync_state(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4397
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
4405
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_ddi.c
4409
if (intel_crtc_has_dp_encoder(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_ddi.c
4410
!intel_dp_initial_fastset_check(encoder, crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
4418
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
445
MISSING_CASE(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_ddi.c
450
drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
sys/dev/pci/drm/i915/display/intel_ddi.c
451
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
sys/dev/pci/drm/i915/display/intel_ddi.c
453
if (crtc_state->limited_color_range)
sys/dev/pci/drm/i915/display/intel_ddi.c
4535
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_ddi.c
4544
crtc_state = intel_atomic_get_new_crtc_state(state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4547
crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
4549
transcoders |= BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
4556
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4565
crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
sys/dev/pci/drm/i915/display/intel_ddi.c
4568
port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
4576
crtc_state->master_transcoder = TRANSCODER_EDP;
sys/dev/pci/drm/i915/display/intel_ddi.c
4578
crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
sys/dev/pci/drm/i915/display/intel_ddi.c
4580
if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
sys/dev/pci/drm/i915/display/intel_ddi.c
4581
crtc_state->master_transcoder = INVALID_TRANSCODER;
sys/dev/pci/drm/i915/display/intel_ddi.c
4582
crtc_state->sync_mode_slaves_mask =
sys/dev/pci/drm/i915/display/intel_ddi.c
4583
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
461
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
sys/dev/pci/drm/i915/display/intel_ddi.c
4682
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_ddi.c
470
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
4705
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_ddi.c
4708
!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
sys/dev/pci/drm/i915/display/intel_ddi.c
4710
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_ddi.c
4713
if (!crtc_state->hdmi_high_tmds_clock_ratio &&
sys/dev/pci/drm/i915/display/intel_ddi.c
4714
!crtc_state->hdmi_scrambling)
sys/dev/pci/drm/i915/display/intel_ddi.c
4729
crtc_state->hdmi_high_tmds_clock_ratio &&
sys/dev/pci/drm/i915/display/intel_ddi.c
4731
crtc_state->hdmi_scrambling)
sys/dev/pci/drm/i915/display/intel_ddi.c
486
intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.c
489
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
490
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
496
if (enable && intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
510
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
512
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
513
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
515
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
526
switch (crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_ddi.c
528
MISSING_CASE(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_ddi.c
544
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
sys/dev/pci/drm/i915/display/intel_ddi.c
546
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
sys/dev/pci/drm/i915/display/intel_ddi.c
559
if (crtc_state->pch_pfit.force_thru)
sys/dev/pci/drm/i915/display/intel_ddi.c
573
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
574
if (crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_ddi.c
579
if (crtc_state->hdmi_scrambling)
sys/dev/pci/drm/i915/display/intel_ddi.c
581
if (crtc_state->hdmi_high_tmds_clock_ratio)
sys/dev/pci/drm/i915/display/intel_ddi.c
584
temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
585
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
587
temp |= (crtc_state->fdi_lanes - 1) << 1;
sys/dev/pci/drm/i915/display/intel_ddi.c
588
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
589
intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
590
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
594
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
599
master = crtc_state->mst_master_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
607
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_ddi.c
611
crtc_state->master_transcoder != INVALID_TRANSCODER) {
sys/dev/pci/drm/i915/display/intel_ddi.c
613
bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
sys/dev/pci/drm/i915/display/intel_ddi.c
623
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
625
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
626
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
629
enum transcoder master_transcoder = crtc_state->master_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
647
crtc_state));
sys/dev/pci/drm/i915/display/intel_ddi.c
657
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
659
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
660
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
663
intel_ddi_config_transcoder_dp2(crtc_state, true);
sys/dev/pci/drm/i915/display/intel_ddi.c
665
ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
677
void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
679
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
680
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_ddi.c
681
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_ddi.c
701
if (!intel_dp_mst_is_master_trans(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
712
if (intel_dp_mst_is_slave_trans(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
713
intel_ddi_config_transcoder_dp2(crtc_state, false);
sys/dev/pci/drm/i915/display/intel_ddi.c
716
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_ddi.c
952
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
969
if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi.c
972
(intel_crtc_has_dp_encoder(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_ddi.c
981
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.c
985
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.c
997
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_ddi.h
27
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
30
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
32
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
39
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
42
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.h
45
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
50
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
52
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
55
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
61
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
63
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
64
void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
66
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
67
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
69
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.h
71
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.h
74
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi.h
76
void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_ddi.h
82
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1148
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1151
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1153
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1161
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1164
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1166
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1168
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1196
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1199
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1201
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1210
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1213
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1215
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1224
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1227
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1229
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1238
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1241
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1243
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1252
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1255
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1257
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1266
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1269
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1271
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1280
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1283
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1285
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1294
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1303
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1306
if (crtc_state->port_clock > 540000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1314
return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1319
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1322
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1324
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1325
return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1327
return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1332
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1335
if (crtc_state->port_clock > 270000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1346
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1349
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1352
return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1357
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1360
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1368
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1371
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1373
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1375
return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1382
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1385
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1393
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1396
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1398
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1400
return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1407
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1412
if (crtc_state->port_clock > 270000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1428
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1431
if (crtc_state->port_clock > 540000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1442
return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1447
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1450
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1452
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1453
return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1455
return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1460
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1463
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1473
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1476
if (crtc_state->port_clock > 540000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1486
return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1491
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1494
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1496
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1497
return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1499
return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1504
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1507
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1515
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1518
if (crtc_state->port_clock > 540000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1529
return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1534
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1537
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1539
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1540
return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1542
return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1547
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1550
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1558
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1561
if (crtc_state->port_clock > 540000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1568
return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1573
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1576
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1578
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1579
return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1581
return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1586
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1589
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1597
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1600
if (crtc_state->port_clock > 540000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1611
return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1616
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1619
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1621
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1622
return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1624
return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1629
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1632
if (crtc_state->port_clock > 270000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1643
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1646
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1649
return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1654
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1657
if (crtc_state->port_clock > 270000) {
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1668
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1671
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1674
return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1679
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1682
if (intel_crtc_has_dp_encoder(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1683
intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1691
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1699
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1702
if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_ddi_buf_trans.c
1704
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_display.c
1114
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
1116
u8 update_planes = crtc_state->update_planes;
sys/dev/pci/drm/i915/display/intel_display.c
1131
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
1133
u8 update_planes = crtc_state->update_planes;
sys/dev/pci/drm/i915/display/intel_display.c
1345
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
1360
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_display.c
1367
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
138
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1382
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_display.c
1389
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
139
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
140
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1404
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_display.c
142
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1479
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
1494
crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_display.c
1498
static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1500
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
1501
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
1503
if (crtc_state->has_pch_encoder) {
sys/dev/pci/drm/i915/display/intel_display.c
1505
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_display.c
1506
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
1508
&crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_display.c
1510
&crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/intel_display.c
1513
intel_set_transcoder_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1515
ilk_set_pipeconf(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1593
static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1595
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1597
return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
sys/dev/pci/drm/i915/display/intel_display.c
1609
static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1611
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1612
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
1615
HSW_LINETIME(crtc_state->linetime) |
sys/dev/pci/drm/i915/display/intel_display.c
1616
HSW_IPS_LINETIME(crtc_state->ips_linetime));
sys/dev/pci/drm/i915/display/intel_display.c
1619
static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1621
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1623
intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
sys/dev/pci/drm/i915/display/intel_display.c
1625
HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
sys/dev/pci/drm/i915/display/intel_display.c
1628
static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
1630
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1631
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
1632
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
1634
if (crtc_state->has_pch_encoder) {
sys/dev/pci/drm/i915/display/intel_display.c
1636
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_display.c
1637
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
1639
&crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_display.c
1641
&crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/intel_display.c
1644
intel_set_transcoder_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1648
crtc_state->pixel_multiplier - 1);
sys/dev/pci/drm/i915/display/intel_display.c
1650
hsw_set_frame_start_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1652
hsw_set_transconf(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1946
static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
1949
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1950
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
1951
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
1957
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_display.c
1962
if (crtc_state->pch_pfit.enabled ||
sys/dev/pci/drm/i915/display/intel_display.c
1963
crtc_state->pch_pfit.force_thru)
sys/dev/pci/drm/i915/display/intel_display.c
1967
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_display.c
1973
if (HAS_DDI(display) && crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_display.c
1976
if (crtc_state->intel_dpll)
sys/dev/pci/drm/i915/display/intel_display.c
1979
if (crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_display.c
1983
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
1986
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
1987
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
1991
get_crtc_power_domains(crtc_state, &domains);
sys/dev/pci/drm/i915/display/intel_display.c
2018
static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2020
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2021
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
2023
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
2025
&crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_display.c
2027
&crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/intel_display.c
203
static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2030
intel_set_transcoder_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2032
i9xx_set_pipeconf(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
205
return (crtc_state->active_planes &
sys/dev/pci/drm/i915/display/intel_display.c
2188
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2190
u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_display.c
2198
if (!crtc_state->pch_pfit.enabled)
sys/dev/pci/drm/i915/display/intel_display.c
2202
drm_rect_width(&crtc_state->pipe_src) << 16,
sys/dev/pci/drm/i915/display/intel_display.c
2203
drm_rect_height(&crtc_state->pipe_src) << 16);
sys/dev/pci/drm/i915/display/intel_display.c
2205
return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/intel_display.c
2230
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2232
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2236
crtc_state->pixel_rate =
sys/dev/pci/drm/i915/display/intel_display.c
2237
crtc_state->hw.pipe_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_display.c
2239
crtc_state->pixel_rate =
sys/dev/pci/drm/i915/display/intel_display.c
2240
ilk_pipe_pixel_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2243
static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
2246
int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2260
static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
2263
int overlap = crtc_state->splitter.pixel_overlap;
sys/dev/pci/drm/i915/display/intel_display.c
2264
int n = crtc_state->splitter.link_count;
sys/dev/pci/drm/i915/display/intel_display.c
2266
if (!crtc_state->splitter.enable)
sys/dev/pci/drm/i915/display/intel_display.c
2284
static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2286
struct drm_display_mode *mode = &crtc_state->hw.mode;
sys/dev/pci/drm/i915/display/intel_display.c
2287
struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/intel_display.c
2288
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_display.c
2297
intel_splitter_adjust_timings(crtc_state, pipe_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2309
mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
sys/dev/pci/drm/i915/display/intel_display.c
2310
intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2311
mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2314
intel_joiner_adjust_timings(crtc_state, pipe_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2317
intel_crtc_compute_pixel_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2321
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2323
encoder->get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2325
intel_crtc_readout_derived_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2328
static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2330
int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2336
width = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2337
height = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2339
drm_rect_init(&crtc_state->pipe_src, 0, 0,
sys/dev/pci/drm/i915/display/intel_display.c
2343
static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2345
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2346
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2348
intel_joiner_compute_pipe_src(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2356
if (drm_rect_width(&crtc_state->pipe_src) & 1) {
sys/dev/pci/drm/i915/display/intel_display.c
2357
if (crtc_state->double_wide) {
sys/dev/pci/drm/i915/display/intel_display.c
2364
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
sys/dev/pci/drm/i915/display/intel_display.c
2376
static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2378
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2379
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2380
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_display.c
2381
struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/intel_display.c
239
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2391
intel_splitter_adjust_timings(crtc_state, pipe_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2394
intel_joiner_adjust_timings(crtc_state, pipe_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2407
crtc_state->double_wide = true;
sys/dev/pci/drm/i915/display/intel_display.c
241
return crtc_state->master_transcoder != INVALID_TRANSCODER;
sys/dev/pci/drm/i915/display/intel_display.c
2416
str_yes_no(crtc_state->double_wide));
sys/dev/pci/drm/i915/display/intel_display.c
2423
static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2425
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2431
vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
2440
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
2443
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_display.c
2446
vblank_delay = intel_crtc_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
245
is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2463
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
247
return crtc_state->sync_mode_slaves_mask != 0;
sys/dev/pci/drm/i915/display/intel_display.c
2475
ret = intel_crtc_compute_pipe_src(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2479
ret = intel_crtc_compute_pipe_mode(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2483
intel_crtc_compute_pixel_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2485
if (crtc_state->has_pch_encoder)
sys/dev/pci/drm/i915/display/intel_display.c
2486
return ilk_fdi_compute_config(crtc, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
251
is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
253
return is_trans_port_sync_master(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_display.c
254
is_trans_port_sync_slave(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
257
static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
259
return ffs(crtc_state->joiner_pipes) - 1;
sys/dev/pci/drm/i915/display/intel_display.c
2631
transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2633
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2634
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
2639
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2641
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2642
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2644
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
2645
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_display.c
266
static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2663
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
sys/dev/pci/drm/i915/display/intel_display.c
268
return hweight8(crtc_state->joiner_pipes) >= 2;
sys/dev/pci/drm/i915/display/intel_display.c
271
static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
273
if (!is_bigjoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
2742
crtc_state->min_hblank);
sys/dev/pci/drm/i915/display/intel_display.c
2746
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2748
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2749
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
2750
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_display.c
276
return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
279
static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2802
intel_vrr_set_fixed_rr_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2803
intel_vrr_transcoder_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2806
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2808
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2809
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
281
if (!is_bigjoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
2810
int width = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2811
int height = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2821
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2823
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2824
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
284
return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
287
bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
289
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2893
static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2895
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
2896
int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2903
primary_pipe = joiner_primary_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2904
width = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_display.c
2906
drm_rect_translate_to(&crtc_state->pipe_src,
sys/dev/pci/drm/i915/display/intel_display.c
291
if (!is_bigjoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
2925
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2927
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2928
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
2936
if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
2939
if (crtc_state->double_wide)
sys/dev/pci/drm/i915/display/intel_display.c
294
return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
2946
if (crtc_state->dither && crtc_state->pipe_bpp != 30)
sys/dev/pci/drm/i915/display/intel_display.c
2950
switch (crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_display.c
2953
MISSING_CASE(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_display.c
2967
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
sys/dev/pci/drm/i915/display/intel_display.c
2969
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
sys/dev/pci/drm/i915/display/intel_display.c
297
bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
2978
crtc_state->limited_color_range)
sys/dev/pci/drm/i915/display/intel_display.c
2981
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_display.c
2983
if (crtc_state->wgc_enable)
sys/dev/pci/drm/i915/display/intel_display.c
2986
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_display.c
299
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
301
if (!is_bigjoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
304
return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
307
u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
309
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
311
if (!is_bigjoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
3125
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3127
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3128
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
3135
if (!intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
3138
switch (crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_display.c
314
return bigjoiner_primary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3141
MISSING_CASE(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_display.c
3157
if (crtc_state->dither)
sys/dev/pci/drm/i915/display/intel_display.c
3160
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
sys/dev/pci/drm/i915/display/intel_display.c
3169
drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
sys/dev/pci/drm/i915/display/intel_display.c
317
u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3170
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
sys/dev/pci/drm/i915/display/intel_display.c
3172
if (crtc_state->limited_color_range &&
sys/dev/pci/drm/i915/display/intel_display.c
3173
!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
sys/dev/pci/drm/i915/display/intel_display.c
3176
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_display.c
3179
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
sys/dev/pci/drm/i915/display/intel_display.c
3181
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_display.c
3182
val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
sys/dev/pci/drm/i915/display/intel_display.c
3188
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
319
return bigjoiner_secondary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3190
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3191
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_display.c
3198
if (!intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
3201
if (display->platform.haswell && crtc_state->dither)
sys/dev/pci/drm/i915/display/intel_display.c
3204
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
sys/dev/pci/drm/i915/display/intel_display.c
3210
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_display.c
3218
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
322
bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3220
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3221
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
3224
switch (crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_display.c
324
return intel_crtc_num_joined_pipes(crtc_state) >= 4;
sys/dev/pci/drm/i915/display/intel_display.c
3240
MISSING_CASE(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_display.c
3244
if (crtc_state->dither)
sys/dev/pci/drm/i915/display/intel_display.c
3247
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
sys/dev/pci/drm/i915/display/intel_display.c
3248
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
sys/dev/pci/drm/i915/display/intel_display.c
3251
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_display.c
3255
if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
327
static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
329
if (!intel_crtc_is_ultrajoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
332
return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
335
bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
337
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
339
return intel_crtc_is_ultrajoiner(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_display.c
340
BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
348
static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
350
if (!intel_crtc_is_ultrajoiner(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
353
return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
356
bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
358
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
360
return intel_crtc_is_ultrajoiner(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_display.c
361
BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
364
u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
366
if (crtc_state->joiner_pipes)
sys/dev/pci/drm/i915/display/intel_display.c
367
return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
372
bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
374
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
376
return crtc_state->joiner_pipes &&
sys/dev/pci/drm/i915/display/intel_display.c
377
crtc->pipe != joiner_primary_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
380
bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
382
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
384
return crtc_state->joiner_pipes &&
sys/dev/pci/drm/i915/display/intel_display.c
385
crtc->pipe == joiner_primary_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
388
int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
390
return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
3913
static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
3915
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
3916
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
3925
crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
sys/dev/pci/drm/i915/display/intel_display.c
393
u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
395
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
397
return BIT(crtc->pipe) | crtc_state->joiner_pipes;
sys/dev/pci/drm/i915/display/intel_display.c
400
struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
4019
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
402
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4021
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4022
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
4024
if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
4027
crtc_state->hw.active = true;
sys/dev/pci/drm/i915/display/intel_display.c
4029
intel_crtc_readout_derived_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
404
if (intel_crtc_is_joiner_secondary(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
405
return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
407
return to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
4085
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
4099
crtc_state = intel_crtc_state_alloc(crtc);
sys/dev/pci/drm/i915/display/intel_display.c
4100
if (!crtc_state) {
sys/dev/pci/drm/i915/display/intel_display.c
4105
if (!intel_crtc_get_pipe_config(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
4106
intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_display.c
4111
intel_encoder_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4113
intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_display.c
4115
intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_display.c
4150
static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
4153
&crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/intel_display.c
4156
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_display.c
4165
static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
4169
&crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/intel_display.c
4172
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_display.c
4181
static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
4183
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4185
&crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/intel_display.c
4188
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_display.c
4192
crtc_state->pixel_rate);
sys/dev/pci/drm/i915/display/intel_display.c
4206
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4211
crtc_state->linetime = skl_linetime_wm(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4213
crtc_state->linetime = hsw_linetime_wm(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4222
crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
4232
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4237
intel_crtc_needs_modeset(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_display.c
4238
!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_display.c
4239
crtc_state->update_wm_post = true;
sys/dev/pci/drm/i915/display/intel_display.c
4241
if (intel_crtc_needs_modeset(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
4260
if (intel_crtc_needs_modeset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_display.c
4261
intel_crtc_needs_fastset(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
4262
ret = skl_update_scaler_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4295
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
4297
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4320
if (bpp < crtc_state->pipe_bpp) {
sys/dev/pci/drm/i915/display/intel_display.c
4327
crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_display.c
4329
crtc_state->pipe_bpp = bpp;
sys/dev/pci/drm/i915/display/intel_display.c
4356
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4362
crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);
sys/dev/pci/drm/i915/display/intel_display.c
4371
ret = compute_sink_pipe_bpp(connector_state, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4452
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4455
WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
4457
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
sys/dev/pci/drm/i915/display/intel_display.c
4458
crtc_state->uapi.degamma_lut);
sys/dev/pci/drm/i915/display/intel_display.c
4459
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_display.c
4460
crtc_state->uapi.gamma_lut);
sys/dev/pci/drm/i915/display/intel_display.c
4461
drm_property_replace_blob(&crtc_state->hw.ctm,
sys/dev/pci/drm/i915/display/intel_display.c
4462
crtc_state->uapi.ctm);
sys/dev/pci/drm/i915/display/intel_display.c
4469
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4472
WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
4474
crtc_state->hw.enable = crtc_state->uapi.enable;
sys/dev/pci/drm/i915/display/intel_display.c
4475
crtc_state->hw.active = crtc_state->uapi.active;
sys/dev/pci/drm/i915/display/intel_display.c
4476
drm_mode_copy(&crtc_state->hw.mode,
sys/dev/pci/drm/i915/display/intel_display.c
4477
&crtc_state->uapi.mode);
sys/dev/pci/drm/i915/display/intel_display.c
4478
drm_mode_copy(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_display.c
4479
&crtc_state->uapi.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_display.c
4480
crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
sys/dev/pci/drm/i915/display/intel_display.c
4568
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4578
intel_crtc_free_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4580
err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4592
saved_state->uapi = crtc_state->uapi;
sys/dev/pci/drm/i915/display/intel_display.c
4593
saved_state->inherited = crtc_state->inherited;
sys/dev/pci/drm/i915/display/intel_display.c
4594
saved_state->scaler_state = crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/intel_display.c
4595
saved_state->intel_dpll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_display.c
4596
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
sys/dev/pci/drm/i915/display/intel_display.c
4597
memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
sys/dev/pci/drm/i915/display/intel_display.c
4599
saved_state->crc_enabled = crtc_state->crc_enabled;
sys/dev/pci/drm/i915/display/intel_display.c
4602
saved_state->wm = crtc_state->wm;
sys/dev/pci/drm/i915/display/intel_display.c
4604
memcpy(crtc_state, saved_state, sizeof(*crtc_state));
sys/dev/pci/drm/i915/display/intel_display.c
4618
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4625
crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
sys/dev/pci/drm/i915/display/intel_display.c
4627
crtc_state->framestart_delay = 1;
sys/dev/pci/drm/i915/display/intel_display.c
4634
if (!(crtc_state->hw.adjusted_mode.flags &
sys/dev/pci/drm/i915/display/intel_display.c
4636
crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
sys/dev/pci/drm/i915/display/intel_display.c
4638
if (!(crtc_state->hw.adjusted_mode.flags &
sys/dev/pci/drm/i915/display/intel_display.c
4640
crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
sys/dev/pci/drm/i915/display/intel_display.c
4646
crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_display.c
4647
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
sys/dev/pci/drm/i915/display/intel_display.c
4649
if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
sys/dev/pci/drm/i915/display/intel_display.c
4653
FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
sys/dev/pci/drm/i915/display/intel_display.c
4654
crtc_state->bw_constrained = true;
sys/dev/pci/drm/i915/display/intel_display.c
4657
base_bpp = crtc_state->pipe_bpp;
sys/dev/pci/drm/i915/display/intel_display.c
4667
drm_mode_get_hv_timing(&crtc_state->hw.mode,
sys/dev/pci/drm/i915/display/intel_display.c
4669
drm_rect_init(&crtc_state->pipe_src, 0, 0,
sys/dev/pci/drm/i915/display/intel_display.c
4691
crtc_state->output_types |=
sys/dev/pci/drm/i915/display/intel_display.c
4692
BIT(encoder->compute_output_type(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
4695
crtc_state->output_types |= BIT(encoder->type);
sys/dev/pci/drm/i915/display/intel_display.c
4699
crtc_state->port_clock = 0;
sys/dev/pci/drm/i915/display/intel_display.c
4700
crtc_state->pixel_multiplier = 1;
sys/dev/pci/drm/i915/display/intel_display.c
4703
drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_display.c
4717
ret = encoder->compute_config(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
4730
if (!crtc_state->port_clock)
sys/dev/pci/drm/i915/display/intel_display.c
4731
crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
sys/dev/pci/drm/i915/display/intel_display.c
4732
* crtc_state->pixel_multiplier;
sys/dev/pci/drm/i915/display/intel_display.c
4747
crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
sys/dev/pci/drm/i915/display/intel_display.c
4748
!crtc_state->dither_force_disable;
sys/dev/pci/drm/i915/display/intel_display.c
4752
base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
sys/dev/pci/drm/i915/display/intel_display.c
4761
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
4767
intel_vrr_compute_config_late(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
4779
ret = encoder->compute_config_late(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
5478
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
5482
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
5505
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_display.c
5529
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5532
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
5533
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5534
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
5536
if (!crtc_state->hw.enable ||
sys/dev/pci/drm/i915/display/intel_display.c
5537
intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5540
ret = intel_modeset_pipe(state, crtc_state, reason);
sys/dev/pci/drm/i915/display/intel_display.c
5549
intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
5551
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_display.c
5553
crtc_state->update_pipe = false;
sys/dev/pci/drm/i915/display/intel_display.c
5554
crtc_state->update_m_n = false;
sys/dev/pci/drm/i915/display/intel_display.c
5555
crtc_state->update_lrr = false;
sys/dev/pci/drm/i915/display/intel_display.c
5576
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5579
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
5580
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5581
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
5583
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_display.c
5584
intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5587
ret = intel_modeset_pipe(state, crtc_state, reason);
sys/dev/pci/drm/i915/display/intel_display.c
5591
intel_crtc_flag_modeset(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
5593
crtc_state->update_planes |= crtc_state->active_planes;
sys/dev/pci/drm/i915/display/intel_display.c
5594
crtc_state->async_flip_planes = 0;
sys/dev/pci/drm/i915/display/intel_display.c
5595
crtc_state->do_async_flip = false;
sys/dev/pci/drm/i915/display/intel_display.c
5617
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
5620
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
5621
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
5625
crtc_state->uapi.connectors_changed = true;
sys/dev/pci/drm/i915/display/intel_display.c
5643
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5651
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display.c
5652
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_display.c
5653
!intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5657
other_crtc_state = crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5660
first_crtc_state = crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5671
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
5672
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5673
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
5675
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
sys/dev/pci/drm/i915/display/intel_display.c
5677
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_display.c
5678
intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
5699
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5703
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display.c
5704
if (crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_display.c
5769
struct intel_crtc_state __maybe_unused *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
5773
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display.c
6179
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display.c
6196
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
6197
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
6198
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
6202
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display.c
6203
affected_pipes |= crtc_state->joiner_pipes;
sys/dev/pci/drm/i915/display/intel_display.c
6204
if (intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
6205
modeset_pipes |= crtc_state->joiner_pipes;
sys/dev/pci/drm/i915/display/intel_display.c
6209
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
6210
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
6211
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
6217
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_display.c
6219
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_display.c
6230
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display.c
6232
if (intel_crtc_needs_modeset(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_display.c
6233
intel_crtc_is_joiner_primary(crtc_state))
sys/dev/pci/drm/i915/display/intel_display.c
633
void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.c
642
crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
sys/dev/pci/drm/i915/display/intel_display.c
644
crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
sys/dev/pci/drm/i915/display/intel_display.c
647
void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
649
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
6569
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
657
crtc_state->enabled_planes = 0;
sys/dev/pci/drm/i915/display/intel_display.c
6573
if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
sys/dev/pci/drm/i915/display/intel_display.c
6576
if (crtc_state->has_pch_encoder) {
sys/dev/pci/drm/i915/display/intel_display.c
658
crtc_state->active_planes = 0;
sys/dev/pci/drm/i915/display/intel_display.c
661
crtc_state->uapi.plane_mask) {
sys/dev/pci/drm/i915/display/intel_display.c
662
crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
sys/dev/pci/drm/i915/display/intel_display.c
663
crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
sys/dev/pci/drm/i915/display/intel_display.c
671
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
681
intel_plane_set_invisible(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_display.c
682
intel_set_plane_visible(crtc_state, plane_state, false);
sys/dev/pci/drm/i915/display/intel_display.c
683
intel_plane_fixup_bitmasks(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
687
if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
sys/dev/pci/drm/i915/display/intel_display.c
688
hsw_ips_disable(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
689
crtc_state->ips_enabled = false;
sys/dev/pci/drm/i915/display/intel_display.c
710
if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
sys/dev/pci/drm/i915/display/intel_display.c
7129
static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
713
intel_plane_disable_arm(NULL, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
7131
if (crtc_state->dsb_commit)
sys/dev/pci/drm/i915/display/intel_display.c
7132
intel_dsb_wait(crtc_state->dsb_commit);
sys/dev/pci/drm/i915/display/intel_display.c
7134
intel_color_wait_commit(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
7137
static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
7139
if (crtc_state->dsb_commit) {
sys/dev/pci/drm/i915/display/intel_display.c
7140
intel_dsb_cleanup(crtc_state->dsb_commit);
sys/dev/pci/drm/i915/display/intel_display.c
7141
crtc_state->dsb_commit = NULL;
sys/dev/pci/drm/i915/display/intel_display.c
7144
intel_color_cleanup_commit(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
728
static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
730
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
731
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_display.c
798
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
807
primary_crtc = intel_primary_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
8176
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
8179
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
8180
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
8184
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_display.c
8185
crtc_state->inherited = false;
sys/dev/pci/drm/i915/display/intel_display.c
8187
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_display.c
8200
crtc_state->uapi.color_mgmt_changed = true;
sys/dev/pci/drm/i915/display/intel_display.c
8203
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_display.c
8205
!encoder->initial_fastset_check(encoder, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_display.c
834
static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
836
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
838
if (!crtc_state->nv12_planes)
sys/dev/pci/drm/i915/display/intel_display.c
848
static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
850
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
853
if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
sys/dev/pci/drm/i915/display/intel_display.c
859
static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
861
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
864
if (is_hdr_mode(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_display.c
865
crtc_state->active_planes & BIT(PLANE_CURSOR) &&
sys/dev/pci/drm/i915/display/intel_display.c
891
static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display.c
893
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_display.c
894
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
sys/dev/pci/drm/i915/display/intel_display.c
896
return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
sys/dev/pci/drm/i915/display/intel_display.c
904
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display.c
918
encoder->audio_enable(encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_display.h
358
crtc_state) \
sys/dev/pci/drm/i915/display/intel_display.h
359
for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
sys/dev/pci/drm/i915/display/intel_display.h
360
((crtc_state)->uapi.plane_mask)) \
sys/dev/pci/drm/i915/display/intel_display.h
362
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
sys/dev/pci/drm/i915/display/intel_display.h
384
#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \
sys/dev/pci/drm/i915/display/intel_display.h
386
_intel_modeset_primary_pipes(crtc_state), \
sys/dev/pci/drm/i915/display/intel_display.h
387
_intel_modeset_secondary_pipes(crtc_state), \
sys/dev/pci/drm/i915/display/intel_display.h
390
#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \
sys/dev/pci/drm/i915/display/intel_display.h
392
_intel_modeset_primary_pipes(crtc_state), \
sys/dev/pci/drm/i915/display/intel_display.h
393
_intel_modeset_secondary_pipes(crtc_state), \
sys/dev/pci/drm/i915/display/intel_display.h
415
u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
416
bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
417
bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
418
bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
419
bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
420
bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
421
bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
422
bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
423
u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
424
u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
425
u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
426
struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
427
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
432
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
433
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
448
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
493
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
499
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
502
void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.h
505
void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display.h
521
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display.h
561
int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1006
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1022
crtc_state = to_intel_crtc_state(crtc->state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1023
seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1072
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1088
crtc_state = to_intel_crtc_state(crtc->state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1090
intel_output_format_name(crtc_state->output_format));
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1218
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1225
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
1226
seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
406
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
415
crtc_state->scaler_state.scaler_users,
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
416
crtc_state->scaler_state.scaler_id,
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
417
crtc_state->hw.scaling_filter);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
421
&crtc_state->scaler_state.scalers[i];
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
540
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
548
str_yes_no(crtc_state->uapi.enable),
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
549
str_yes_no(crtc_state->uapi.active),
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
550
DRM_MODE_ARG(&crtc_state->uapi.mode));
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
553
str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active));
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
555
DRM_MODE_ARG(&crtc_state->hw.adjusted_mode));
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
557
DRM_MODE_ARG(&crtc_state->hw.pipe_mode));
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
560
DRM_RECT_ARG(&crtc_state->pipe_src),
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
561
str_yes_no(crtc_state->dither), crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
563
crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
567
if (crtc_state->joiner_pipes)
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
569
crtc_state->joiner_pipes,
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
570
intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master");
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
572
intel_vdsc_state_dump(&p, 1, crtc_state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
575
crtc_state->uapi.encoder_mask)
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
660
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
668
entry = &crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
674
entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
768
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
774
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
775
commit = crtc_state->uapi.commit;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
782
if (!ret && crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
787
intel_crtc_arm_fifo_underrun(crtc, crtc_state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
891
struct intel_crtc_state *crtc_state = NULL;
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
925
crtc_state = to_intel_crtc_state(crtc->state);
sys/dev/pci/drm/i915/display/intel_display_debugfs.c
927
str_yes_no(crtc_state->dsc.compression_enable));
sys/dev/pci/drm/i915/display/intel_display_driver.c
750
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_display_driver.c
764
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_display_driver.c
770
crtc_state->mode_changed = true;
sys/dev/pci/drm/i915/display/intel_display_types.h
1523
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1528
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1533
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
1538
int (*check_plane)(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1541
int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1545
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1560
#define to_intel_crtc_state(crtc_state) \
sys/dev/pci/drm/i915/display/intel_display_types.h
1561
container_of_const((crtc_state), struct intel_crtc_state, uapi)
sys/dev/pci/drm/i915/display/intel_display_types.h
1805
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
1807
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1810
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
1814
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
1919
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1923
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
1928
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
2125
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
2128
return crtc_state->output_types & BIT(type);
sys/dev/pci/drm/i915/display/intel_display_types.h
2132
intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display_types.h
2134
return crtc_state->output_types &
sys/dev/pci/drm/i915/display/intel_display_types.h
214
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
2141
intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display_types.h
2143
return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_display_types.h
2147
intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display_types.h
2149
return crtc_state->update_pipe;
sys/dev/pci/drm/i915/display/intel_display_types.h
2153
intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_display_types.h
2155
return crtc_state->uapi.color_mgmt_changed ||
sys/dev/pci/drm/i915/display/intel_display_types.h
2156
intel_crtc_needs_fastset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_display_types.h
2157
intel_crtc_needs_modeset(crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
235
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
242
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
249
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
277
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
287
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
289
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
292
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_display_types.h
307
void (*enable)(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_display_types.h
531
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.c
742
static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dmc.c
744
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.c
751
if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_dmc.c
757
void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dmc.c
759
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.c
760
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dmc.c
767
if (!can_enable_pipedmc(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dmc.c
768
intel_dmc_disable_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.c
792
void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dmc.c
794
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.c
795
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dmc.h
23
void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dmc.h
24
void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
146
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
148
return drm_dp_is_uhbr_rate(crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_dp.c
1661
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
1666
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
sys/dev/pci/drm/i915/display/intel_dp.c
1667
!intel_dp_supports_fec(intel_dp, connector, crtc_state))
sys/dev/pci/drm/i915/display/intel_dp.c
1670
return intel_dsc_source_support(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
1674
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
1677
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_dp.c
1695
if (intel_hdmi_bpc_possible(crtc_state, bpc,
sys/dev/pci/drm/i915/display/intel_dp.c
1697
intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
sys/dev/pci/drm/i915/display/intel_dp.c
1706
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
1713
bpc = crtc_state->pipe_bpp / 3;
sys/dev/pci/drm/i915/display/intel_dp.c
1721
max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
sys/dev/pci/drm/i915/display/intel_dp.c
1757
static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
1761
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
1885
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
1888
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_dp.c
1898
vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_dp.c
1902
ret = intel_dsc_compute_params(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
2344
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
2346
if (crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_dp.c
2357
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp.c
2360
crtc_state->fec_enable = true;
sys/dev/pci/drm/i915/display/intel_dp.c
2470
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2476
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
2477
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp.c
2481
max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
sys/dev/pci/drm/i915/display/intel_dp.c
2496
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
2502
crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2555
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2561
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp.c
2573
limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
sys/dev/pci/drm/i915/display/intel_dp.c
2583
limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
sys/dev/pci/drm/i915/display/intel_dp.c
2585
limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2590
if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&
sys/dev/pci/drm/i915/display/intel_dp.c
2599
crtc_state)));
sys/dev/pci/drm/i915/display/intel_dp.c
2621
intel_dp_test_compute_config(intel_dp, crtc_state, limits);
sys/dev/pci/drm/i915/display/intel_dp.c
2625
crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2630
int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
2633
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
2634
int bpp = crtc_state->dsc.compression_enable ?
sys/dev/pci/drm/i915/display/intel_dp.c
2635
fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
sys/dev/pci/drm/i915/display/intel_dp.c
2636
crtc_state->pipe_bpp;
sys/dev/pci/drm/i915/display/intel_dp.c
2745
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2751
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
2760
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_dp.c
2769
return crtc_state->pipe_bpp != 18 &&
sys/dev/pci/drm/i915/display/intel_dp.c
2788
static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2792
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
2794
if (crtc_state->has_panel_replay) {
sys/dev/pci/drm/i915/display/intel_dp.c
2813
switch (crtc_state->output_format) {
sys/dev/pci/drm/i915/display/intel_dp.c
2859
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_dp.c
2866
vsc->bpc = crtc_state->pipe_bpp / 3;
sys/dev/pci/drm/i915/display/intel_dp.c
2878
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
2880
struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
sys/dev/pci/drm/i915/display/intel_dp.c
2882
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
2884
if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
sys/dev/pci/drm/i915/display/intel_dp.c
2887
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
sys/dev/pci/drm/i915/display/intel_dp.c
2892
as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
2894
if (crtc_state->cmrr.enable) {
sys/dev/pci/drm/i915/display/intel_dp.c
2905
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2911
!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
sys/dev/pci/drm/i915/display/intel_dp.c
2912
!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_dp.c
2915
vsc = &crtc_state->infoframes.vsc;
sys/dev/pci/drm/i915/display/intel_dp.c
2917
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
sys/dev/pci/drm/i915/display/intel_dp.c
2921
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
sys/dev/pci/drm/i915/display/intel_dp.c
2922
intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2924
} else if (crtc_state->has_panel_replay) {
sys/dev/pci/drm/i915/display/intel_dp.c
2932
} else if (crtc_state->has_sel_update) {
sys/dev/pci/drm/i915/display/intel_dp.c
2967
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
2972
struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
sys/dev/pci/drm/i915/display/intel_dp.c
2985
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_dp.c
3081
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
3089
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
3098
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_dp.c
3100
crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dp.c
3103
crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
sys/dev/pci/drm/i915/display/intel_dp.c
3105
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_dp.c
3108
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
sys/dev/pci/drm/i915/display/intel_dp.c
3113
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
sys/dev/pci/drm/i915/display/intel_dp.c
3114
crtc_state->output_format = intel_dp_output_format(connector,
sys/dev/pci/drm/i915/display/intel_dp.c
3115
crtc_state->sink_format);
sys/dev/pci/drm/i915/display/intel_dp.c
3116
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_dp.c
3139
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
3151
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
sys/dev/pci/drm/i915/display/intel_dp.c
3166
int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
3169
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
3171
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp.c
3173
int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
sys/dev/pci/drm/i915/display/intel_dp.c
3178
int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
sys/dev/pci/drm/i915/display/intel_dp.c
3179
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp.c
3180
int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
3191
if (!is_mst && !intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp.c
3194
if (crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/intel_dp.c
3205
if (crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_dp.c
3206
link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
sys/dev/pci/drm/i915/display/intel_dp.c
3208
link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
sys/dev/pci/drm/i915/display/intel_dp.c
3209
crtc_state->pipe_bpp));
sys/dev/pci/drm/i915/display/intel_dp.c
3235
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp.c
3242
(crtc_state->dsc.compression_enable &&
sys/dev/pci/drm/i915/display/intel_dp.c
3243
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
sys/dev/pci/drm/i915/display/intel_dp.c
3244
crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));
sys/dev/pci/drm/i915/display/intel_dp.c
3250
crtc_state->min_hblank = min_hblank;
sys/dev/pci/drm/i915/display/intel_dp.c
3395
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
3398
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
3406
intel_backlight_enable(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_dp.c
3723
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
3732
if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
sys/dev/pci/drm/i915/display/intel_dp.c
3737
intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
sys/dev/pci/drm/i915/display/intel_dp.c
3739
if (crtc_state) {
sys/dev/pci/drm/i915/display/intel_dp.c
3741
intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp.c
3747
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
3758
crtc_state->port_clock) < 0) {
sys/dev/pci/drm/i915/display/intel_dp.c
3762
crtc_state->uapi.connectors_changed = true;
sys/dev/pci/drm/i915/display/intel_dp.c
3773
if (crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/intel_dp.c
3777
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_dp.c
3785
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_dp.c
4010
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
4012
int vactive = crtc_state->hw.adjusted_mode.vdisplay;
sys/dev/pci/drm/i915/display/intel_dp.c
4019
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
4028
return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
sys/dev/pci/drm/i915/display/intel_dp.c
4035
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4040
int output_format = crtc_state->output_format;
sys/dev/pci/drm/i915/display/intel_dp.c
4053
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
4080
slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
4084
num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
4088
slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
sys/dev/pci/drm/i915/display/intel_dp.c
4091
bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4109
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
4130
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
sys/dev/pci/drm/i915/display/intel_dp.c
4131
switch (crtc_state->output_format) {
sys/dev/pci/drm/i915/display/intel_dp.c
4142
MISSING_CASE(crtc_state->output_format);
sys/dev/pci/drm/i915/display/intel_dp.c
4145
} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
sys/dev/pci/drm/i915/display/intel_dp.c
4146
switch (crtc_state->output_format) {
sys/dev/pci/drm/i915/display/intel_dp.c
4153
MISSING_CASE(crtc_state->output_format);
sys/dev/pci/drm/i915/display/intel_dp.c
4663
intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4671
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_dp.c
4796
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4804
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_dp.c
4810
len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
sys/dev/pci/drm/i915/display/intel_dp.c
4814
&crtc_state->infoframes.drm.drm,
sys/dev/pci/drm/i915/display/intel_dp.c
4818
len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
sys/dev/pci/drm/i915/display/intel_dp.c
4829
dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
sys/dev/pci/drm/i915/display/intel_dp.c
4834
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4838
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp.c
4856
if (!enable || !crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_dp.c
4865
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
sys/dev/pci/drm/i915/display/intel_dp.c
4866
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
sys/dev/pci/drm/i915/display/intel_dp.c
4868
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
sys/dev/pci/drm/i915/display/intel_dp.c
4978
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
4987
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_dp.c
4991
dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
sys/dev/pci/drm/i915/display/intel_dp.c
5046
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5055
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_dp.c
5059
dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
sys/dev/pci/drm/i915/display/intel_dp.c
5068
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5077
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_dp.c
5081
dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
sys/dev/pci/drm/i915/display/intel_dp.c
5093
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5098
intel_read_dp_vsc_sdp(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5099
&crtc_state->infoframes.vsc);
sys/dev/pci/drm/i915/display/intel_dp.c
5102
intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5103
&crtc_state->infoframes.drm.drm);
sys/dev/pci/drm/i915/display/intel_dp.c
5106
intel_read_dp_as_sdp(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.c
5107
&crtc_state->infoframes.as_sdp);
sys/dev/pci/drm/i915/display/intel_dp.c
5369
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp.c
5383
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_dp.c
5386
!intel_crtc_has_dp_encoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_dp.c
5388
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_dp.c
6145
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp.c
6149
if (crtc_state && crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/intel_dp.c
6208
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp.c
6227
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_dp.c
6228
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_dp.c
6248
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp.c
6251
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_dp.c
6252
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp.c
6253
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.c
6255
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_dp.c
6258
if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
sys/dev/pci/drm/i915/display/intel_dp.c
6261
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_dp.c
6271
transcoders &= ~BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp.h
101
int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
125
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
128
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
131
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
175
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
179
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
183
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
185
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
189
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
197
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
212
int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
40
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp.h
47
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
51
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
62
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
85
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp.h
92
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
304
intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
307
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
334
panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
483
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_aux_backlight.c
499
panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1000
if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1007
if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1025
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1036
intel_dp_is_uhbr(crtc_state));
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1038
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1044
if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1061
crtc_state->lane_count)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1069
crtc_state->lane_count)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1076
intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1078
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1104
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1135
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1143
intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1146
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1147
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1166
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1171
if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1174
if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1183
crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1206
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1213
i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1271
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1277
lane_count = crtc_state->lane_count;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1278
link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1280
lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1293
static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1297
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1298
return reduce_link_params_in_bw_order(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1301
return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1306
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1318
if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1330
crtc_state->lane_count, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1341
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1354
} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1359
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1367
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1376
ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1384
ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1387
intel_dp->set_idle_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1397
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1411
if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1426
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1427
if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1433
if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1457
if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1477
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1480
if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1529
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1559
drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1585
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1591
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1599
if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1600
intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1606
crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1618
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1639
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1660
intel_dp_prepare_link_train(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1662
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1663
passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1665
passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1697
if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1709
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1717
if (!intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
335
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
346
voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
390
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
398
lane = min(lane, crtc_state->lane_count - 1);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
401
for (lane = 0; lane < crtc_state->lane_count; lane++)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
410
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
421
lane = min(lane, crtc_state->lane_count - 1);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
426
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
438
voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
446
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
451
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
452
return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
455
return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
484
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
491
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
495
crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
502
crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
508
u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
530
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
538
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
543
memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
544
len = crtc_state->lane_count + 1;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
566
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
576
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
605
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
610
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
614
crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
621
crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
627
encoder->set_signal_levels(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
632
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
637
intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
638
return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
643
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
651
intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
654
intel_dp->train_set, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
656
return ret == crtc_state->lane_count;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
693
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
697
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
700
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
723
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
739
crtc_state->port_clock, crtc_state->vrr.in_range);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
776
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
783
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
797
} else if (crtc_state->port_clock == 810000) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
815
} else if (crtc_state->port_clock >= 540000) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
828
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
831
intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
832
crtc_state->enhanced_framing);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
841
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
846
intel_dp->prepare_link_retrain(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
848
intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
882
intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
883
intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
889
static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
895
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
898
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
931
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
942
intel_dp_is_uhbr(crtc_state));
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
945
if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
975
if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
993
intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
995
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
27
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
31
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
35
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
39
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
41
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_link_training.h
54
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1178
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1181
crtc_state->port_clock, crtc_state->lane_count))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1187
crtc_state->port_clock, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1252
static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1254
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1265
if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1266
set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1270
if (intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1271
set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1272
else if (crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1273
clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1275
if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1276
set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1373
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1377
return intel_dp_initial_fastset_check(primary_encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
142
static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
145
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
147
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
149
if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
172
return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
177
static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
181
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
185
flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
187
flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1912
bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1914
return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1917
bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1919
return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
sys/dev/pci/drm/i915/display/intel_dp_mst.c
192
overhead = drm_dp_bw_overhead(crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
1920
crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
202
return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
sys/dev/pci/drm/i915/display/intel_dp_mst.c
205
static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
211
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
214
intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
216
crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
236
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
239
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
240
int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
248
static void mst_stream_update_slots(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
251
u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
sys/dev/pci/drm/i915/display/intel_dp_mst.c
258
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
263
struct drm_atomic_state *state = crtc_state->uapi.state;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
268
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
269
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
290
mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
291
crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
293
mst_stream_update_slots(crtc_state, mst_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
297
if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
300
crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
303
max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));
sys/dev/pci/drm/i915/display/intel_dp_mst.c
314
dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
337
fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
340
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
343
intel_dp_mst_compute_m_n(crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
346
&crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
353
remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
382
remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
393
drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
394
crtc_state->dp_m_n.tu = remote_tu;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
405
crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
406
4 / crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
408
if (crtc_state->dp_m_n.tu <= 64)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
409
slots = crtc_state->dp_m_n.tu;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
418
drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
431
crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
433
crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
442
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
446
crtc_state->lane_count = limits->max_lane_count;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
447
crtc_state->port_clock = limits->max_rate;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
453
return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
460
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
493
crtc_state->pipe_bpp = max_bpp;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
504
max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_step_x16);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
510
crtc_state->lane_count = limits->max_lane_count;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
511
crtc_state->port_clock = limits->max_rate;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
513
return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
528
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
532
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
546
if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
555
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
560
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
563
if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
567
if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_mst.c
615
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
623
crtc_state, false, dsc,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
629
crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
768
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
775
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
777
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
780
transcoders |= BIT(crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
827
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dp_mst.c
831
if (drm_WARN_ON(display->drm, !crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_mst.c
834
if (crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_dp_mst.c
911
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_mst.c
918
crtc_state->mst_master_transcoder =
sys/dev/pci/drm/i915/display/intel_dp_mst.c
952
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp_mst.c
970
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
971
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dp_mst.c
972
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.c
979
crtc_state->uapi.mode_changed = true;
sys/dev/pci/drm/i915/display/intel_dp_mst.h
22
bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
23
bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_mst.h
35
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_test.c
221
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_test.c
226
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp_test.c
236
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_dp_test.c
297
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
sys/dev/pci/drm/i915/display/intel_dp_test.c
307
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_test.c
321
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
sys/dev/pci/drm/i915/display/intel_dp_test.c
324
intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
sys/dev/pci/drm/i915/display/intel_dp_test.c
326
intel_dp_phy_pattern_update(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_test.c
329
intel_dp->train_set, crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dp_test.c
417
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp_test.c
431
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_dp_test.c
434
!intel_crtc_has_dp_encoder(crtc_state));
sys/dev/pci/drm/i915/display/intel_dp_test.c
436
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_dp_test.c
475
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dp_test.c
480
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
sys/dev/pci/drm/i915/display/intel_dp_test.c
481
!intel_dp_mst_is_master_trans(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_test.c
484
intel_dp_process_phy_request(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
131
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
133
int stream_bw = intel_dp_config_required_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
296
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
338
if (crtc_state) {
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
339
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
512
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
515
if (!crtc_state->dp_tunnel_ref.tunnel)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
524
crtc_state->dp_tunnel_ref.tunnel);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
526
return intel_dp_tunnel_atomic_add_group_state(state, crtc_state->dp_tunnel_ref.tunnel);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
587
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
591
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
592
int required_rate = intel_dp_config_required_rate(crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
613
&crtc_state->dp_tunnel_ref);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
629
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
631
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
634
if (!crtc_state->dp_tunnel_ref.tunnel)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
638
crtc_state->dp_tunnel_ref.tunnel,
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
643
drm_dp_tunnel_ref_put(&crtc_state->dp_tunnel_ref);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
720
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
725
encoder = intel_get_crtc_new_encoder(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
736
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
742
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
745
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
747
struct drm_dp_tunnel *tunnel = crtc_state->dp_tunnel_ref.tunnel;
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
750
if (!intel_crtc_needs_modeset(crtc_state))
sys/dev/pci/drm/i915/display/intel_dp_tunnel.c
761
queue_retry_work(state, tunnel, crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
30
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
42
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
44
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
70
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
86
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dp_tunnel.h
93
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1011
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1021
__chv_data_lane_soft_reset(encoder, crtc_state, false);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1073
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1101
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1129
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1134
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
296
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
304
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
318
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
319
int level = intel_ddi_level(encoder, crtc_state, lane);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
327
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
328
int level = intel_ddi_level(encoder, crtc_state, lane);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
342
for (lane = 0; lane < crtc_state->lane_count; lane++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
343
int level = intel_ddi_level(encoder, crtc_state, lane);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
716
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
736
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
749
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
757
for (i = 0; i < crtc_state->lane_count; i++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
765
for (i = 0; i < crtc_state->lane_count; i++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
788
for (i = 0; i < crtc_state->lane_count; i++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
802
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
812
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
828
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
845
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
857
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
863
__chv_data_lane_soft_reset(encoder, crtc_state, reset);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
868
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
872
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
877
intel_dp_unused_lane_mask(crtc_state->lane_count);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
893
__chv_data_lane_soft_reset(encoder, crtc_state, true);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
923
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
949
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
966
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
973
for (i = 0; i < crtc_state->lane_count; i++) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
975
if (crtc_state->lane_count == 1)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
983
if (crtc_state->port_clock > 270000)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
985
else if (crtc_state->port_clock > 135000)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
987
else if (crtc_state->port_clock > 67500)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
989
else if (crtc_state->port_clock > 33750)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
998
if (crtc_state->lane_count > 2) {
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
131
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
137
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
142
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
146
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
158
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
164
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
168
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
33
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
51
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
55
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
58
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
60
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
66
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
70
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
72
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpio_phy.h
83
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1002
static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1006
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1011
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
sys/dev/pci/drm/i915/display/intel_dpll.c
1018
dpll |= (crtc_state->pixel_multiplier - 1)
sys/dev/pci/drm/i915/display/intel_dpll.c
1022
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
sys/dev/pci/drm/i915/display/intel_dpll.c
1023
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1026
if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll.c
1060
if (crtc_state->sdvo_tv_clock)
sys/dev/pci/drm/i915/display/intel_dpll.c
1062
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1071
static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1075
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1076
struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1086
hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
sys/dev/pci/drm/i915/display/intel_dpll.c
1089
hw_state->dpll_md = i965_dpll_md(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1092
static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1096
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1101
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1127
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
sys/dev/pci/drm/i915/display/intel_dpll.c
1130
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1139
static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1143
struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1148
hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
sys/dev/pci/drm/i915/display/intel_dpll.c
1155
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1158
intel_get_crtc_new_encoder(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1162
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1170
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1174
if (!crtc_state->has_pch_encoder)
sys/dev/pci/drm/i915/display/intel_dpll.c
1175
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1184
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1187
intel_get_crtc_new_encoder(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1190
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1199
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1202
intel_get_crtc_new_encoder(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1205
ret = intel_mpllb_calc_state(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
1209
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1217
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1220
intel_get_crtc_new_encoder(state, crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1223
ret = intel_cx0pll_calc_state(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
1228
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1230
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1235
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1237
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1239
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1244
if (crtc_state->sdvo_tv_clock)
sys/dev/pci/drm/i915/display/intel_dpll.c
1266
static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1270
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1275
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
sys/dev/pci/drm/i915/display/intel_dpll.c
1280
dpll |= (crtc_state->pixel_multiplier - 1)
sys/dev/pci/drm/i915/display/intel_dpll.c
1283
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
sys/dev/pci/drm/i915/display/intel_dpll.c
1284
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1287
if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll.c
1305
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
sys/dev/pci/drm/i915/display/intel_dpll.c
1329
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1338
static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
1342
struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1343
int factor = ilk_fb_cb_factor(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1348
hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
sys/dev/pci/drm/i915/display/intel_dpll.c
1355
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1362
if (!crtc_state->has_pch_encoder)
sys/dev/pci/drm/i915/display/intel_dpll.c
1365
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1388
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1389
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1390
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1393
i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1395
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
sys/dev/pci/drm/i915/display/intel_dpll.c
1396
&crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1402
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1403
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1411
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1415
if (!crtc_state->has_pch_encoder)
sys/dev/pci/drm/i915/display/intel_dpll.c
1421
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1423
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
1433
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1439
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1441
struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1443
hw_state->dpll = vlv_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1444
hw_state->dpll_md = i965_dpll_md(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1447
static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1449
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
1459
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1465
void chv_compute_dpll(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1467
struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1469
hw_state->dpll = chv_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1470
hw_state->dpll_md = i965_dpll_md(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1476
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1481
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1482
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1483
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1486
chv_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1488
chv_compute_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1491
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1494
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1495
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1503
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1508
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1509
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1510
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1513
vlv_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1515
vlv_compute_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1518
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1521
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1522
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1531
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1536
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1548
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
sys/dev/pci/drm/i915/display/intel_dpll.c
1549
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1551
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1558
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1559
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1560
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1563
i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1565
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
sys/dev/pci/drm/i915/display/intel_dpll.c
1566
&crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1568
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1570
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
sys/dev/pci/drm/i915/display/intel_dpll.c
1571
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1580
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1585
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1598
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1599
!pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1600
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1603
pnv_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1605
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
sys/dev/pci/drm/i915/display/intel_dpll.c
1606
&crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1608
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1609
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1618
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1623
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1636
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1637
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1638
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1641
i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1643
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
sys/dev/pci/drm/i915/display/intel_dpll.c
1644
&crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1646
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1648
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
sys/dev/pci/drm/i915/display/intel_dpll.c
1649
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1658
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1663
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1672
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1678
if (!crtc_state->clock_set &&
sys/dev/pci/drm/i915/display/intel_dpll.c
1679
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll.c
1680
refclk, NULL, &crtc_state->dpll))
sys/dev/pci/drm/i915/display/intel_dpll.c
1683
i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1685
i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
sys/dev/pci/drm/i915/display/intel_dpll.c
1686
&crtc_state->dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1688
crtc_state->port_clock = crtc_state->dpll.dot;
sys/dev/pci/drm/i915/display/intel_dpll.c
1689
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1740
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1744
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
sys/dev/pci/drm/i915/display/intel_dpll.c
1746
memset(&crtc_state->dpll_hw_state, 0,
sys/dev/pci/drm/i915/display/intel_dpll.c
1747
sizeof(crtc_state->dpll_hw_state));
sys/dev/pci/drm/i915/display/intel_dpll.c
1749
if (!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_dpll.c
1766
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll.c
1770
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
sys/dev/pci/drm/i915/display/intel_dpll.c
1771
drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);
sys/dev/pci/drm/i915/display/intel_dpll.c
1773
if (!crtc_state->hw.enable || crtc_state->intel_dpll)
sys/dev/pci/drm/i915/display/intel_dpll.c
1822
void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1824
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1825
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
1826
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1830
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
1901
static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1903
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1904
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
1905
const struct dpll *clock = &crtc_state->dpll;
sys/dev/pci/drm/i915/display/intel_dpll.c
1950
if (crtc_state->port_clock == 162000 ||
sys/dev/pci/drm/i915/display/intel_dpll.c
1951
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
sys/dev/pci/drm/i915/display/intel_dpll.c
1952
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll.c
1957
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
1973
if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll.c
1982
static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1984
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
1985
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
1986
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
1997
void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
1999
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2000
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2001
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
2004
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
2014
vlv_prepare_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2015
_vlv_enable_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2022
static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2024
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2025
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2026
const struct dpll *clock = &crtc_state->dpll;
sys/dev/pci/drm/i915/display/intel_dpll.c
2111
static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2113
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2114
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2115
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
2143
void chv_enable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2145
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2146
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2147
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
2150
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
2160
chv_prepare_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2161
_chv_enable_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2205
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_dpll.c
2207
crtc_state = intel_crtc_state_alloc(crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2208
if (!crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2211
crtc_state->cpu_transcoder = (enum transcoder)pipe;
sys/dev/pci/drm/i915/display/intel_dpll.c
2212
crtc_state->pixel_multiplier = 1;
sys/dev/pci/drm/i915/display/intel_dpll.c
2213
crtc_state->dpll = *dpll;
sys/dev/pci/drm/i915/display/intel_dpll.c
2214
crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
sys/dev/pci/drm/i915/display/intel_dpll.c
2217
chv_compute_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2218
chv_enable_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2220
vlv_compute_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2221
vlv_enable_pll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2224
intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_dpll.c
2272
void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
2274
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
2275
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
2283
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dpll.c
375
static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
377
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
378
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
423
void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
425
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
426
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
427
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
432
int refclk = i9xx_pll_refclk(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
512
crtc_state->port_clock = port_clock;
sys/dev/pci/drm/i915/display/intel_dpll.c
515
void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
517
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
518
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
521
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
540
crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
sys/dev/pci/drm/i915/display/intel_dpll.c
543
void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
545
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
546
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll.c
549
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
sys/dev/pci/drm/i915/display/intel_dpll.c
574
crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
sys/dev/pci/drm/i915/display/intel_dpll.c
621
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
624
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
626
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
sys/dev/pci/drm/i915/display/intel_dpll.c
655
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
660
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
666
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
sys/dev/pci/drm/i915/display/intel_dpll.c
713
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
718
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
724
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
sys/dev/pci/drm/i915/display/intel_dpll.c
769
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
774
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
783
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
sys/dev/pci/drm/i915/display/intel_dpll.c
863
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
868
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
920
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
925
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.c
976
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
982
return chv_find_best_dpll(limit, crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.c
983
crtc_state->port_clock, refclk,
sys/dev/pci/drm/i915/display/intel_dpll.c
997
static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll.c
999
return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
sys/dev/pci/drm/i915/display/intel_dpll.h
28
void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
29
void chv_compute_dpll(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
35
void chv_enable_pll(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
37
void vlv_enable_pll(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
39
void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
40
void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
41
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll.h
45
void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
46
void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll.h
47
void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1044
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1046
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1049
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1056
crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1057
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1066
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1070
&crtc_state->dpll_hw_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1076
hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1078
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1079
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1094
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1096
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1099
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1152
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1154
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1156
if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1169
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1172
return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1205
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1208
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1210
else if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1211
return hsw_ddi_lcpll_compute_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1212
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1222
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1226
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1228
else if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1229
pll = hsw_ddi_lcpll_get_dpll(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1230
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1237
pll, &crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1239
crtc_state->intel_dpll = pll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1810
static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1812
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1813
struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1817
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1842
crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1843
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1849
skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1851
struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1859
switch (crtc_state->port_clock / 2) {
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1925
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1928
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1929
return skl_ddi_hdmi_pll_dividers(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1930
else if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1931
return skl_ddi_dp_set_dpll_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1940
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1944
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1946
&crtc_state->dpll_hw_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1950
&crtc_state->dpll_hw_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1958
pll, &crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1960
crtc_state->intel_dpll = pll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2264
bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2267
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2274
if (!bxt_find_best_dpll(crtc_state, clk_div))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2282
static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2285
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2290
if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2299
clk_div->dot != crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2302
static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2305
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2306
struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2307
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2390
bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2394
bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2396
return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2400
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2402
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2406
bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2408
ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2412
crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2413
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2422
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2425
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2426
return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2427
else if (intel_crtc_has_dp_encoder(crtc_state))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2428
return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2438
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2451
pll, &crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2453
crtc_state->intel_dpll = pll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
258
void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
260
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
261
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
262
struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
263
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2707
static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2710
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2715
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2729
static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2732
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2793
icl_calc_wrpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2796
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
2798
u32 afe_clock = crtc_state->port_clock * 5;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3005
static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3008
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3011
int clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3019
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
304
void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
306
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
307
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
308
struct intel_dpll *pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
309
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3290
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3294
&crtc_state->icl_port_dplls[port_dpll_id];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3296
crtc_state->intel_dpll = port_dpll->pll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3297
crtc_state->dpll_hw_state = port_dpll->hw_state;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3304
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3318
icl_set_active_port_dpll(crtc_state, port_dpll_id);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3325
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3328
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3332
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3333
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3334
ret = icl_calc_wrpll(crtc_state, &pll_params);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3336
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3344
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3346
crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3357
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3360
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3417
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3422
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3426
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3427
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3433
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3434
ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3441
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3443
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3445
crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3455
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3458
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3462
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3471
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3488
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4528
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4531
if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
615
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
631
&crtc_state->dpll_hw_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
641
pll, &crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
643
crtc_state->intel_dpll = pll;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
417
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
428
void intel_dpll_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.h
429
void intel_dpll_disable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.c
132
static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_drrs.c
134
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.c
135
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_drrs.c
141
crtc_state->joiner_pipes)
sys/dev/pci/drm/i915/display/intel_drrs.c
153
void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_drrs.c
155
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_drrs.c
157
if (!crtc_state->has_drrs)
sys/dev/pci/drm/i915/display/intel_drrs.c
160
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_drrs.c
163
if (intel_crtc_is_joiner_secondary(crtc_state))
sys/dev/pci/drm/i915/display/intel_drrs.c
168
crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_drrs.c
169
crtc->drrs.m_n = crtc_state->dp_m_n;
sys/dev/pci/drm/i915/display/intel_drrs.c
170
crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;
sys/dev/pci/drm/i915/display/intel_drrs.c
171
crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.c
315
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_drrs.c
322
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_drrs.c
328
crtc_state->cpu_transcoder)));
sys/dev/pci/drm/i915/display/intel_drrs.c
331
str_yes_no(crtc_state->has_drrs));
sys/dev/pci/drm/i915/display/intel_drrs.c
356
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_drrs.c
364
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_drrs.c
366
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_drrs.c
367
!crtc_state->has_drrs)
sys/dev/pci/drm/i915/display/intel_drrs.c
370
commit = crtc_state->uapi.commit;
sys/dev/pci/drm/i915/display/intel_drrs.c
380
intel_drrs_activate(crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.c
382
intel_drrs_deactivate(crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.h
23
void intel_drrs_activate(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_drrs.h
24
void intel_drrs_deactivate(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_dsb.c
121
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
131
return intel_vrr_vblank_delay(crtc_state) + 1;
sys/dev/pci/drm/i915/display/intel_dsb.c
133
return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dsb.c
139
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
143
return intel_vrr_vmax_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_dsb.c
145
return intel_mode_vtotal(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dsb.c
152
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
156
return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) -
sys/dev/pci/drm/i915/display/intel_dsb.c
157
intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency);
sys/dev/pci/drm/i915/display/intel_dsb.c
163
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
166
return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dsb.c
172
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
176
return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
sys/dev/pci/drm/i915/display/intel_dsb.c
707
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
709
int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_dsb.c
722
if (crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_dsb.c
726
int vblank_delay = intel_vrr_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_dsb.c
728
end = intel_vrr_vmin_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_dsb.c
732
end = intel_vrr_vmax_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_dsb.c
736
int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dsb.c
738
end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_dsb.c
822
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_dsb.c
824
int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_dsi_dcs_backlight.c
128
static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_fbc.c
1300
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbc.c
1313
fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_fbc.c
1370
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fbc.c
1381
if (intel_crtc_needs_modeset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_fbc.c
1399
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbc.c
1418
crtc_state);
sys/dev/pci/drm/i915/display/intel_fbc.c
1433
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_fbc.c
1470
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_fbc.c
1472
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
sys/dev/pci/drm/i915/display/intel_fbc.c
1477
if (crtc_state->double_wide) {
sys/dev/pci/drm/i915/display/intel_fbc.c
1494
if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) {
sys/dev/pci/drm/i915/display/intel_fbc.c
1502
crtc_state->has_psr && !crtc_state->has_panel_replay) {
sys/dev/pci/drm/i915/display/intel_fbc.c
1571
if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
sys/dev/pci/drm/i915/display/intel_fbc.c
1926
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbc.c
1940
if (intel_crtc_needs_fastset(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_fbdev.c
405
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbdev.c
413
if (!crtc_state->uapi.active) {
sys/dev/pci/drm/i915/display/intel_fbdev.c
444
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbdev.c
450
if (!crtc_state->uapi.active) {
sys/dev/pci/drm/i915/display/intel_fbdev.c
465
cur_size = crtc_state->uapi.adjusted_mode.crtc_hdisplay;
sys/dev/pci/drm/i915/display/intel_fbdev.c
476
cur_size = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_fbdev.c
482
crtc_state->uapi.adjusted_mode.crtc_hdisplay,
sys/dev/pci/drm/i915/display/intel_fbdev.c
483
crtc_state->uapi.adjusted_mode.crtc_vdisplay,
sys/dev/pci/drm/i915/display/intel_fbdev.c
514
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_fbdev.c
521
if (!crtc_state->uapi.active)
sys/dev/pci/drm/i915/display/intel_fdi.c
1007
temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
sys/dev/pci/drm/i915/display/intel_fdi.c
122
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
126
display->funcs.fdi->fdi_link_train(crtc, crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
177
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
179
if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
sys/dev/pci/drm/i915/display/intel_fdi.c
180
return crtc_state->fdi_lanes;
sys/dev/pci/drm/i915/display/intel_fdi.c
26
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
370
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_fdi.c
373
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_fdi.c
376
if (!crtc_state->has_pch_encoder ||
sys/dev/pci/drm/i915/display/intel_fdi.c
377
!intel_crtc_needs_modeset(crtc_state) ||
sys/dev/pci/drm/i915/display/intel_fdi.c
378
!crtc_state->hw.enable)
sys/dev/pci/drm/i915/display/intel_fdi.c
381
ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
sys/dev/pci/drm/i915/display/intel_fdi.c
414
static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
416
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
417
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_fdi.c
423
if (crtc_state->fdi_lanes > 2)
sys/dev/pci/drm/i915/display/intel_fdi.c
479
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
494
assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_fdi.c
510
temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
sys/dev/pci/drm/i915/display/intel_fdi.c
580
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
609
temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
sys/dev/pci/drm/i915/display/intel_fdi.c
715
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
722
ivb_update_fdi_bc_bifurcation(crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
765
temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
sys/dev/pci/drm/i915/display/intel_fdi.c
850
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
852
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
856
encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_fdi.c
858
hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
876
FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
sys/dev/pci/drm/i915/display/intel_fdi.c
886
drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);
sys/dev/pci/drm/i915/display/intel_fdi.c
887
intel_ddi_enable_clock(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
905
((crtc_state->fdi_lanes - 1) << 1) |
sys/dev/pci/drm/i915/display/intel_fdi.c
995
void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_fdi.c
997
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.c
998
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_fdi.h
30
void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.h
33
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_fdi.h
38
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_flipq.c
200
static int intel_flipq_exec_time_lines(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_flipq.c
202
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_flipq.c
204
return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
sys/dev/pci/drm/i915/display/intel_flipq.c
284
void intel_flipq_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_flipq.c
286
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_flipq.c
287
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_flipq.c
289
int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode) -
sys/dev/pci/drm/i915/display/intel_flipq.c
290
intel_flipq_exec_time_lines(crtc_state);
sys/dev/pci/drm/i915/display/intel_flipq.c
297
intel_flipq_exec_time_lines(crtc_state));
sys/dev/pci/drm/i915/display/intel_flipq.c
313
void intel_flipq_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_flipq.c
315
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_flipq.c
316
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_flipq.h
23
void intel_flipq_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2517
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdcp.c
2533
_intel_hdcp_enable(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2567
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdcp.c
2626
_intel_hdcp_enable(state, encoder, crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_hdcp.c
2697
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2710
crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
sys/dev/pci/drm/i915/display/intel_hdcp.c
2717
if (drm_atomic_crtc_needs_modeset(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_hdcp.c
2735
crtc_state->mode_changed = true;
sys/dev/pci/drm/i915/display/intel_hdcp.h
39
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1000
intel_de_write(display, reg, crtc_state->infoframes.gcp);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1006
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1009
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1012
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_hdmi.c
1017
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1025
crtc_state->infoframes.gcp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1029
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1034
if (display->platform.g4x || !crtc_state->has_infoframe)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1037
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_hdmi.c
1041
if (crtc_state->pipe_bpp > 24)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1042
crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1045
if (gcp_default_phase_possible(crtc_state->pipe_bpp,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1046
&crtc_state->hw.adjusted_mode))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1047
crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1052
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1056
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1092
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1098
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1100
&crtc_state->infoframes.avi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1101
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1103
&crtc_state->infoframes.spd);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1104
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1106
&crtc_state->infoframes.hdmi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1111
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1115
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1141
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1147
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1149
&crtc_state->infoframes.avi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1150
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1152
&crtc_state->infoframes.spd);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1153
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1155
&crtc_state->infoframes.hdmi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1160
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1164
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1199
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1205
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1207
&crtc_state->infoframes.avi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1208
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1210
&crtc_state->infoframes.spd);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1211
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1213
&crtc_state->infoframes.hdmi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1217
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1222
crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1225
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_hdmi.c
1235
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1237
&crtc_state->infoframes.drm);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1242
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1247
crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1251
crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1264
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
sys/dev/pci/drm/i915/display/intel_hdmi.c
1270
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1272
&crtc_state->infoframes.avi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1273
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1275
&crtc_state->infoframes.spd);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1276
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1278
&crtc_state->infoframes.hdmi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1279
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1281
&crtc_state->infoframes.drm);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1843
static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
1845
return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2078
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2081
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2087
if (connector_state->base.crtc != crtc_state->uapi.crtc)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2091
crtc_state->sink_format))
sys/dev/pci/drm/i915/display/intel_hdmi.c
2098
static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2100
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2102
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2108
if (intel_hdmi_is_ycbcr420(crtc_state) &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
2114
return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2118
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2128
bpc = max(crtc_state->pipe_bpp / 3, 8);
sys/dev/pci/drm/i915/display/intel_hdmi.c
213
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2140
crtc_state->sink_format);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2142
if (hdmi_bpc_possible(crtc_state, bpc) &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
2145
crtc_state->has_hdmi_sink) == MODE_OK)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2153
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2158
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2164
bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2169
crtc_state->port_clock =
sys/dev/pci/drm/i915/display/intel_hdmi.c
2170
intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2177
crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2181
bpc, crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2186
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2192
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2201
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2206
return crtc_state->has_hdmi_sink &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
2215
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2222
if (!crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2232
intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2236
if (!crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2246
intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2248
return crtc_state->sink_format;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2252
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2258
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2263
crtc_state->sink_format =
sys/dev/pci/drm/i915/display/intel_hdmi.c
2264
intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2266
if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
2269
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2272
crtc_state->output_format = intel_hdmi_output_format(crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2273
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2275
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
sys/dev/pci/drm/i915/display/intel_hdmi.c
2276
!crtc_state->has_hdmi_sink ||
sys/dev/pci/drm/i915/display/intel_hdmi.c
2281
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
sys/dev/pci/drm/i915/display/intel_hdmi.c
2282
crtc_state->output_format = intel_hdmi_output_format(crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2283
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2289
static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
2291
return crtc_state->uapi.encoder_mask &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
2292
!is_power_of_2(crtc_state->uapi.encoder_mask);
sys/dev/pci/drm/i915/display/intel_hdmi.c
2315
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
2321
!intel_hdmi_is_cloned(crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
249
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
281
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
287
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
3158
intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
3180
int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_hdmi.c
3191
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
sys/dev/pci/drm/i915/display/intel_hdmi.c
3192
crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
sys/dev/pci/drm/i915/display/intel_hdmi.c
320
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
3247
slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
sys/dev/pci/drm/i915/display/intel_hdmi.c
325
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
356
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
362
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
398
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
403
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
430
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
436
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
470
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
475
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
506
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
512
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_hdmi.c
538
if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
539
!crtc_state->has_panel_replay && type == DP_SDP_VSC))
sys/dev/pci/drm/i915/display/intel_hdmi.c
550
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
554
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_hdmi.c
608
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_hdmi.c
615
val = dig_port->infoframes_enabled(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
651
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
659
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_hdmi.c
676
dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
sys/dev/pci/drm/i915/display/intel_hdmi.c
680
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
688
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_hdmi.c
692
dig_port->read_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
714
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
717
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
sys/dev/pci/drm/i915/display/intel_hdmi.c
719
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_hdmi.c
723
if (!crtc_state->has_infoframe)
sys/dev/pci/drm/i915/display/intel_hdmi.c
726
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_hdmi.c
734
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_hdmi.c
736
else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
sys/dev/pci/drm/i915/display/intel_hdmi.c
744
drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
sys/dev/pci/drm/i915/display/intel_hdmi.c
745
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
sys/dev/pci/drm/i915/display/intel_hdmi.c
747
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
sys/dev/pci/drm/i915/display/intel_hdmi.c
750
crtc_state->limited_color_range ?
sys/dev/pci/drm/i915/display/intel_hdmi.c
771
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
774
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.c
775
struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
sys/dev/pci/drm/i915/display/intel_hdmi.c
778
if (!crtc_state->has_infoframe)
sys/dev/pci/drm/i915/display/intel_hdmi.c
781
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_hdmi.c
803
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
807
&crtc_state->infoframes.hdmi.vendor.hdmi;
sys/dev/pci/drm/i915/display/intel_hdmi.c
812
if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
sys/dev/pci/drm/i915/display/intel_hdmi.c
815
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_hdmi.c
820
&crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_hdmi.c
833
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
837
struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
sys/dev/pci/drm/i915/display/intel_hdmi.c
843
if (!crtc_state->has_infoframe)
sys/dev/pci/drm/i915/display/intel_hdmi.c
849
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_hdmi.c
868
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
925
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
927
&crtc_state->infoframes.avi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
928
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
930
&crtc_state->infoframes.spd);
sys/dev/pci/drm/i915/display/intel_hdmi.c
931
intel_write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
933
&crtc_state->infoframes.hdmi);
sys/dev/pci/drm/i915/display/intel_hdmi.c
980
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.c
984
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_hdmi.c
987
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_hdmi.c
992
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.h
27
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
40
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.h
43
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_hdmi.h
45
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
48
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
51
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
53
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
59
int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
65
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_hdmi.h
69
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_link_bw.c
111
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_link_bw.c
117
crtc_state = intel_atomic_get_crtc_state(&state->base,
sys/dev/pci/drm/i915/display/intel_link_bw.c
119
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_link_bw.c
120
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_link_bw.c
122
if (crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_link_bw.c
123
link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
sys/dev/pci/drm/i915/display/intel_link_bw.c
131
link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);
sys/dev/pci/drm/i915/display/intel_link_bw.c
180
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_link_bw.c
182
int pipe_bpp = min(crtc_state->pipe_bpp,
sys/dev/pci/drm/i915/display/intel_link_bw.c
183
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
sys/dev/pci/drm/i915/display/intel_link_bw.c
190
crtc_state->pipe_bpp = pipe_bpp;
sys/dev/pci/drm/i915/display/intel_link_bw.c
62
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_link_bw.c
66
if (state->base.duplicated && crtc_state) {
sys/dev/pci/drm/i915/display/intel_link_bw.c
67
limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;
sys/dev/pci/drm/i915/display/intel_link_bw.c
68
if (crtc_state->fec_enable)
sys/dev/pci/drm/i915/display/intel_link_bw.h
30
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_load_detect.c
144
crtc_state = intel_atomic_get_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_load_detect.c
145
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_load_detect.c
146
ret = PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_load_detect.c
150
crtc_state->uapi.active = true;
sys/dev/pci/drm/i915/display/intel_load_detect.c
152
ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
sys/dev/pci/drm/i915/display/intel_load_detect.c
60
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_lspcon.c
494
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lspcon.c
515
hsw_write_infoframe(encoder, crtc_state, type, frame, len);
sys/dev/pci/drm/i915/display/intel_lspcon.c
528
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lspcon.c
534
hsw_read_infoframe(encoder, crtc_state, type,
sys/dev/pci/drm/i915/display/intel_lspcon.c
540
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lspcon.c
547
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_lspcon.c
576
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
sys/dev/pci/drm/i915/display/intel_lspcon.c
585
drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
sys/dev/pci/drm/i915/display/intel_lspcon.c
586
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
sys/dev/pci/drm/i915/display/intel_lspcon.c
588
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
sys/dev/pci/drm/i915/display/intel_lspcon.c
592
crtc_state->limited_color_range ?
sys/dev/pci/drm/i915/display/intel_lspcon.c
608
dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI,
sys/dev/pci/drm/i915/display/intel_lspcon.h
26
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lspcon.h
30
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lspcon.h
35
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lvds.c
123
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_lvds.c
129
crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
sys/dev/pci/drm/i915/display/intel_lvds.c
141
crtc_state->hw.adjusted_mode.flags |= flags;
sys/dev/pci/drm/i915/display/intel_lvds.c
144
crtc_state->gmch_pfit.lvds_border_bits =
sys/dev/pci/drm/i915/display/intel_lvds.c
151
crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
sys/dev/pci/drm/i915/display/intel_lvds.c
154
crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
sys/dev/pci/drm/i915/display/intel_lvds.c
240
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lvds.c
245
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_lvds.c
246
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_lvds.c
252
assert_dpll_disabled(display, crtc_state->intel_dpll);
sys/dev/pci/drm/i915/display/intel_lvds.c
272
temp |= crtc_state->gmch_pfit.lvds_border_bits;
sys/dev/pci/drm/i915/display/intel_lvds.c
302
if (crtc_state->dither && crtc_state->pipe_bpp == 18)
sys/dev/pci/drm/i915/display/intel_lvds.c
321
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lvds.c
336
intel_backlight_enable(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_lvds.c
418
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_lvds.c
424
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_lvds.c
425
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_lvds.c
436
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/intel_lvds.c
437
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
sys/dev/pci/drm/i915/display/intel_lvds.c
447
if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
sys/dev/pci/drm/i915/display/intel_lvds.c
450
crtc_state->pipe_bpp, lvds_bpp);
sys/dev/pci/drm/i915/display/intel_lvds.c
451
crtc_state->pipe_bpp = lvds_bpp;
sys/dev/pci/drm/i915/display/intel_lvds.c
454
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_lvds.c
455
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
sys/dev/pci/drm/i915/display/intel_lvds.c
470
ret = intel_pfit_compute_config(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
100
&crtc_state->intel_dpll->state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
162
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
166
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
167
intel_crtc_free_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
168
intel_crtc_state_reset(crtc_state, crtc);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
219
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
225
if (!is_trans_port_sync_mode(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
232
if (is_trans_port_sync_master(crtc_state))
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
233
master_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
235
master_transcoder = crtc_state->master_transcoder;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
312
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
315
conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
321
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
323
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
325
if (intel_crtc_is_joiner_secondary(crtc_state))
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
328
crtc_state->uapi.enable = crtc_state->hw.enable;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
329
crtc_state->uapi.active = crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
330
drm_WARN_ON(crtc_state->uapi.crtc->dev,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
331
drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
333
crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
334
crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
338
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
339
crtc_state->pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
340
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
341
crtc_state->post_csc_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
351
drm_WARN_ON(display->drm, crtc_state->post_csc_lut &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
352
crtc_state->pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
354
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
356
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
357
crtc_state->post_csc_lut ?:
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
358
crtc_state->pre_csc_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
361
drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
362
crtc_state->hw.degamma_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
363
drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
364
crtc_state->hw.gamma_lut);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
365
drm_property_replace_blob(&crtc_state->uapi.ctm,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
366
crtc_state->hw.ctm);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
44
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
443
static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
445
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
446
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
462
!crtc_state->hw.active &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
470
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
473
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
487
intel_color_commit_noarm(NULL, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
488
intel_color_commit_arm(NULL, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
491
if (!crtc_state->hw.active ||
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
492
intel_crtc_is_joiner_secondary(crtc_state))
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
51
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
547
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
550
intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
554
static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
556
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
569
crtc_state->hw.active &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
570
crtc_state->intel_dpll &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
571
crtc_state->port_clock == 0;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
579
struct intel_crtc_state *crtc_state = crtc ?
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
589
bool has_active_crtc = crtc_state &&
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
590
crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
592
if (crtc_state && has_bogus_dpll_config(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
615
if (crtc_state) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
629
encoder->disable(NULL, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
632
encoder->post_disable(NULL, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
665
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
672
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
674
intel_set_plane_visible(crtc_state, plane_state, visible);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
683
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
686
intel_plane_fixup_bitmasks(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
701
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
704
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
705
intel_crtc_free_hw_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
706
intel_crtc_state_reset(crtc_state, crtc);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
708
intel_crtc_get_pipe_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
710
crtc_state->hw.enable = crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
712
crtc->base.enabled = crtc_state->hw.enable;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
713
crtc->active = crtc_state->hw.active;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
718
str_enabled_disabled(crtc_state->hw.active));
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
724
struct intel_crtc_state *crtc_state = NULL;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
730
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
733
intel_encoder_get_config(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
736
if (crtc_state->joiner_pipes) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
740
WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
743
intel_crtc_joiner_secondary_pipes(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
76
intel_crtc_joiner_secondary_pipes(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
763
encoder->sync_state(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
776
struct intel_crtc_state *crtc_state = NULL;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
787
crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
789
if (crtc_state && crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
795
crtc_state->uapi.connector_mask |=
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
797
crtc_state->uapi.encoder_mask |=
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
806
connector->sync_state(connector, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
816
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
829
crtc_state->inherited = true;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
831
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
832
intel_crtc_update_active_timings(crtc_state,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
833
crtc_state->vrr.enable);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
835
intel_crtc_copy_hw_to_uapi_state(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
847
crtc_state->data_rate[plane->id] =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
848
4 * crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
854
if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
855
crtc_state->min_cdclk[plane->id] =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
856
DIV_ROUND_UP(crtc_state->pixel_rate, 2);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
858
crtc_state->min_cdclk[plane->id] =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
859
crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
864
crtc_state->min_cdclk[plane->id]);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
868
crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
887
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
899
crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
900
encoder->get_power_domains(encoder, crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
957
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
960
intel_sanitize_fifo_underrun_reporting(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
964
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
965
intel_dmc_enable_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
966
intel_crtc_vblank_on(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
97
if (crtc_state->intel_dpll)
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
99
crtc_state->intel_dpll,
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
993
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_modeset_setup.c
997
intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
27
static void intel_connector_verify_state(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
39
INTEL_DISPLAY_STATE_WARN(display, !crtc_state,
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
42
if (!crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
45
INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
58
INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
60
INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
76
const struct intel_crtc_state *crtc_state = NULL;
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
82
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
84
intel_connector_verify_state(crtc_state, new_conn_state);
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
91
static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
93
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
95
if (crtc_state->has_pch_encoder) {
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
96
int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
97
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_modeset_verify.c
98
int dotclock = crtc_state->hw.adjusted_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_overlay.c
827
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_overlay.c
831
if (crtc_state->gamma_enable &&
sys/dev/pci/drm/i915/display/intel_overlay.c
832
crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
sys/dev/pci/drm/i915/display/intel_overlay.c
834
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_overlay.c
976
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_overlay.c
985
if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src))
sys/dev/pci/drm/i915/display/intel_panel.c
491
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_panel.c
493
crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/intel_panel.c
495
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_panel.c
498
intel_panel_prepare(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_panel.c
584
void intel_panel_prepare(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_panel.h
56
void intel_panel_prepare(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pch_display.c
223
static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pch_display.c
226
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
227
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_pch_display.c
246
static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.c
248
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
249
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pch_display.c
255
assert_dpll_enabled(display, crtc_state->intel_dpll);
sys/dev/pci/drm/i915/display/intel_pch_display.c
271
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
282
val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
290
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
sys/dev/pci/drm/i915/display/intel_pch_display.c
299
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
sys/dev/pci/drm/i915/display/intel_pch_display.c
342
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_pch_display.c
350
ilk_fdi_pll_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
365
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_pch_display.c
373
intel_fdi_link_train(crtc, crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
385
if (crtc_state->intel_dpll ==
sys/dev/pci/drm/i915/display/intel_pch_display.c
402
intel_dpll_enable(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
406
if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_pch_display.c
407
intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
sys/dev/pci/drm/i915/display/intel_pch_display.c
408
intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
sys/dev/pci/drm/i915/display/intel_pch_display.c
410
ilk_pch_transcoder_set_timings(crtc_state, pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
416
intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_pch_display.c
418
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pch_display.c
437
port = intel_get_crtc_new_encoder(state, crtc_state)->port;
sys/dev/pci/drm/i915/display/intel_pch_display.c
444
ilk_enable_pch_transcoder(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
479
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.c
481
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
484
i9xx_crtc_clock_get(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
491
crtc_state->hw.adjusted_mode.crtc_clock =
sys/dev/pci/drm/i915/display/intel_pch_display.c
492
intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),
sys/dev/pci/drm/i915/display/intel_pch_display.c
493
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_pch_display.c
496
void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.c
498
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
499
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pch_display.c
509
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/intel_pch_display.c
512
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/pci/drm/i915/display/intel_pch_display.c
515
intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
sys/dev/pci/drm/i915/display/intel_pch_display.c
516
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_pch_display.c
532
crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
sys/dev/pci/drm/i915/display/intel_pch_display.c
533
pll = crtc_state->intel_dpll;
sys/dev/pci/drm/i915/display/intel_pch_display.c
536
&crtc_state->dpll_hw_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
539
tmp = crtc_state->dpll_hw_state.i9xx.dpll;
sys/dev/pci/drm/i915/display/intel_pch_display.c
540
crtc_state->pixel_multiplier =
sys/dev/pci/drm/i915/display/intel_pch_display.c
544
ilk_pch_clock_get(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
547
static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.c
549
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
550
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_pch_display.c
562
val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_pch_display.c
596
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_pch_display.c
601
lpt_program_iclkip(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
604
ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
sys/dev/pci/drm/i915/display/intel_pch_display.c
606
lpt_enable_pch_transcoder(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
619
void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.c
621
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.c
622
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pch_display.c
628
crtc_state->has_pch_encoder = true;
sys/dev/pci/drm/i915/display/intel_pch_display.c
631
crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
sys/dev/pci/drm/i915/display/intel_pch_display.c
634
intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
sys/dev/pci/drm/i915/display/intel_pch_display.c
635
&crtc_state->fdi_m_n);
sys/dev/pci/drm/i915/display/intel_pch_display.c
637
crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);
sys/dev/pci/drm/i915/display/intel_pch_display.h
31
void ilk_pch_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.h
37
void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_display.h
71
static inline void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_display.h
82
static inline void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
176
int lpt_iclkip(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
180
lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
186
void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
188
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
189
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
sys/dev/pci/drm/i915/display/intel_pch_refclk.h
15
void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_refclk.h
18
int lpt_iclkip(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pch_refclk.h
23
static inline void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pch_refclk.h
33
static inline int lpt_iclkip(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
108
static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
110
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
111
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
112
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
sys/dev/pci/drm/i915/display/intel_pfit.c
113
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
114
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
143
static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
145
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
146
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
148
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
161
static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
163
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
164
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
173
if (crtc_state->uapi.encoder_mask &&
sys/dev/pci/drm/i915/display/intel_pfit.c
174
!is_power_of_2(crtc_state->uapi.encoder_mask)) {
sys/dev/pci/drm/i915/display/intel_pfit.c
185
static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.c
188
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
19
static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
190
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
191
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
192
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
198
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_pfit.c
21
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
22
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
24
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
25
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
sys/dev/pci/drm/i915/display/intel_pfit.c
252
drm_rect_init(&crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/intel_pfit.c
254
crtc_state->pch_pfit.enabled = true;
sys/dev/pci/drm/i915/display/intel_pfit.c
263
ret = intel_pch_pfit_check_dst_window(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
267
ret = intel_pch_pfit_check_src_size(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
271
ret = intel_pch_pfit_check_scaling(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
275
ret = intel_pch_pfit_check_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
279
ret = intel_pch_pfit_check_cloning(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
342
static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.c
346
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
347
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
348
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
363
static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.c
367
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
368
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
369
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
419
static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
421
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
422
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
424
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
451
static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.c
454
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
455
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
457
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_pfit.c
458
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
459
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
498
i965_scale_aspect(crtc_state, &pfit_control);
sys/dev/pci/drm/i915/display/intel_pfit.c
500
i9xx_scale_aspect(crtc_state, &pfit_control,
sys/dev/pci/drm/i915/display/intel_pfit.c
537
if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)
sys/dev/pci/drm/i915/display/intel_pfit.c
540
crtc_state->gmch_pfit.control = pfit_control;
sys/dev/pci/drm/i915/display/intel_pfit.c
541
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
sys/dev/pci/drm/i915/display/intel_pfit.c
542
crtc_state->gmch_pfit.lvds_border_bits = border;
sys/dev/pci/drm/i915/display/intel_pfit.c
547
return intel_gmch_pfit_check_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
560
int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.c
563
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
566
return gmch_panel_fitting(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
568
return pch_panel_fitting(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
571
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
573
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
574
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
575
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
sys/dev/pci/drm/i915/display/intel_pfit.c
582
if (!crtc_state->pch_pfit.enabled)
sys/dev/pci/drm/i915/display/intel_pfit.c
619
void ilk_pfit_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
621
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
622
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
635
crtc_state->pch_pfit.enabled = true;
sys/dev/pci/drm/i915/display/intel_pfit.c
640
drm_rect_init(&crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/intel_pfit.c
654
void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
656
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
657
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
659
if (!crtc_state->gmch_pfit.control)
sys/dev/pci/drm/i915/display/intel_pfit.c
668
assert_transcoder_disabled(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_pfit.c
671
crtc_state->gmch_pfit.pgm_ratios);
sys/dev/pci/drm/i915/display/intel_pfit.c
673
crtc_state->gmch_pfit.control);
sys/dev/pci/drm/i915/display/intel_pfit.c
70
static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
705
void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pfit.c
707
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
708
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
72
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.c
728
crtc_state->gmch_pfit.control = tmp;
sys/dev/pci/drm/i915/display/intel_pfit.c
729
crtc_state->gmch_pfit.pgm_ratios =
sys/dev/pci/drm/i915/display/intel_pfit.c
73
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pfit.c
74
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.c
75
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_pfit.h
16
int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_pfit.h
18
void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.h
20
void ilk_pfit_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.h
21
void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pfit.h
23
void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_plane.c
1006
const struct drm_rect *clip = &crtc_state->pipe_src;
sys/dev/pci/drm/i915/display/intel_plane.c
1328
struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);
sys/dev/pci/drm/i915/display/intel_plane.c
1336
if (crtc_state->enable_psr2_sel_fetch) {
sys/dev/pci/drm/i915/display/intel_plane.c
1338
intel_psr2_panic_force_full_update(display, crtc_state);
sys/dev/pci/drm/i915/display/intel_plane.c
1463
static void link_nv12_planes(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
1480
crtc_state->enabled_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1481
crtc_state->active_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1482
crtc_state->update_planes |= BIT(y_plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1484
crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];
sys/dev/pci/drm/i915/display/intel_plane.c
1485
crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];
sys/dev/pci/drm/i915/display/intel_plane.c
1500
static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
1518
crtc_state->enabled_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1519
crtc_state->active_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1520
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
1521
crtc_state->data_rate[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
1522
crtc_state->rel_data_rate[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
1529
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_plane.c
1546
unlink_nv12_plane(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_plane.c
1549
if (!crtc_state->nv12_planes)
sys/dev/pci/drm/i915/display/intel_plane.c
1559
if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
sys/dev/pci/drm/i915/display/intel_plane.c
1566
if (crtc_state->active_planes & BIT(y_plane->id))
sys/dev/pci/drm/i915/display/intel_plane.c
1580
hweight8(crtc_state->nv12_planes));
sys/dev/pci/drm/i915/display/intel_plane.c
1584
link_nv12_planes(crtc_state, plane_state, y_plane_state);
sys/dev/pci/drm/i915/display/intel_plane.c
1691
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_plane.c
1695
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/intel_plane.c
1698
ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state));
sys/dev/pci/drm/i915/display/intel_plane.c
221
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
238
crtc_state->pixel_rate);
sys/dev/pci/drm/i915/display/intel_plane.c
241
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
250
return intel_plane_pixel_rate(crtc_state, plane_state) *
sys/dev/pci/drm/i915/display/intel_plane.c
255
intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
285
skl_plane_relative_data_rate(crtc_state, plane, width, height,
sys/dev/pci/drm/i915/display/intel_plane.c
424
static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
427
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
432
unlink_nv12_plane(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_plane.c
434
crtc_state->active_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
435
crtc_state->scaled_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
436
crtc_state->nv12_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
437
crtc_state->c8_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
438
crtc_state->async_flip_planes &= ~BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_plane.c
439
crtc_state->data_rate[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
440
crtc_state->data_rate_y[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
441
crtc_state->rel_data_rate[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
442
crtc_state->rel_data_rate_y[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
443
crtc_state->min_cdclk[plane->id] = 0;
sys/dev/pci/drm/i915/display/intel_plane.c
803
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_plane.c
819
if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
sys/dev/pci/drm/i915/display/intel_plane.c
821
skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
sys/dev/pci/drm/i915/display/intel_plane.c
826
ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/intel_plane.c
827
ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/intel_plane.c
840
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
843
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_plane.c
851
plane->update_noarm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_plane.c
856
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
860
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_plane.c
863
plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
sys/dev/pci/drm/i915/display/intel_plane.c
868
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.c
871
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_plane.c
873
if (crtc_state->do_async_flip && plane->async_flip) {
sys/dev/pci/drm/i915/display/intel_plane.c
874
intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);
sys/dev/pci/drm/i915/display/intel_plane.c
879
plane->update_arm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_plane.c
884
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_plane.c
886
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_plane.c
889
plane->disable_arm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/intel_plane.c
997
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
29
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
32
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
42
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
47
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
51
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
55
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_plane.h
69
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
76
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane.h
80
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_plane_initial.c
37
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_plane_initial.c
40
if (!crtc_state->uapi.active)
sys/dev/pci/drm/i915/display/intel_pmdemand.c
210
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_pmdemand.c
216
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_pmdemand.c
218
crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_pmdemand.c
220
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_pps.c
1281
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pps.c
1285
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_pps.c
1327
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_pps.h
52
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_pps.h
54
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
1131
static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1133
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_psr.c
1137
drm_mode_vrefresh(&crtc_state->hw.adjusted_mode));
sys/dev/pci/drm/i915/display/intel_psr.c
1194
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1198
enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
1209
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1212
const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_psr.c
1227
if (crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_psr.c
1233
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_psr.c
1245
intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
sys/dev/pci/drm/i915/display/intel_psr.c
1250
crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
sys/dev/pci/drm/i915/display/intel_psr.c
1254
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1265
return crtc_state->enable_psr2_sel_fetch = true;
sys/dev/pci/drm/i915/display/intel_psr.c
1269
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1272
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_psr.c
1273
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
sys/dev/pci/drm/i915/display/intel_psr.c
1274
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_psr.c
1285
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_psr.c
1303
if (crtc_state->dsc.compression_enable &&
sys/dev/pci/drm/i915/display/intel_psr.c
1307
crtc_state->su_y_granularity = y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
1312
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1315
const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_psr.c
1322
req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000);
sys/dev/pci/drm/i915/display/intel_psr.c
1331
crtc_state->req_psr2_sdp_prior_scanline = true;
sys/dev/pci/drm/i915/display/intel_psr.c
1369
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
1373
int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
sys/dev/pci/drm/i915/display/intel_psr.c
1374
crtc_state->hw.adjusted_mode.crtc_vblank_start;
sys/dev/pci/drm/i915/display/intel_psr.c
1384
if (crtc_state->req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
1395
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
1400
if (!intel_alpm_compute_params(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1406
if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1416
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1419
int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
sys/dev/pci/drm/i915/display/intel_psr.c
1420
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_psr.c
1446
if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1449
transcoder_name(crtc_state->cpu_transcoder));
sys/dev/pci/drm/i915/display/intel_psr.c
1458
if (crtc_state->dsc.compression_enable &&
sys/dev/pci/drm/i915/display/intel_psr.c
1468
max_bpp = crtc_state->pipe_bpp;
sys/dev/pci/drm/i915/display/intel_psr.c
1483
if (crtc_state->pipe_bpp > max_bpp) {
sys/dev/pci/drm/i915/display/intel_psr.c
1486
crtc_state->pipe_bpp, max_bpp);
sys/dev/pci/drm/i915/display/intel_psr.c
1491
if (crtc_state->vrr.enable &&
sys/dev/pci/drm/i915/display/intel_psr.c
1498
if (!alpm_config_valid(intel_dp, crtc_state, false))
sys/dev/pci/drm/i915/display/intel_psr.c
1501
if (!crtc_state->enable_psr2_sel_fetch &&
sys/dev/pci/drm/i915/display/intel_psr.c
1510
tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
1516
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1521
!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
sys/dev/pci/drm/i915/display/intel_psr.c
1534
if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
sys/dev/pci/drm/i915/display/intel_psr.c
1537
if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1543
if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 ||
sys/dev/pci/drm/i915/display/intel_psr.c
1547
if (crtc_state->crc_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1553
if (!psr2_granularity_check(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1559
crtc_state->enable_psr2_su_region_et =
sys/dev/pci/drm/i915/display/intel_psr.c
1560
psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
sys/dev/pci/drm/i915/display/intel_psr.c
1565
crtc_state->enable_psr2_sel_fetch = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1570
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1573
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_psr.c
1582
if (crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_psr.c
1588
crtc_state->entry_setup_frames = entry_setup_frames;
sys/dev/pci/drm/i915/display/intel_psr.c
1600
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
1616
if (crtc_state->crc_enabled) {
sys/dev/pci/drm/i915/display/intel_psr.c
1627
if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
sys/dev/pci/drm/i915/display/intel_psr.c
1628
to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
sys/dev/pci/drm/i915/display/intel_psr.c
1632
if (intel_dp_is_uhbr(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1649
if (!alpm_config_valid(intel_dp, crtc_state, true))
sys/dev/pci/drm/i915/display/intel_psr.c
1656
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1660
return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
sys/dev/pci/drm/i915/display/intel_psr.c
1661
!crtc_state->has_sel_update);
sys/dev/pci/drm/i915/display/intel_psr.c
1665
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
1669
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_psr.c
1670
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
sys/dev/pci/drm/i915/display/intel_psr.c
1696
if (crtc_state->joiner_pipes) {
sys/dev/pci/drm/i915/display/intel_psr.c
1702
crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
sys/dev/pci/drm/i915/display/intel_psr.c
1703
crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
1706
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
sys/dev/pci/drm/i915/display/intel_psr.c
1707
_psr_compute_config(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
1709
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
1712
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
1715
if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
1716
crtc_state->has_psr = false;
sys/dev/pci/drm/i915/display/intel_psr.c
1727
if (crtc_state->has_panel_replay)
sys/dev/pci/drm/i915/display/intel_psr.c
1736
crtc_state->active_non_psr_pipes = active_pipes &
sys/dev/pci/drm/i915/display/intel_psr.c
1737
~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
sys/dev/pci/drm/i915/display/intel_psr.c
1828
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1835
if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
1840
crtc_state->hw.adjusted_mode.crtc_vblank_start !=
sys/dev/pci/drm/i915/display/intel_psr.c
1841
crtc_state->hw.adjusted_mode.crtc_vdisplay)
sys/dev/pci/drm/i915/display/intel_psr.c
1853
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
1935
wm_optimization_wa(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
1972
intel_alpm_configure(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2006
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2014
intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
sys/dev/pci/drm/i915/display/intel_psr.c
2015
intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
sys/dev/pci/drm/i915/display/intel_psr.c
2017
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
sys/dev/pci/drm/i915/display/intel_psr.c
2018
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2020
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
sys/dev/pci/drm/i915/display/intel_psr.c
2022
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
sys/dev/pci/drm/i915/display/intel_psr.c
2023
intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
sys/dev/pci/drm/i915/display/intel_psr.c
2024
intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
sys/dev/pci/drm/i915/display/intel_psr.c
2027
crtc_state->req_psr2_sdp_prior_scanline;
sys/dev/pci/drm/i915/display/intel_psr.c
2028
intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
sys/dev/pci/drm/i915/display/intel_psr.c
2029
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
sys/dev/pci/drm/i915/display/intel_psr.c
2030
intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
sys/dev/pci/drm/i915/display/intel_psr.c
2054
intel_psr_enable_sink(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2059
intel_psr_enable_source(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
218
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2318
bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
232
return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
sys/dev/pci/drm/i915/display/intel_psr.c
2320
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
2321
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2359
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_psr.c
2363
if (crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
2374
int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2376
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2378
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
2382
if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
sys/dev/pci/drm/i915/display/intel_psr.c
2404
if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||
sys/dev/pci/drm/i915/display/intel_psr.c
2405
crtc_state->has_sel_update))
sys/dev/pci/drm/i915/display/intel_psr.c
2407
else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||
sys/dev/pci/drm/i915/display/intel_psr.c
2408
intel_crtc_has_type(crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
2463
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2465
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2466
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
2467
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2470
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_psr.c
2474
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_psr.c
2487
crtc_state->psr2_man_track_ctl);
sys/dev/pci/drm/i915/display/intel_psr.c
2489
if (!crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_psr.c
2493
crtc_state->pipe_srcsz_early_tpt);
sys/dev/pci/drm/i915/display/intel_psr.c
2495
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_psr.c
2498
intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
2499
drm_rect_height(&crtc_state->psr2_su_area));
sys/dev/pci/drm/i915/display/intel_psr.c
2502
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
2505
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2516
if (crtc_state->psr2_su_area.y1 == -1)
sys/dev/pci/drm/i915/display/intel_psr.c
2520
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);
sys/dev/pci/drm/i915/display/intel_psr.c
2521
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);
sys/dev/pci/drm/i915/display/intel_psr.c
2523
drm_WARN_ON(crtc_state->uapi.crtc->dev,
sys/dev/pci/drm/i915/display/intel_psr.c
2524
crtc_state->psr2_su_area.y1 % 4 ||
sys/dev/pci/drm/i915/display/intel_psr.c
2525
crtc_state->psr2_su_area.y2 % 4);
sys/dev/pci/drm/i915/display/intel_psr.c
2528
crtc_state->psr2_su_area.y1 / 4 + 1);
sys/dev/pci/drm/i915/display/intel_psr.c
2530
crtc_state->psr2_su_area.y2 / 4 + 1);
sys/dev/pci/drm/i915/display/intel_psr.c
2533
crtc_state->psr2_man_track_ctl = val;
sys/dev/pci/drm/i915/display/intel_psr.c
2536
static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.c
2541
if (!crtc_state->enable_psr2_su_region_et || full_update)
sys/dev/pci/drm/i915/display/intel_psr.c
2544
width = drm_rect_width(&crtc_state->psr2_su_area);
sys/dev/pci/drm/i915/display/intel_psr.c
2545
height = drm_rect_height(&crtc_state->psr2_su_area);
sys/dev/pci/drm/i915/display/intel_psr.c
2570
static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2572
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2573
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_psr.c
2578
if (crtc_state->dsc.compression_enable &&
sys/dev/pci/drm/i915/display/intel_psr.c
2582
y_alignment = crtc_state->su_y_granularity;
sys/dev/pci/drm/i915/display/intel_psr.c
2584
if (crtc_state->psr2_su_area.y1 % y_alignment) {
sys/dev/pci/drm/i915/display/intel_psr.c
2585
crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
sys/dev/pci/drm/i915/display/intel_psr.c
2589
if (crtc_state->psr2_su_area.y2 % y_alignment) {
sys/dev/pci/drm/i915/display/intel_psr.c
2590
crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
sys/dev/pci/drm/i915/display/intel_psr.c
2607
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
2612
if (!crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_psr.c
2618
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
sys/dev/pci/drm/i915/display/intel_psr.c
2627
inter = crtc_state->psr2_su_area;
sys/dev/pci/drm/i915/display/intel_psr.c
2631
clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,
sys/dev/pci/drm/i915/display/intel_psr.c
2632
&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2664
static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2666
if (crtc_state->scaler_state.scaler_id >= 0)
sys/dev/pci/drm/i915/display/intel_psr.c
2673
static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2675
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2679
if (crtc_state->psr2_su_area.y1 != 0 ||
sys/dev/pci/drm/i915/display/intel_psr.c
2680
crtc_state->psr2_su_area.y2 != 0)
sys/dev/pci/drm/i915/display/intel_psr.c
2683
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
sys/dev/pci/drm/i915/display/intel_psr.c
2684
hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546;
sys/dev/pci/drm/i915/display/intel_psr.c
2686
hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273;
sys/dev/pci/drm/i915/display/intel_psr.c
2688
if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit)
sys/dev/pci/drm/i915/display/intel_psr.c
2692
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_psr.c
2698
crtc_state->psr2_su_area.y2++;
sys/dev/pci/drm/i915/display/intel_psr.c
2705
intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2707
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2710
if (!crtc_state->has_panel_replay &&
sys/dev/pci/drm/i915/display/intel_psr.c
2713
crtc_state->splitter.enable)
sys/dev/pci/drm/i915/display/intel_psr.c
2714
crtc_state->psr2_su_area.y1 = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2718
intel_psr_apply_pr_link_on_su_wa(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2725
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
2731
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/intel_psr.c
2734
if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
2739
crtc_state->psr2_su_area.x1 = 0;
sys/dev/pci/drm/i915/display/intel_psr.c
2740
crtc_state->psr2_su_area.y1 = -1;
sys/dev/pci/drm/i915/display/intel_psr.c
2741
crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2742
crtc_state->psr2_su_area.y2 = -1;
sys/dev/pci/drm/i915/display/intel_psr.c
2755
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
sys/dev/pci/drm/i915/display/intel_psr.c
2778
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
sys/dev/pci/drm/i915/display/intel_psr.c
2779
&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2785
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
sys/dev/pci/drm/i915/display/intel_psr.c
2786
&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2793
clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
sys/dev/pci/drm/i915/display/intel_psr.c
2794
&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2810
clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2819
if (crtc_state->psr2_su_area.y1 == -1) {
sys/dev/pci/drm/i915/display/intel_psr.c
2829
intel_psr_apply_su_area_workarounds(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2847
su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
2871
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
sys/dev/pci/drm/i915/display/intel_psr.c
2875
inter = crtc_state->psr2_su_area;
sys/dev/pci/drm/i915/display/intel_psr.c
2885
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_psr.c
2898
crtc_state->update_planes |= BIT(plane->id);
sys/dev/pci/drm/i915/display/intel_psr.c
2915
crtc_state->update_planes |= BIT(linked->id);
sys/dev/pci/drm/i915/display/intel_psr.c
2921
clip_area_update(&crtc_state->psr2_su_area, &crtc_state->pipe_src,
sys/dev/pci/drm/i915/display/intel_psr.c
2922
&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/intel_psr.c
2924
psr2_man_trk_ctl_calc(crtc_state, full_update);
sys/dev/pci/drm/i915/display/intel_psr.c
2925
crtc_state->pipe_srcsz_early_tpt =
sys/dev/pci/drm/i915/display/intel_psr.c
2926
psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
sys/dev/pci/drm/i915/display/intel_psr.c
2931
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
2933
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
2934
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_psr.c
2944
if (!crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_psr.c
3000
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_psr.c
3004
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
3008
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_psr.c
3016
psr->enabled && !crtc_state->active_planes);
sys/dev/pci/drm/i915/display/intel_psr.c
3019
keep_disabled |= !crtc_state->active_planes;
sys/dev/pci/drm/i915/display/intel_psr.c
3023
crtc_state->wm_level_disabled;
sys/dev/pci/drm/i915/display/intel_psr.c
3026
intel_psr_enable_locked(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
3027
else if (psr->enabled && !crtc_state->wm_level_disabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3029
wm_optimization_wa(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
3032
if (crtc_state->crc_enabled && psr->enabled)
sys/dev/pci/drm/i915/display/intel_psr.c
3201
struct drm_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_psr.c
3215
crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
sys/dev/pci/drm/i915/display/intel_psr.c
3216
if (IS_ERR(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_psr.c
3217
err = PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
3222
crtc_state->mode_changed = true;
sys/dev/pci/drm/i915/display/intel_psr.c
3768
void intel_psr_lock(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
3770
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
3773
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
3777
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_psr.c
3791
void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
3793
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
3796
if (!crtc_state->has_psr)
sys/dev/pci/drm/i915/display/intel_psr.c
3800
crtc_state->uapi.encoder_mask) {
sys/dev/pci/drm/i915/display/intel_psr.c
4352
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
4358
return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
sys/dev/pci/drm/i915/display/intel_psr.c
4359
crtc_state->has_panel_replay);
sys/dev/pci/drm/i915/display/intel_psr.c
4363
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
4365
return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
sys/dev/pci/drm/i915/display/intel_psr.c
747
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
756
if (crtc_state->has_sel_update)
sys/dev/pci/drm/i915/display/intel_psr.c
759
if (crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_psr.c
762
if (crtc_state->req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
773
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
778
if (crtc_state->has_sel_update) {
sys/dev/pci/drm/i915/display/intel_psr.c
788
if (crtc_state->req_psr2_sdp_prior_scanline)
sys/dev/pci/drm/i915/display/intel_psr.c
791
if (crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/intel_psr.c
803
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_psr.c
805
intel_alpm_enable_sink(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.c
807
crtc_state->has_panel_replay ?
sys/dev/pci/drm/i915/display/intel_psr.c
808
_panel_replay_enable_sink(intel_dp, crtc_state) :
sys/dev/pci/drm/i915/display/intel_psr.c
809
_psr_enable_sink(intel_dp, crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
30
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
48
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_psr.h
61
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
63
struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
66
bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
75
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
76
void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
80
int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
83
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_psr.h
85
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1099
struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1103
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1105
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1108
if (!crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1111
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_sdvo.c
1123
crtc_state->limited_color_range ?
sys/dev/pci/drm/i915/display/intel_sdvo.c
1135
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1139
const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1142
if ((crtc_state->infoframes.enable &
sys/dev/pci/drm/i915/display/intel_sdvo.c
1160
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1164
union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1168
if (!crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1180
crtc_state->infoframes.enable |=
sys/dev/pci/drm/i915/display/intel_sdvo.c
1196
struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1202
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1212
crtc_state->eld, sizeof(crtc_state->eld));
sys/dev/pci/drm/i915/display/intel_sdvo.c
1326
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1334
return intel_hdmi_limited_color_range(crtc_state, conn_state);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1338
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1347
if (!crtc_state->has_hdmi_sink)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1524
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1528
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1529
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1534
const struct drm_display_mode *mode = &crtc_state->hw.mode;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1580
if (crtc_state->has_hdmi_sink) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1583
crtc_state->limited_color_range ?
sys/dev/pci/drm/i915/display/intel_sdvo.c
1586
intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
sys/dev/pci/drm/i915/display/intel_sdvo.c
1606
switch (crtc_state->pixel_multiplier) {
sys/dev/pci/drm/i915/display/intel_sdvo.c
1645
sdvox |= (crtc_state->pixel_multiplier - 1)
sys/dev/pci/drm/i915/display/intel_sdvo.c
1815
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sdvo.c
1819
const u8 *eld = crtc_state->eld;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1821
if (!crtc_state->has_audio)
sys/dev/pci/drm/i915/display/intel_sdvo.c
2444
struct drm_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_sdvo.c
2447
crtc_state->connectors_changed = true;
sys/dev/pci/drm/i915/display/intel_sdvo.c
2529
struct drm_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/intel_sdvo.c
2533
crtc_state->connectors_changed = true;
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1776
intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1779
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1781
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1783
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1791
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1797
tables = intel_mpllb_tables_get(crtc_state, encoder);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1802
if (crtc_state->port_clock == tables[i]->clock) {
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1803
crtc_state->dpll_hw_state.mpllb = *tables[i];
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1809
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1810
intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb,
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1811
crtc_state->port_clock);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1820
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1823
const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
sys/dev/pci/drm/i915/display/intel_snps_phy.c
68
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_snps_phy.c
75
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
sys/dev/pci/drm/i915/display/intel_snps_phy.c
80
int level = intel_ddi_level(encoder, crtc_state, ln);
sys/dev/pci/drm/i915/display/intel_snps_phy.h
23
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_snps_phy.h
26
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_snps_phy.h
34
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_sprite.c
1002
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_sprite.c
1005
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_sprite.c
1139
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1169
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1179
dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_sprite.c
1210
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
1273
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1282
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_sprite.c
1339
g4x_sprite_check(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1357
ret = intel_plane_check_clipping(plane_state, crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1373
ret = g4x_sprite_check_scaling(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/intel_sprite.c
1403
vlv_sprite_check(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
1412
ret = intel_plane_check_clipping(plane_state, crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
179
vlv_plane_ratio(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
183
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_sprite.c
237
int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
250
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_sprite.c
252
vlv_plane_ratio(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/intel_sprite.c
257
static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
261
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_sprite.c
368
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
390
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
401
sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_sprite.c
437
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
482
static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
486
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_sprite.c
519
static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
546
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
559
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_sprite.c
561
ivb_plane_ratio(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/intel_sprite.c
566
static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
579
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_sprite.c
585
ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/intel_sprite.c
587
ivb_plane_ratio(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/intel_sprite.c
596
static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
600
u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
sys/dev/pci/drm/i915/display/intel_sprite.c
629
int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
632
unsigned int pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_sprite.c
635
hsw_plane_ratio(crtc_state, plane_state, &num, &den);
sys/dev/pci/drm/i915/display/intel_sprite.c
640
static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
644
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/intel_sprite.c
647
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/intel_sprite.c
791
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
822
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
832
sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/intel_sprite.c
867
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.c
913
static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.c
927
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/intel_sprite.c
998
static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_sprite.h
22
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.h
24
int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_sprite.h
26
int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_tc.c
1636
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_tc.c
1646
} else if (crtc_state && crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/intel_tc.c
1647
pll_type = intel_ddi_port_pll_type(&dig_port->base, crtc_state);
sys/dev/pci/drm/i915/display/intel_tc.c
1672
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_tc.c
1680
if (!tc_port_has_active_streams(tc, crtc_state)) {
sys/dev/pci/drm/i915/display/intel_tc.c
1777
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_tc.c
1779
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/intel_tc.c
1780
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/intel_tc.c
1781
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/intel_tc.c
1783
crtc_state->uapi.connectors_changed = true;
sys/dev/pci/drm/i915/display/intel_tc.h
99
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
198
int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vblank.c
200
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
232
return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ? 2 : 1;
sys/dev/pci/drm/i915/display/intel_vblank.c
523
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vblank.c
526
drm_mode_init(mode, &crtc_state->hw.adjusted_mode);
sys/dev/pci/drm/i915/display/intel_vblank.c
532
mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
533
mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
534
mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
535
*vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
538
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vblank.c
541
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
542
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vblank.c
543
u8 mode_flags = crtc_state->mode_flags;
sys/dev/pci/drm/i915/display/intel_vblank.c
549
crtc_state, vrr_enable);
sys/dev/pci/drm/i915/display/intel_vblank.c
577
crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
659
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/intel_vblank.c
670
crtc_state = pre_commit_crtc_state(old_crtc_state, new_crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
672
adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_vblank.c
679
if (intel_vrr_is_push_sent(crtc_state))
sys/dev/pci/drm/i915/display/intel_vblank.c
680
evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
682
evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.c
684
vblank_delay = intel_vrr_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vblank.h
43
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vblank.h
45
int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1003
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1005
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1006
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1007
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vdsc.c
1012
if (!intel_dsc_source_support(crtc_state))
sys/dev/pci/drm/i915/display/intel_vdsc.c
1024
crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
sys/dev/pci/drm/i915/display/intel_vdsc.c
1025
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1029
crtc_state->dsc.num_streams = 3;
sys/dev/pci/drm/i915/display/intel_vdsc.c
1031
crtc_state->dsc.num_streams = 2;
sys/dev/pci/drm/i915/display/intel_vdsc.c
1033
crtc_state->dsc.num_streams = 1;
sys/dev/pci/drm/i915/display/intel_vdsc.c
1035
intel_dsc_get_pps_config(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1041
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1045
FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
sys/dev/pci/drm/i915/display/intel_vdsc.c
1046
crtc_state->dsc.slice_count,
sys/dev/pci/drm/i915/display/intel_vdsc.c
1047
crtc_state->dsc.num_streams);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1051
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1053
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1056
intel_vdsc_dump_state(p, indent, crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1057
drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1060
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1062
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1063
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1066
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
1076
min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1078
if (crtc_state->joiner_pipes) {
sys/dev/pci/drm/i915/display/intel_vdsc.c
1079
int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
sys/dev/pci/drm/i915/display/intel_vdsc.c
1095
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
sys/dev/pci/drm/i915/display/intel_vdsc.c
24
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
26
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
263
static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
265
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
269
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI);
sys/dev/pci/drm/i915/display/intel_vdsc.c
27
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vdsc.c
401
static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
403
return crtc_state->dsc.num_streams;
sys/dev/pci/drm/i915/display/intel_vdsc.c
406
int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
408
int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
409
int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
416
static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
sys/dev/pci/drm/i915/display/intel_vdsc.c
419
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
420
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vdsc.c
436
static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vdsc.c
439
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
443
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
448
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
sys/dev/pci/drm/i915/display/intel_vdsc.c
454
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
456
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
457
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
458
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
459
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vdsc.c
465
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
466
int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
488
intel_dsc_pps_write(crtc_state, 0, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
492
intel_dsc_pps_write(crtc_state, 1, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
497
intel_dsc_pps_write(crtc_state, 2, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
502
intel_dsc_pps_write(crtc_state, 3, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
507
intel_dsc_pps_write(crtc_state, 4, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
512
intel_dsc_pps_write(crtc_state, 5, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
519
intel_dsc_pps_write(crtc_state, 6, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
524
intel_dsc_pps_write(crtc_state, 7, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
529
intel_dsc_pps_write(crtc_state, 8, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
534
intel_dsc_pps_write(crtc_state, 9, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
541
intel_dsc_pps_write(crtc_state, 10, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
549
intel_dsc_pps_write(crtc_state, 16, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
554
intel_dsc_pps_write(crtc_state, 17, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
559
intel_dsc_pps_write(crtc_state, 18, pps_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
712
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
714
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
720
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
734
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
737
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
740
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
749
dig_port->write_infoframe(encoder, crtc_state,
sys/dev/pci/drm/i915/display/intel_vdsc.c
755
const struct intel_crtc_state *crtc_state, int su_lines)
sys/dev/pci/drm/i915/display/intel_vdsc.c
757
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
758
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
759
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
761
int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
789
void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
791
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
792
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
795
if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
sys/dev/pci/drm/i915/display/intel_vdsc.c
796
if (intel_crtc_is_bigjoiner_secondary(crtc_state))
sys/dev/pci/drm/i915/display/intel_vdsc.c
801
intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
sys/dev/pci/drm/i915/display/intel_vdsc.c
806
void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
808
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
809
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vdsc.c
812
int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
814
if (!crtc_state->dsc.compression_enable)
sys/dev/pci/drm/i915/display/intel_vdsc.c
817
intel_dsc_pps_configure(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
830
if (crtc_state->joiner_pipes) {
sys/dev/pci/drm/i915/display/intel_vdsc.c
831
if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
sys/dev/pci/drm/i915/display/intel_vdsc.c
834
if (intel_crtc_is_ultrajoiner_primary(crtc_state))
sys/dev/pci/drm/i915/display/intel_vdsc.c
839
if (intel_crtc_is_bigjoiner_primary(crtc_state))
sys/dev/pci/drm/i915/display/intel_vdsc.c
842
intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
843
intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
sys/dev/pci/drm/i915/display/intel_vdsc.c
859
static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
sys/dev/pci/drm/i915/display/intel_vdsc.c
862
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
867
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
872
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
sys/dev/pci/drm/i915/display/intel_vdsc.c
888
static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
sys/dev/pci/drm/i915/display/intel_vdsc.c
890
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
894
val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
sys/dev/pci/drm/i915/display/intel_vdsc.c
900
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vdsc.c
902
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
903
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
sys/dev/pci/drm/i915/display/intel_vdsc.c
904
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.c
908
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
sys/dev/pci/drm/i915/display/intel_vdsc.c
920
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
sys/dev/pci/drm/i915/display/intel_vdsc.c
927
crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
sys/dev/pci/drm/i915/display/intel_vdsc.c
930
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
sys/dev/pci/drm/i915/display/intel_vdsc.c
936
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
sys/dev/pci/drm/i915/display/intel_vdsc.c
942
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
sys/dev/pci/drm/i915/display/intel_vdsc.c
948
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
sys/dev/pci/drm/i915/display/intel_vdsc.c
954
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
sys/dev/pci/drm/i915/display/intel_vdsc.c
962
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
sys/dev/pci/drm/i915/display/intel_vdsc.c
968
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
sys/dev/pci/drm/i915/display/intel_vdsc.c
974
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
sys/dev/pci/drm/i915/display/intel_vdsc.c
979
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
sys/dev/pci/drm/i915/display/intel_vdsc.c
985
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
sys/dev/pci/drm/i915/display/intel_vdsc.c
991
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
sys/dev/pci/drm/i915/display/intel_vdsc.c
996
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
sys/dev/pci/drm/i915/display/intel_vdsc.h
19
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
20
void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
21
void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
22
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
24
void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
28
int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
30
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
32
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
34
const struct intel_crtc_state *crtc_state, int su_lines);
sys/dev/pci/drm/i915/display/intel_vdsc.h
36
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vdsc.h
37
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
101
int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
103
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
105
return intel_vrr_real_vblank_delay(crtc_state) +
sys/dev/pci/drm/i915/display/intel_vrr.c
115
static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
117
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
119
return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
sys/dev/pci/drm/i915/display/intel_vrr.c
138
static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
140
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
143
return crtc_state->vrr.guardband;
sys/dev/pci/drm/i915/display/intel_vrr.c
146
return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
sys/dev/pci/drm/i915/display/intel_vrr.c
149
int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
151
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
155
return intel_vrr_vmin_flipline(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
157
return intel_vrr_vmin_flipline(crtc_state) +
sys/dev/pci/drm/i915/display/intel_vrr.c
158
intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
161
int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
163
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
166
return crtc_state->vrr.vmax;
sys/dev/pci/drm/i915/display/intel_vrr.c
168
return crtc_state->vrr.vmax +
sys/dev/pci/drm/i915/display/intel_vrr.c
169
intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
172
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
174
return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
177
int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
179
return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
183
is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
185
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
187
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_vrr.c
207
cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
sys/dev/pci/drm/i915/display/intel_vrr.c
211
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_vrr.c
220
crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
sys/dev/pci/drm/i915/display/intel_vrr.c
223
crtc_state->cmrr.cmrr_n);
sys/dev/pci/drm/i915/display/intel_vrr.c
225
crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
sys/dev/pci/drm/i915/display/intel_vrr.c
231
void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
233
crtc_state->cmrr.enable = true;
sys/dev/pci/drm/i915/display/intel_vrr.c
240
crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
sys/dev/pci/drm/i915/display/intel_vrr.c
241
crtc_state->vrr.vmin = crtc_state->vrr.vmax;
sys/dev/pci/drm/i915/display/intel_vrr.c
242
crtc_state->vrr.flipline = crtc_state->vrr.vmin;
sys/dev/pci/drm/i915/display/intel_vrr.c
243
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
sys/dev/pci/drm/i915/display/intel_vrr.c
247
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
249
crtc_state->vrr.enable = true;
sys/dev/pci/drm/i915/display/intel_vrr.c
250
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
sys/dev/pci/drm/i915/display/intel_vrr.c
258
int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
260
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
261
int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
sys/dev/pci/drm/i915/display/intel_vrr.c
267
intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
271
int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
273
return intel_vrr_fixed_rr_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
277
int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
279
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
281
return intel_vrr_fixed_rr_vtotal(crtc_state) -
sys/dev/pci/drm/i915/display/intel_vrr.c
286
int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
288
return intel_vrr_fixed_rr_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
291
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
293
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
294
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
296
if (!intel_vrr_possible(crtc_state))
sys/dev/pci/drm/i915/display/intel_vrr.c
300
intel_vrr_fixed_rr_vmin(crtc_state) - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
302
intel_vrr_fixed_rr_vmax(crtc_state) - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
304
intel_vrr_fixed_rr_flipline(crtc_state) - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
308
void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
314
crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
sys/dev/pci/drm/i915/display/intel_vrr.c
315
crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
sys/dev/pci/drm/i915/display/intel_vrr.c
319
int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
328
return crtc_state->hw.adjusted_mode.crtc_vtotal;
sys/dev/pci/drm/i915/display/intel_vrr.c
346
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vrr.c
349
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
354
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_vrr.c
363
crtc_state->vrr.in_range =
sys/dev/pci/drm/i915/display/intel_vrr.c
374
if (crtc_state->joiner_pipes)
sys/dev/pci/drm/i915/display/intel_vrr.c
375
crtc_state->vrr.in_range = false;
sys/dev/pci/drm/i915/display/intel_vrr.c
377
vmin = intel_vrr_compute_vmin(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
379
if (crtc_state->vrr.in_range) {
sys/dev/pci/drm/i915/display/intel_vrr.c
381
crtc_state->update_lrr = true;
sys/dev/pci/drm/i915/display/intel_vrr.c
387
crtc_state->vrr.vmin = vmin;
sys/dev/pci/drm/i915/display/intel_vrr.c
388
crtc_state->vrr.vmax = vmax;
sys/dev/pci/drm/i915/display/intel_vrr.c
390
crtc_state->vrr.flipline = crtc_state->vrr.vmin;
sys/dev/pci/drm/i915/display/intel_vrr.c
392
if (crtc_state->uapi.vrr_enabled && vmin < vmax)
sys/dev/pci/drm/i915/display/intel_vrr.c
393
intel_vrr_compute_vrr_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
394
else if (is_cmrr_frac_required(crtc_state) && is_edp)
sys/dev/pci/drm/i915/display/intel_vrr.c
395
intel_vrr_compute_cmrr_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
397
intel_vrr_compute_fixed_rr_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
404
crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display);
sys/dev/pci/drm/i915/display/intel_vrr.c
407
crtc_state->vrr.vsync_start =
sys/dev/pci/drm/i915/display/intel_vrr.c
408
(crtc_state->hw.adjusted_mode.crtc_vtotal -
sys/dev/pci/drm/i915/display/intel_vrr.c
409
crtc_state->hw.adjusted_mode.vsync_start);
sys/dev/pci/drm/i915/display/intel_vrr.c
410
crtc_state->vrr.vsync_end =
sys/dev/pci/drm/i915/display/intel_vrr.c
411
(crtc_state->hw.adjusted_mode.crtc_vtotal -
sys/dev/pci/drm/i915/display/intel_vrr.c
412
crtc_state->hw.adjusted_mode.vsync_end);
sys/dev/pci/drm/i915/display/intel_vrr.c
416
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
418
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
419
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/intel_vrr.c
421
if (!intel_vrr_possible(crtc_state))
sys/dev/pci/drm/i915/display/intel_vrr.c
425
crtc_state->vrr.guardband =
sys/dev/pci/drm/i915/display/intel_vrr.c
426
crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
sys/dev/pci/drm/i915/display/intel_vrr.c
429
crtc_state->vrr.pipeline_full =
sys/dev/pci/drm/i915/display/intel_vrr.c
430
min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
sys/dev/pci/drm/i915/display/intel_vrr.c
431
crtc_state->framestart_delay - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
437
crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
438
crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
439
crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
443
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
445
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
449
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
sys/dev/pci/drm/i915/display/intel_vrr.c
452
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
sys/dev/pci/drm/i915/display/intel_vrr.c
455
VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
sys/dev/pci/drm/i915/display/intel_vrr.c
459
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
461
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
462
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
488
if (!intel_vrr_possible(crtc_state)) {
sys/dev/pci/drm/i915/display/intel_vrr.c
494
if (crtc_state->cmrr.enable) {
sys/dev/pci/drm/i915/display/intel_vrr.c
496
upper_32_bits(crtc_state->cmrr.cmrr_m));
sys/dev/pci/drm/i915/display/intel_vrr.c
498
lower_32_bits(crtc_state->cmrr.cmrr_m));
sys/dev/pci/drm/i915/display/intel_vrr.c
500
upper_32_bits(crtc_state->cmrr.cmrr_n));
sys/dev/pci/drm/i915/display/intel_vrr.c
502
lower_32_bits(crtc_state->cmrr.cmrr_n));
sys/dev/pci/drm/i915/display/intel_vrr.c
505
intel_vrr_set_fixed_rr_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
507
if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
509
trans_vrr_ctl(crtc_state));
sys/dev/pci/drm/i915/display/intel_vrr.c
514
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
sys/dev/pci/drm/i915/display/intel_vrr.c
515
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
sys/dev/pci/drm/i915/display/intel_vrr.c
519
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
521
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
522
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
524
if (!crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
539
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
541
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
542
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/intel_vrr.c
543
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
545
if (!crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
566
if (intel_vrr_is_push_sent(crtc_state))
sys/dev/pci/drm/i915/display/intel_vrr.c
572
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
574
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
575
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
577
if (!crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
595
void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
597
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
598
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
610
EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
sys/dev/pci/drm/i915/display/intel_vrr.c
613
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
615
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
616
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
618
if (!crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
62
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
622
crtc_state->vrr.vmin - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
624
crtc_state->vrr.vmax - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
626
crtc_state->vrr.flipline - 1);
sys/dev/pci/drm/i915/display/intel_vrr.c
632
intel_vrr_set_db_point_and_transmission_line(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
634
if (crtc_state->cmrr.enable) {
sys/dev/pci/drm/i915/display/intel_vrr.c
637
trans_vrr_ctl(crtc_state));
sys/dev/pci/drm/i915/display/intel_vrr.c
64
return crtc_state->vrr.flipline;
sys/dev/pci/drm/i915/display/intel_vrr.c
640
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
sys/dev/pci/drm/i915/display/intel_vrr.c
665
void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
667
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
668
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
673
intel_vrr_set_transcoder_timings(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
675
if (!intel_vrr_possible(crtc_state))
sys/dev/pci/drm/i915/display/intel_vrr.c
680
trans_vrr_ctl(crtc_state));
sys/dev/pci/drm/i915/display/intel_vrr.c
687
intel_vrr_set_db_point_and_transmission_line(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
690
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
sys/dev/pci/drm/i915/display/intel_vrr.c
693
void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
695
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
696
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
701
if (!intel_vrr_possible(crtc_state))
sys/dev/pci/drm/i915/display/intel_vrr.c
711
bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
713
return crtc_state->vrr.flipline &&
sys/dev/pci/drm/i915/display/intel_vrr.c
714
crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
sys/dev/pci/drm/i915/display/intel_vrr.c
715
crtc_state->vrr.flipline == intel_vrr_vmin_flipline(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
718
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
720
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
721
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
sys/dev/pci/drm/i915/display/intel_vrr.c
729
crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
sys/dev/pci/drm/i915/display/intel_vrr.c
731
if (crtc_state->cmrr.enable) {
sys/dev/pci/drm/i915/display/intel_vrr.c
732
crtc_state->cmrr.cmrr_n =
sys/dev/pci/drm/i915/display/intel_vrr.c
735
crtc_state->cmrr.cmrr_m =
sys/dev/pci/drm/i915/display/intel_vrr.c
741
crtc_state->vrr.guardband =
sys/dev/pci/drm/i915/display/intel_vrr.c
745
crtc_state->vrr.pipeline_full =
sys/dev/pci/drm/i915/display/intel_vrr.c
749
crtc_state->vrr.flipline = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_vrr.c
751
crtc_state->vrr.vmax = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_vrr.c
753
crtc_state->vrr.vmin = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_vrr.c
763
crtc_state->hw.adjusted_mode.crtc_vtotal =
sys/dev/pci/drm/i915/display/intel_vrr.c
764
intel_vrr_vmin_vtotal(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
770
crtc_state->vrr.vsync_start =
sys/dev/pci/drm/i915/display/intel_vrr.c
772
crtc_state->vrr.vsync_end =
sys/dev/pci/drm/i915/display/intel_vrr.c
780
crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.c
782
crtc_state->vrr.enable = vrr_enable;
sys/dev/pci/drm/i915/display/intel_vrr.c
789
if (crtc_state->vrr.enable)
sys/dev/pci/drm/i915/display/intel_vrr.c
790
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
sys/dev/pci/drm/i915/display/intel_vrr.c
82
static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/intel_vrr.c
84
return crtc_state->hw.adjusted_mode.crtc_vblank_start -
sys/dev/pci/drm/i915/display/intel_vrr.c
85
crtc_state->hw.adjusted_mode.crtc_vdisplay;
sys/dev/pci/drm/i915/display/intel_vrr.h
20
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
22
void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_vrr.h
24
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
25
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
26
void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
28
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
30
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
31
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
33
void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
34
int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
35
int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
36
int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
37
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
38
int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
39
bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
40
void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
41
void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_vrr.h
42
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/intel_wm.c
119
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/intel_wm.c
125
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/intel_wm.h
29
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
154
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
sys/dev/pci/drm/i915/display/skl_scaler.c
160
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
162
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
163
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_scaler.c
165
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/skl_scaler.c
166
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/skl_scaler.c
167
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/skl_scaler.c
185
if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&
sys/dev/pci/drm/i915/display/skl_scaler.c
267
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
269
const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/skl_scaler.c
272
if (crtc_state->pch_pfit.enabled) {
sys/dev/pci/drm/i915/display/skl_scaler.c
273
width = drm_rect_width(&crtc_state->pch_pfit.dst);
sys/dev/pci/drm/i915/display/skl_scaler.c
274
height = drm_rect_height(&crtc_state->pch_pfit.dst);
sys/dev/pci/drm/i915/display/skl_scaler.c
279
return skl_update_scaler(crtc_state, !crtc_state->hw.active,
sys/dev/pci/drm/i915/display/skl_scaler.c
281
&crtc_state->scaler_state.scaler_id,
sys/dev/pci/drm/i915/display/skl_scaler.c
282
drm_rect_width(&crtc_state->pipe_src),
sys/dev/pci/drm/i915/display/skl_scaler.c
283
drm_rect_height(&crtc_state->pipe_src),
sys/dev/pci/drm/i915/display/skl_scaler.c
285
crtc_state->pch_pfit.enabled);
sys/dev/pci/drm/i915/display/skl_scaler.c
297
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
311
return skl_update_scaler(crtc_state, force_detach,
sys/dev/pci/drm/i915/display/skl_scaler.c
378
static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
385
struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
467
if (crtc_state->pch_pfit.enabled) {
sys/dev/pci/drm/i915/display/skl_scaler.c
472
drm_rect_width(&crtc_state->pipe_src) << 16,
sys/dev/pci/drm/i915/display/skl_scaler.c
473
drm_rect_height(&crtc_state->pipe_src) << 16);
sys/dev/pci/drm/i915/display/skl_scaler.c
483
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
sys/dev/pci/drm/i915/display/skl_scaler.c
488
hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/skl_scaler.c
490
vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/skl_scaler.c
498
drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);
sys/dev/pci/drm/i915/display/skl_scaler.c
518
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_scaler.c
521
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
523
return intel_atomic_setup_scaler(crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
534
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_scaler.c
537
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
558
return intel_atomic_setup_scaler(crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
584
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_scaler.c
587
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
741
void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
743
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
744
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_scaler.c
746
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
747
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
sys/dev/pci/drm/i915/display/skl_scaler.c
759
if (!crtc_state->pch_pfit.enabled)
sys/dev/pci/drm/i915/display/skl_scaler.c
763
crtc_state->scaler_state.scaler_id < 0))
sys/dev/pci/drm/i915/display/skl_scaler.c
767
adl_scaler_ecc_mask(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
770
drm_rect_width(&crtc_state->pipe_src) << 16,
sys/dev/pci/drm/i915/display/skl_scaler.c
771
drm_rect_height(&crtc_state->pipe_src) << 16);
sys/dev/pci/drm/i915/display/skl_scaler.c
782
skl_scaler_get_filter_select(crtc_state->hw.scaling_filter);
sys/dev/pci/drm/i915/display/skl_scaler.c
787
crtc_state->hw.scaling_filter);
sys/dev/pci/drm/i915/display/skl_scaler.c
804
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.c
812
&crtc_state->scaler_state.scalers[scaler_id];
sys/dev/pci/drm/i915/display/skl_scaler.c
884
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
886
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_scaler.c
888
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
907
void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
909
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
910
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_scaler.c
911
struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.c
924
crtc_state->pch_pfit.enabled = true;
sys/dev/pci/drm/i915/display/skl_scaler.c
929
drm_rect_init(&crtc_state->pch_pfit.dst,
sys/dev/pci/drm/i915/display/skl_scaler.c
946
void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
948
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
950
if (!crtc_state->pch_pfit.enabled)
sys/dev/pci/drm/i915/display/skl_scaler.c
956
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_scaler.c
958
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.c
959
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_scaler.c
961
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_scaler.h
19
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.h
21
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.h
27
void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.h
31
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_scaler.h
34
const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.h
37
void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.h
45
void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_scaler.h
47
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1154
static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1156
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1162
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1165
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1212
static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1214
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1220
if (crtc_state->gamma_enable)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1223
if (crtc_state->csc_enable)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1353
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1380
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1405
skl_write_plane_wm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1411
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1422
skl_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1426
crtc_state->async_flip_planes & BIT(plane->id))
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1431
glk_plane_color_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1462
skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1477
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1487
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1492
if (crtc_state->enable_psr2_su_region_et)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1493
y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1524
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1542
glk_plane_color_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1589
skl_write_plane_wm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1596
icl_plane_csc_load_black(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1598
icl_plane_update_sel_fetch_noarm(dsb, plane, crtc_state, plane_state, color_plane);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1603
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1609
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1616
icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1622
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1631
skl_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1641
skl_program_plane_scaler(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1643
icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1670
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1680
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1707
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1783
if (crtc_state->hw.enable &&
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1784
crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1806
static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1813
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2302
static int skl_plane_check(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2312
ret = skl_plane_check_fb(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2322
ret = intel_plane_check_clipping(plane_state, crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
2336
ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
264
static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
267
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
288
static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
291
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3009
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
3025
if (crtc_state->joiner_pipes) {
sys/dev/pci/drm/i915/display/skl_universal_plane.c
315
static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_universal_plane.c
318
unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
830
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
835
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
sys/dev/pci/drm/i915/display/skl_universal_plane.c
837
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_universal_plane.c
839
&crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/skl_universal_plane.c
840
const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_universal_plane.c
842
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_universal_plane.c
876
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
882
skl_write_plane_wm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
890
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
895
if (!crtc_state->enable_psr2_sel_fetch)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
904
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_universal_plane.c
913
skl_write_plane_wm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_universal_plane.c
915
icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1257
use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1264
crtc_state->uapi.async_flip &&
sys/dev/pci/drm/i915/display/skl_watermark.c
1269
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1278
if (use_minimal_wm0_only(crtc_state, plane))
sys/dev/pci/drm/i915/display/skl_watermark.c
1285
skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
1287
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1288
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
1296
data_rate += crtc_state->rel_data_rate[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1299
data_rate += crtc_state->rel_data_rate_y[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1414
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
1428
memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
sys/dev/pci/drm/i915/display/skl_watermark.c
1429
memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
sys/dev/pci/drm/i915/display/skl_watermark.c
1430
memset(crtc_state->wm.skl.plane_min_ddb, 0,
sys/dev/pci/drm/i915/display/skl_watermark.c
1431
sizeof(crtc_state->wm.skl.plane_min_ddb));
sys/dev/pci/drm/i915/display/skl_watermark.c
1432
memset(crtc_state->wm.skl.plane_interim_ddb, 0,
sys/dev/pci/drm/i915/display/skl_watermark.c
1433
sizeof(crtc_state->wm.skl.plane_interim_ddb));
sys/dev/pci/drm/i915/display/skl_watermark.c
1435
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
1444
cursor_size = skl_cursor_allocation(crtc_state, num_active);
sys/dev/pci/drm/i915/display/skl_watermark.c
1446
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
sys/dev/pci/drm/i915/display/skl_watermark.c
1449
iter.data_rate = skl_total_relative_data_rate(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1459
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1463
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1503
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1505
&crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1506
u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1508
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1510
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1516
crtc_state->nv12_planes & BIT(plane_id)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
1518
crtc_state->rel_data_rate_y[plane_id]);
sys/dev/pci/drm/i915/display/skl_watermark.c
1520
crtc_state->rel_data_rate[plane_id]);
sys/dev/pci/drm/i915/display/skl_watermark.c
1523
crtc_state->rel_data_rate[plane_id]);
sys/dev/pci/drm/i915/display/skl_watermark.c
1542
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1544
&crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1546
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1549
crtc_state->nv12_planes & BIT(plane_id))
sys/dev/pci/drm/i915/display/skl_watermark.c
1570
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1572
&crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1574
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1576
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
1579
crtc_state->nv12_planes & BIT(plane_id)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
1640
intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
1642
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1647
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
1650
pixel_rate = crtc_state->pixel_rate;
sys/dev/pci/drm/i915/display/skl_watermark.c
1655
crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
sys/dev/pci/drm/i915/display/skl_watermark.c
1662
skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1668
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1746
wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state));
sys/dev/pci/drm/i915/display/skl_watermark.c
1752
skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1766
return skl_compute_wm_params(crtc_state, width,
sys/dev/pci/drm/i915/display/skl_watermark.c
1769
intel_plane_pixel_rate(crtc_state, plane_state),
sys/dev/pci/drm/i915/display/skl_watermark.c
1798
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1806
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1812
(use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
1821
crtc_state->hw.pipe_mode.crtc_htotal,
sys/dev/pci/drm/i915/display/skl_watermark.c
1828
if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
sys/dev/pci/drm/i915/display/skl_watermark.c
1937
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1942
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1950
skl_compute_plane_wm(crtc_state, plane, level, latency,
sys/dev/pci/drm/i915/display/skl_watermark.c
1957
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
1962
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
1971
skl_compute_plane_wm(crtc_state, plane, 0, latency,
sys/dev/pci/drm/i915/display/skl_watermark.c
2039
static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2043
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2044
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2048
ret = skl_compute_plane_wm_params(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2053
skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
sys/dev/pci/drm/i915/display/skl_watermark.c
2059
tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
sys/dev/pci/drm/i915/display/skl_watermark.c
2068
static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2072
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2079
ret = skl_compute_plane_wm_params(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2084
skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
sys/dev/pci/drm/i915/display/skl_watermark.c
2089
static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2094
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2100
if (!intel_wm_plane_visible(crtc_state, plane_state))
sys/dev/pci/drm/i915/display/skl_watermark.c
2103
ret = skl_build_plane_wm_single(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2109
ret = skl_build_plane_wm_uv(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2118
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2124
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2137
!intel_wm_plane_visible(crtc_state, plane_state));
sys/dev/pci/drm/i915/display/skl_watermark.c
2141
ret = skl_build_plane_wm_single(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2146
ret = skl_build_plane_wm_single(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2150
} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
sys/dev/pci/drm/i915/display/skl_watermark.c
2151
ret = skl_build_plane_wm_single(crtc_state, plane_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2161
cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
2163
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2165
to_intel_atomic_state(crtc_state->uapi.state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2174
return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
sys/dev/pci/drm/i915/display/skl_watermark.c
2179
dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
2181
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
2183
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_watermark.c
2184
int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
sys/dev/pci/drm/i915/display/skl_watermark.c
2185
crtc_state->hw.adjusted_mode.clock);
sys/dev/pci/drm/i915/display/skl_watermark.c
2188
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
sys/dev/pci/drm/i915/display/skl_watermark.c
2191
if (!crtc_state->dsc.compression_enable ||
sys/dev/pci/drm/i915/display/skl_watermark.c
2207
dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2209
return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
sys/dev/pci/drm/i915/display/skl_watermark.c
2213
scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
2216
&crtc_state->scaler_state;
sys/dev/pci/drm/i915/display/skl_watermark.c
2219
int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
sys/dev/pci/drm/i915/display/skl_watermark.c
2220
crtc_state->hw.adjusted_mode.clock);
sys/dev/pci/drm/i915/display/skl_watermark.c
2231
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
sys/dev/pci/drm/i915/display/skl_watermark.c
2239
scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2241
return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
sys/dev/pci/drm/i915/display/skl_watermark.c
2245
skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2249
&crtc_state->hw.adjusted_mode;
sys/dev/pci/drm/i915/display/skl_watermark.c
2251
return crtc_state->framestart_delay +
sys/dev/pci/drm/i915/display/skl_watermark.c
2253
scaler_prefill_latency(crtc_state) +
sys/dev/pci/drm/i915/display/skl_watermark.c
2254
dsc_prefill_latency(crtc_state) +
sys/dev/pci/drm/i915/display/skl_watermark.c
2259
static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
2261
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
2266
const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2280
static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
2283
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2298
if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
sys/dev/pci/drm/i915/display/skl_watermark.c
2305
static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
2307
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2308
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
2311
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
2314
wm0_lines = skl_max_wm0_lines(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2316
level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
sys/dev/pci/drm/i915/display/skl_watermark.c
2324
crtc_state->wm_level_disabled = level < display->wm.num_levels - 1;
sys/dev/pci/drm/i915/display/skl_watermark.c
2331
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2344
skl_is_vblank_too_short(crtc_state, wm0_lines,
sys/dev/pci/drm/i915/display/skl_watermark.c
2350
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
2364
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
2380
ret = icl_build_plane_wm(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2382
ret = skl_build_plane_wm(crtc_state, plane_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2387
crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
sys/dev/pci/drm/i915/display/skl_watermark.c
2389
return skl_wm_check_vblank(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
2868
const struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/skl_watermark.c
2876
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
sys/dev/pci/drm/i915/display/skl_watermark.c
2877
display->pkgc.disable[crtc->pipe] = crtc_state->vrr.enable;
sys/dev/pci/drm/i915/display/skl_watermark.c
2878
display->pkgc.linetime[crtc->pipe] = DIV_ROUND_UP(crtc_state->linetime, 8);
sys/dev/pci/drm/i915/display/skl_watermark.c
302
static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
304
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
305
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
3070
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3077
memset(&crtc_state->wm.skl.optimal, 0,
sys/dev/pci/drm/i915/display/skl_watermark.c
3078
sizeof(crtc_state->wm.skl.optimal));
sys/dev/pci/drm/i915/display/skl_watermark.c
3079
if (crtc_state->hw.active) {
sys/dev/pci/drm/i915/display/skl_watermark.c
3080
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
sys/dev/pci/drm/i915/display/skl_watermark.c
3083
crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
sys/dev/pci/drm/i915/display/skl_watermark.c
3089
&crtc_state->wm.skl.plane_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
3091
&crtc_state->wm.skl.plane_ddb_y[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
3093
&crtc_state->wm.skl.plane_min_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
3095
&crtc_state->wm.skl.plane_interim_ddb[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
3097
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
3108
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
3117
crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
sys/dev/pci/drm/i915/display/skl_watermark.c
3118
crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
sys/dev/pci/drm/i915/display/skl_watermark.c
312
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
3122
skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);
sys/dev/pci/drm/i915/display/skl_watermark.c
315
if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
sys/dev/pci/drm/i915/display/skl_watermark.c
320
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
342
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
355
static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
357
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
360
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
365
&crtc_state->wm.skl.optimal.planes[plane_id];
sys/dev/pci/drm/i915/display/skl_watermark.c
3719
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3722
entries[crtc->pipe] = crtc_state->wm.skl.ddb;
sys/dev/pci/drm/i915/display/skl_watermark.c
3726
const struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3735
if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,
sys/dev/pci/drm/i915/display/skl_watermark.c
374
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
376
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
3767
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3773
drm_WARN_ON(display->drm, crtc_state->active_planes != 0);
sys/dev/pci/drm/i915/display/skl_watermark.c
3775
memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));
sys/dev/pci/drm/i915/display/skl_watermark.c
3788
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3804
memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));
sys/dev/pci/drm/i915/display/skl_watermark.c
3811
struct intel_crtc_state *crtc_state =
sys/dev/pci/drm/i915/display/skl_watermark.c
3817
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
sys/dev/pci/drm/i915/display/skl_watermark.c
3818
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
sys/dev/pci/drm/i915/display/skl_watermark.c
3820
crtc_state->wm.skl.plane_min_ddb[plane->id] = 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
3821
crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0;
sys/dev/pci/drm/i915/display/skl_watermark.c
3823
memset(&crtc_state->wm.skl.raw.planes[plane->id], 0,
sys/dev/pci/drm/i915/display/skl_watermark.c
3824
sizeof(crtc_state->wm.skl.raw.planes[plane->id]));
sys/dev/pci/drm/i915/display/skl_watermark.c
3825
memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0,
sys/dev/pci/drm/i915/display/skl_watermark.c
3826
sizeof(crtc_state->wm.skl.optimal.planes[plane->id]));
sys/dev/pci/drm/i915/display/skl_watermark.c
386
if (crtc_state->inherited)
sys/dev/pci/drm/i915/display/skl_watermark.c
390
return tgl_crtc_can_enable_sagv(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
392
return skl_crtc_can_enable_sagv(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
468
static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/skl_watermark.c
470
const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
sys/dev/pci/drm/i915/display/skl_watermark.c
473
if (!crtc_state->hw.active)
sys/dev/pci/drm/i915/display/skl_watermark.c
531
struct intel_crtc_state *crtc_state;
sys/dev/pci/drm/i915/display/skl_watermark.c
571
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
sys/dev/pci/drm/i915/display/skl_watermark.c
572
if (IS_ERR(crtc_state))
sys/dev/pci/drm/i915/display/skl_watermark.c
573
return PTR_ERR(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
579
crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
sys/dev/pci/drm/i915/display/skl_watermark.c
580
crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
sys/dev/pci/drm/i915/display/skl_watermark.c
593
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
599
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
630
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/skl_watermark.c
633
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.c
634
struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);
sys/dev/pci/drm/i915/display/skl_watermark.c
640
ret = skl_compute_wm_params(crtc_state, 256,
sys/dev/pci/drm/i915/display/skl_watermark.c
644
crtc_state->pixel_rate, &wp, 0, 0);
sys/dev/pci/drm/i915/display/skl_watermark.c
650
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
sys/dev/pci/drm/i915/display/skl_watermark.h
27
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/skl_watermark.h
58
unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/vlv_dsi.c
1757
int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/vlv_dsi.c
1759
struct intel_display *display = to_intel_display(crtc_state);
sys/dev/pci/drm/i915/display/vlv_dsi.c
1761
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
sys/dev/pci/drm/i915/display/vlv_dsi.c
612
const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/i915/display/vlv_dsi.c
615
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
sys/dev/pci/drm/i915/display/vlv_dsi.c
821
const struct intel_crtc_state *crtc_state,
sys/dev/pci/drm/i915/display/vlv_dsi.c
824
intel_crtc_vblank_on(crtc_state);
sys/dev/pci/drm/i915/display/vlv_dsi.h
16
int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
sys/dev/pci/drm/i915/display/vlv_dsi.h
22
static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
213
#define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
214
drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
231
#define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
232
drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
234
__drm_atomic_get_current_plane_state((crtc_state)->state, \
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
293
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
55
const struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_atomic_helper.h
62
int drm_atomic_helper_check_crtc_primary_plane(struct drm_crtc_state *crtc_state);
sys/dev/pci/drm/include/drm/drm_bridge.h
1341
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_bridge.h
1355
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_bridge.h
431
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_bridge.h
471
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_bridge.h
503
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_crtc.h
1326
bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state);
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
685
struct drm_crtc_state *crtc_state,
sys/dev/pci/drm/include/drm/drm_modeset_helper_vtables.h
840
struct drm_crtc_state *crtc_state,
