cpu_reg - OpenBSD

sys/dev/pci/if_bnx.c

2806

bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,

sys/dev/pci/if_bnx.c

2813

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/pci/if_bnx.c

2814

val |= cpu_reg->mode_value_halt;

sys/dev/pci/if_bnx.c

2815

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/pci/if_bnx.c

2816

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/pci/if_bnx.c

2819

offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2828

offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2837

offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2846

offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2855

offset = cpu_reg->spad_base +

sys/dev/pci/if_bnx.c

2856

(fw->rodata_addr - cpu_reg->mips_view_base);

sys/dev/pci/if_bnx.c

2865

REG_WR_IND(sc, cpu_reg->inst, 0);

sys/dev/pci/if_bnx.c

2866

REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);

sys/dev/pci/if_bnx.c

2869

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/pci/if_bnx.c

2870

val &= ~cpu_reg->mode_value_halt;

sys/dev/pci/if_bnx.c

2871

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/pci/if_bnx.c

2872

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/pci/if_bnx.c

2888

struct cpu_reg cpu_reg;

sys/dev/pci/if_bnx.c

2906

cpu_reg.mode = BNX_RXP_CPU_MODE;

sys/dev/pci/if_bnx.c

2907

cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

2908

cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

2909

cpu_reg.state = BNX_RXP_CPU_STATE;

sys/dev/pci/if_bnx.c

2910

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

2911

cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

2912

cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

2913

cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

2914

cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

2915

cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

2916

cpu_reg.spad_base = BNX_RXP_SCRATCH;

sys/dev/pci/if_bnx.c

2917

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

2950

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

2953

cpu_reg.mode = BNX_TXP_CPU_MODE;

sys/dev/pci/if_bnx.c

2954

cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

2955

cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

2956

cpu_reg.state = BNX_TXP_CPU_STATE;

sys/dev/pci/if_bnx.c

2957

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

2958

cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

2959

cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

2960

cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

2961

cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

2962

cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

2963

cpu_reg.spad_base = BNX_TXP_SCRATCH;

sys/dev/pci/if_bnx.c

2964

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

2997

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3000

cpu_reg.mode = BNX_TPAT_CPU_MODE;

sys/dev/pci/if_bnx.c

3001

cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3002

cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3003

cpu_reg.state = BNX_TPAT_CPU_STATE;

sys/dev/pci/if_bnx.c

3004

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3005

cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3006

cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3007

cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3008

cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3009

cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3010

cpu_reg.spad_base = BNX_TPAT_SCRATCH;

sys/dev/pci/if_bnx.c

3011

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3044

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

3047

cpu_reg.mode = BNX_COM_CPU_MODE;

sys/dev/pci/if_bnx.c

3048

cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;

sys/dev/pci/if_bnx.c

3049

cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;

sys/dev/pci/if_bnx.c

3050

cpu_reg.state = BNX_COM_CPU_STATE;

sys/dev/pci/if_bnx.c

3051

cpu_reg.state_value_clear = 0xffffff;

sys/dev/pci/if_bnx.c

3052

cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;

sys/dev/pci/if_bnx.c

3053

cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;

sys/dev/pci/if_bnx.c

3054

cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;

sys/dev/pci/if_bnx.c

3055

cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;

sys/dev/pci/if_bnx.c

3056

cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;

sys/dev/pci/if_bnx.c

3057

cpu_reg.spad_base = BNX_COM_SCRATCH;

sys/dev/pci/if_bnx.c

3058

cpu_reg.mips_view_base = 0x8000000;

sys/dev/pci/if_bnx.c

3091

bnx_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/pci/if_bnx.c

349

void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *,