sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

100

adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

830

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

843

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

851

return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1675

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1688

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1696

return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1019

if (CONTROLLER_ID_D1 != bp_params->controller_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1052

uint8_t controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1059

bp_params->controller_id, &controller_id)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1060

clk.sPCLKInput.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1122

uint8_t controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1129

bp_params->controller_id, &controller_id)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1149

clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1214

uint8_t controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1220

&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1240

clk.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1832

bp_params->controller_id, &atom_controller_id))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1905

bp_params->controller_id, &atom_controller_id))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1987

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2006

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2013

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2039

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2056

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2063

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2319

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2340

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

76

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

80

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

90

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

485

uint8_t controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

492

controller_id, &controller_id)) {

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

512

clk.crtc_id = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

532

bp_params->target_pixel_clock_100hz, (int)controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

614

bp_params->controller_id, &atom_controller_id))

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

706

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

723

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

730

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

800

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

805

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

845

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

877

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

76

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

80

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

90

enum controller_id crtc_id,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

76

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h

41

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

99

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h

41

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

35

bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

540

ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

546

if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

102

enum controller_id id,

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

125

enum controller_id controller_id,

sys/dev/pci/drm/amd/display/dc/dc_types.h

682

enum controller_id controllerId;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

103

dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

113

if (controller_id == 0)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

234

unsigned int controller_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

245

controller_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

58

static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

75

MASTER_COMM_CMD_REG_BYTE1, controller_id);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

90

uint32_t controller_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1016

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1074

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1118

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1180

bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1288

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1334

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

863

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

937

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

972

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

174

unsigned int controller_id,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

146

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1805

switch (tg110->controller_id) {

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2346

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

238

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

307

bp_params.controller_id = tg110->controller_id;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

101

enum controller_id controller_id;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

694

tg110->controller_id = CONTROLLER_ID_UNDERLAY0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1261

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

151

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

393

switch (tg110->controller_id) {

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

251

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

233

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/pci/drm/amd/display/dc/dm_services.h

250

bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

74

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

89

if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

92

dcb, controller_id + 1, cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

98

HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

45

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1273

enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

209

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

225

if (controller_id == underlay_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

226

controller_id = CONTROLLER_ID_UNDERLAY0 - 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

228

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

231

dcb, controller_id + 1, cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

240

if (controller_id < CONTROLLER_ID_MAX - 1)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

242

HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3198

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3213

controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

117

enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id);

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

115

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

130

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

133

dcb, controller_id + 1, cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

139

HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

153

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

170

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

173

dcb, controller_id + 1, cntl);

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

179

HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

184

dce120_init_pte(ctx, controller_id);

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

79

#define CNTL_ID(controller_id)\

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

80

controller_id

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

84

static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3590

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

149

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

94

uint8_t controller_id,

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

92

enum controller_id controller_id;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

690

enum controller_id controllerId;

sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h

42

bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h

50

unsigned int controller_id,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

895

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1002

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1238

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1711

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

137

enum controller_id controller_id;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

170

enum controller_id controller_id;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

218

enum controller_id controller_id; /* (Which CRTC uses this PLL) */

sys/dev/pci/drm/amd/display/include/grph_object_id.h

255

static inline enum controller_id dal_graphics_object_id_get_controller_id(

sys/dev/pci/drm/amd/display/include/grph_object_id.h

259

return (enum controller_id) id.id;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

50

uint32_t controller_id;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

88

display_cfg->controller_id = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

309

if (display_config->displays[index].controller_id != 0)