bin/md5/md5.c

1000

hf->update(&context, data, (size_t)TEST_BLOCK_LEN);

bin/md5/md5.c

1001

digest_end(hf, &context, digest, sizeof(digest), hf->base64);

bin/md5/md5.c

1017

union ANY_CTX context;

bin/md5/md5.c

1038

hf->init(&context);

bin/md5/md5.c

1039

hf->update(&context, test_strings[i],

bin/md5/md5.c

1041

digest_end(hf, &context, digest, sizeof(digest),

bin/md5/md5.c

1048

hf->init(&context);

bin/md5/md5.c

1050

hf->update(&context, buf, sizeof(buf));

bin/md5/md5.c

1051

digest_end(hf, &context, digest, sizeof(digest), hf->base64);

bin/md5/md5.c

656

union ANY_CTX context;

bin/md5/md5.c

659

hf->init(&context);

bin/md5/md5.c

660

hf->update(&context, string, strlen(string));

bin/md5/md5.c

661

digest_end(hf, &context, digest, sizeof(digest),

bin/md5/md5.c

780

union ANY_CTX context;

bin/md5/md5.c

922

hf->init(&context);

bin/md5/md5.c

924

hf->update(&context, data, nread);

bin/md5/md5.c

932

digest_end(hf, &context, digest, sizeof(digest), base64);

bin/md5/md5.c

979

union ANY_CTX context;

bin/md5/md5.c

998

hf->init(&context);

distrib/special/more/more.c

1011

Fseek(f, context.chrctr);

distrib/special/more/more.c

1012

Currline = context.line;

distrib/special/more/more.c

1183

context.line = saveln = Currline;

distrib/special/more/more.c

1184

context.chrctr = startline;

distrib/special/more/more.c

158

} context, screen_start;

distrib/special/more/more.c

315

context.line = context.chrctr = 0;

distrib/special/more/more.c

366

context.line = context.chrctr = 0L;

lib/libagentx/ax.c

1004

if (context != NULL) {

lib/libagentx/ax.c

1005

if (ax_pdu_add_str(ax, context) == -1)

lib/libagentx/ax.c

438

struct ax_ostring *context, struct ax_varbind *vblist, size_t nvb)

lib/libagentx/ax.c

446

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

457

struct ax_ostring *context, struct ax_varbind *vblist, size_t nvb)

lib/libagentx/ax.c

460

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

471

struct ax_ostring *context, struct ax_oid *id,

lib/libagentx/ax.c

475

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

487

struct ax_ostring *context, struct ax_oid *id)

lib/libagentx/ax.c

490

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

501

struct ax_ostring *context, uint8_t timeout, uint8_t priority,

lib/libagentx/ax.c

510

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

531

struct ax_ostring *context, uint8_t priority, uint8_t range_subid,

lib/libagentx/ax.c

535

sessionid, 0, 0, context) == -1)

lib/libagentx/ax.c

979

struct ax_ostring *context)

lib/libagentx/ax.c

990

if (context != NULL)

lib/libc/hash/sha1.c

108

SHA1Init(SHA1_CTX *context)

lib/libc/hash/sha1.c

112

context->count = 0;

lib/libc/hash/sha1.c

113

context->state[0] = 0x67452301;

lib/libc/hash/sha1.c

114

context->state[1] = 0xEFCDAB89;

lib/libc/hash/sha1.c

115

context->state[2] = 0x98BADCFE;

lib/libc/hash/sha1.c

116

context->state[3] = 0x10325476;

lib/libc/hash/sha1.c

117

context->state[4] = 0xC3D2E1F0;

lib/libc/hash/sha1.c

126

SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len)

lib/libc/hash/sha1.c

134

j = (size_t)((context->count >> 3) & 63);

lib/libc/hash/sha1.c

135

context->count += ((u_int64_t)len << 3);

lib/libc/hash/sha1.c

137

(void)memcpy(&context->buffer[j], data, (i = 64-j));

lib/libc/hash/sha1.c

138

SHA1Transform(context->state, context->buffer);

lib/libc/hash/sha1.c

140

SHA1Transform(context->state, (u_int8_t *)&data[i]);

lib/libc/hash/sha1.c

145

(void)memcpy(&context->buffer[j], &data[i], len - i);

lib/libc/hash/sha1.c

154

SHA1Pad(SHA1_CTX *context)

lib/libc/hash/sha1.c

160

finalcount[i] = (u_int8_t)((context->count >>

lib/libc/hash/sha1.c

163

SHA1Update(context, (u_int8_t *)"\200", 1);

lib/libc/hash/sha1.c

164

while ((context->count & 504) != 448)

lib/libc/hash/sha1.c

165

SHA1Update(context, (u_int8_t *)"\0", 1);

lib/libc/hash/sha1.c

166

SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */

lib/libc/hash/sha1.c

171

SHA1Final(u_int8_t digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context)

lib/libc/hash/sha1.c

175

SHA1Pad(context);

lib/libc/hash/sha1.c

178

((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);

lib/libc/hash/sha1.c

180

explicit_bzero(context, sizeof(*context));

lib/libc/hash/sha2.c

305

SHA224Init(SHA2_CTX *context)

lib/libc/hash/sha2.c

307

memcpy(context->state.st32, sha224_initial_hash_value,

lib/libc/hash/sha2.c

309

memset(context->buffer, 0, sizeof(context->buffer));

lib/libc/hash/sha2.c

310

context->bitcount[0] = 0;

lib/libc/hash/sha2.c

322

SHA224Final(u_int8_t digest[SHA224_DIGEST_LENGTH], SHA2_CTX *context)

lib/libc/hash/sha2.c

324

SHA224Pad(context);

lib/libc/hash/sha2.c

331

BE_32_TO_8(digest + i * 4, context->state.st32[i]);

lib/libc/hash/sha2.c

333

memcpy(digest, context->state.st32, SHA224_DIGEST_LENGTH);

lib/libc/hash/sha2.c

335

explicit_bzero(context, sizeof(*context));

lib/libc/hash/sha2.c

342

SHA256Init(SHA2_CTX *context)

lib/libc/hash/sha2.c

344

memcpy(context->state.st32, sha256_initial_hash_value,

lib/libc/hash/sha2.c

346

memset(context->buffer, 0, sizeof(context->buffer));

lib/libc/hash/sha2.c

347

context->bitcount[0] = 0;

lib/libc/hash/sha2.c

511

SHA256Update(SHA2_CTX *context, const u_int8_t *data, size_t len)

lib/libc/hash/sha2.c

519

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

lib/libc/hash/sha2.c

526

memcpy(&context->buffer[usedspace], data, freespace);

lib/libc/hash/sha2.c

527

context->bitcount[0] += freespace << 3;

lib/libc/hash/sha2.c

530

SHA256Transform(context->state.st32, context->buffer);

lib/libc/hash/sha2.c

533

memcpy(&context->buffer[usedspace], data, len);

lib/libc/hash/sha2.c

534

context->bitcount[0] += (u_int64_t)len << 3;

lib/libc/hash/sha2.c

542

SHA256Transform(context->state.st32, data);

lib/libc/hash/sha2.c

543

context->bitcount[0] += SHA256_BLOCK_LENGTH << 3;

lib/libc/hash/sha2.c

549

memcpy(context->buffer, data, len);

lib/libc/hash/sha2.c

550

context->bitcount[0] += len << 3;

lib/libc/hash/sha2.c

558

SHA256Pad(SHA2_CTX *context)

lib/libc/hash/sha2.c

562

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

lib/libc/hash/sha2.c

565

context->buffer[usedspace++] = 0x80;

lib/libc/hash/sha2.c

569

memset(&context->buffer[usedspace], 0,

lib/libc/hash/sha2.c

573

memset(&context->buffer[usedspace], 0,

lib/libc/hash/sha2.c

577

SHA256Transform(context->state.st32, context->buffer);

lib/libc/hash/sha2.c

580

memset(context->buffer, 0, SHA256_SHORT_BLOCK_LENGTH);

lib/libc/hash/sha2.c

584

memset(context->buffer, 0, SHA256_SHORT_BLOCK_LENGTH);

lib/libc/hash/sha2.c

587

*context->buffer = 0x80;

lib/libc/hash/sha2.c

590

BE_64_TO_8(&context->buffer[SHA256_SHORT_BLOCK_LENGTH],

lib/libc/hash/sha2.c

591

context->bitcount[0]);

lib/libc/hash/sha2.c

594

SHA256Transform(context->state.st32, context->buffer);

lib/libc/hash/sha2.c

602

SHA256Final(u_int8_t digest[SHA256_DIGEST_LENGTH], SHA2_CTX *context)

lib/libc/hash/sha2.c

604

SHA256Pad(context);

lib/libc/hash/sha2.c

611

BE_32_TO_8(digest + i * 4, context->state.st32[i]);

lib/libc/hash/sha2.c

613

memcpy(digest, context->state.st32, SHA256_DIGEST_LENGTH);

lib/libc/hash/sha2.c

615

explicit_bzero(context, sizeof(*context));

lib/libc/hash/sha2.c

622

SHA512Init(SHA2_CTX *context)

lib/libc/hash/sha2.c

624

memcpy(context->state.st64, sha512_initial_hash_value,

lib/libc/hash/sha2.c

626

memset(context->buffer, 0, sizeof(context->buffer));

lib/libc/hash/sha2.c

627

context->bitcount[0] = context->bitcount[1] = 0;

lib/libc/hash/sha2.c

792

SHA512Update(SHA2_CTX *context, const u_int8_t *data, size_t len)

lib/libc/hash/sha2.c

800

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

lib/libc/hash/sha2.c

807

memcpy(&context->buffer[usedspace], data, freespace);

lib/libc/hash/sha2.c

808

ADDINC128(context->bitcount, freespace << 3);

lib/libc/hash/sha2.c

811

SHA512Transform(context->state.st64, context->buffer);

lib/libc/hash/sha2.c

814

memcpy(&context->buffer[usedspace], data, len);

lib/libc/hash/sha2.c

815

ADDINC128(context->bitcount, len << 3);

lib/libc/hash/sha2.c

823

SHA512Transform(context->state.st64, data);

lib/libc/hash/sha2.c

824

ADDINC128(context->bitcount, SHA512_BLOCK_LENGTH << 3);

lib/libc/hash/sha2.c

830

memcpy(context->buffer, data, len);

lib/libc/hash/sha2.c

831

ADDINC128(context->bitcount, len << 3);

lib/libc/hash/sha2.c

839

SHA512Pad(SHA2_CTX *context)

lib/libc/hash/sha2.c

843

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

lib/libc/hash/sha2.c

846

context->buffer[usedspace++] = 0x80;

lib/libc/hash/sha2.c

850

memset(&context->buffer[usedspace], 0, SHA512_SHORT_BLOCK_LENGTH - usedspace);

lib/libc/hash/sha2.c

853

memset(&context->buffer[usedspace], 0, SHA512_BLOCK_LENGTH - usedspace);

lib/libc/hash/sha2.c

856

SHA512Transform(context->state.st64, context->buffer);

lib/libc/hash/sha2.c

859

memset(context->buffer, 0, SHA512_BLOCK_LENGTH - 2);

lib/libc/hash/sha2.c

863

memset(context->buffer, 0, SHA512_SHORT_BLOCK_LENGTH);

lib/libc/hash/sha2.c

866

*context->buffer = 0x80;

lib/libc/hash/sha2.c

869

BE_64_TO_8(&context->buffer[SHA512_SHORT_BLOCK_LENGTH],

lib/libc/hash/sha2.c

870

context->bitcount[1]);

lib/libc/hash/sha2.c

871

BE_64_TO_8(&context->buffer[SHA512_SHORT_BLOCK_LENGTH + 8],

lib/libc/hash/sha2.c

872

context->bitcount[0]);

lib/libc/hash/sha2.c

875

SHA512Transform(context->state.st64, context->buffer);

lib/libc/hash/sha2.c

883

SHA512Final(u_int8_t digest[SHA512_DIGEST_LENGTH], SHA2_CTX *context)

lib/libc/hash/sha2.c

885

SHA512Pad(context);

lib/libc/hash/sha2.c

892

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

lib/libc/hash/sha2.c

894

memcpy(digest, context->state.st64, SHA512_DIGEST_LENGTH);

lib/libc/hash/sha2.c

896

explicit_bzero(context, sizeof(*context));

lib/libc/hash/sha2.c

904

SHA384Init(SHA2_CTX *context)

lib/libc/hash/sha2.c

906

memcpy(context->state.st64, sha384_initial_hash_value,

lib/libc/hash/sha2.c

908

memset(context->buffer, 0, sizeof(context->buffer));

lib/libc/hash/sha2.c

909

context->bitcount[0] = context->bitcount[1] = 0;

lib/libc/hash/sha2.c

921

SHA384Final(u_int8_t digest[SHA384_DIGEST_LENGTH], SHA2_CTX *context)

lib/libc/hash/sha2.c

923

SHA384Pad(context);

lib/libc/hash/sha2.c

930

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

lib/libc/hash/sha2.c

932

memcpy(digest, context->state.st64, SHA384_DIGEST_LENGTH);

lib/libc/hash/sha2.c

935

explicit_bzero(context, sizeof(*context));

lib/libc/hash/sha2.c

941

SHA512_256Init(SHA2_CTX *context)

lib/libc/hash/sha2.c

943

memcpy(context->state.st64, sha512_256_initial_hash_value,

lib/libc/hash/sha2.c

945

memset(context->buffer, 0, sizeof(context->buffer));

lib/libc/hash/sha2.c

946

context->bitcount[0] = context->bitcount[1] = 0;

lib/libc/hash/sha2.c

958

SHA512_256Final(u_int8_t digest[SHA512_256_DIGEST_LENGTH], SHA2_CTX *context)

lib/libc/hash/sha2.c

960

SHA512_256Pad(context);

lib/libc/hash/sha2.c

967

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

lib/libc/hash/sha2.c

969

memcpy(digest, context->state.st64, SHA512_256_DIGEST_LENGTH);

lib/libc/hash/sha2.c

972

explicit_bzero(context, sizeof(*context));

lib/libcbor/src/cbor.c

103

return context.root;

lib/libcbor/src/cbor.c

55

struct _cbor_decoder_context context = (struct _cbor_decoder_context){

lib/libcbor/src/cbor.c

65

&callbacks, &context);

lib/libcbor/src/cbor.c

93

if (context.creation_failed) {

lib/libcbor/src/cbor.c

97

} else if (context.syntax_error) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

142

void cbor_builder_uint8_callback(void *context, uint8_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

143

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

151

void cbor_builder_uint16_callback(void *context, uint16_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

152

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

160

void cbor_builder_uint32_callback(void *context, uint32_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

161

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

169

void cbor_builder_uint64_callback(void *context, uint64_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

170

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

178

void cbor_builder_negint8_callback(void *context, uint8_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

179

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

187

void cbor_builder_negint16_callback(void *context, uint16_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

188

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

196

void cbor_builder_negint32_callback(void *context, uint32_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

197

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

205

void cbor_builder_negint64_callback(void *context, uint64_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

206

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

214

void cbor_builder_byte_string_callback(void *context, cbor_data data,

lib/libcbor/src/cbor/internal/builder_callbacks.c

216

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

248

void cbor_builder_byte_string_start_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

249

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

255

void cbor_builder_string_callback(void *context, cbor_data data,

lib/libcbor/src/cbor/internal/builder_callbacks.c

257

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

299

void cbor_builder_string_start_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

300

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

306

void cbor_builder_array_start_callback(void *context, uint64_t size) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

307

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

318

void cbor_builder_indef_array_start_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

319

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

325

void cbor_builder_indef_map_start_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

326

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

332

void cbor_builder_map_start_callback(void *context, uint64_t size) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

333

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

362

void cbor_builder_indef_break_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

363

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

381

void cbor_builder_float2_callback(void *context, float value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

382

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

389

void cbor_builder_float4_callback(void *context, float value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

390

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

397

void cbor_builder_float8_callback(void *context, double value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

398

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

405

void cbor_builder_null_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

406

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

412

void cbor_builder_undefined_callback(void *context) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

413

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

419

void cbor_builder_boolean_callback(void *context, bool value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

420

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/internal/builder_callbacks.c

426

void cbor_builder_tag_callback(void *context, uint64_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

427

struct _cbor_decoder_context *ctx = context;

lib/libcbor/src/cbor/streaming.c

102

callbacks->uint32(context, _cbor_load_uint32(source + 1));

lib/libcbor/src/cbor/streaming.c

110

callbacks->uint64(context, _cbor_load_uint64(source + 1));

lib/libcbor/src/cbor/streaming.c

146

callbacks->negint8(context,

lib/libcbor/src/cbor/streaming.c

154

callbacks->negint8(context, _cbor_load_uint8(source + 1));

lib/libcbor/src/cbor/streaming.c

162

callbacks->negint16(context, _cbor_load_uint16(source + 1));

lib/libcbor/src/cbor/streaming.c

170

callbacks->negint32(context, _cbor_load_uint32(source + 1));

lib/libcbor/src/cbor/streaming.c

178

callbacks->negint64(context, _cbor_load_uint64(source + 1));

lib/libcbor/src/cbor/streaming.c

238

callbacks->byte_string_start(context);

lib/libcbor/src/cbor/streaming.c

29

callbacks->callback_name(context, source + 1 + source_extra_offset, \

lib/libcbor/src/cbor/streaming.c

291

callbacks->string_start(context);

lib/libcbor/src/cbor/streaming.c

321

context, _cbor_load_uint8(source) - 0x80); /* 0x40 offset */

lib/libcbor/src/cbor/streaming.c

328

callbacks->array_start(context, _cbor_load_uint8(source + 1));

lib/libcbor/src/cbor/streaming.c

336

callbacks->array_start(context, _cbor_load_uint16(source + 1));

lib/libcbor/src/cbor/streaming.c

344

callbacks->array_start(context, _cbor_load_uint32(source + 1));

lib/libcbor/src/cbor/streaming.c

352

callbacks->array_start(context, _cbor_load_uint64(source + 1));

lib/libcbor/src/cbor/streaming.c

364

callbacks->indef_array_start(context);

lib/libcbor/src/cbor/streaming.c

393

callbacks->map_start(context,

lib/libcbor/src/cbor/streaming.c

401

callbacks->map_start(context, _cbor_load_uint8(source + 1));

lib/libcbor/src/cbor/streaming.c

409

callbacks->map_start(context, _cbor_load_uint16(source + 1));

lib/libcbor/src/cbor/streaming.c

417

callbacks->map_start(context, _cbor_load_uint32(source + 1));

lib/libcbor/src/cbor/streaming.c

425

callbacks->map_start(context, _cbor_load_uint64(source + 1));

lib/libcbor/src/cbor/streaming.c

437

callbacks->indef_map_start(context);

lib/libcbor/src/cbor/streaming.c

45

const struct cbor_callbacks *callbacks, void *context) {

lib/libcbor/src/cbor/streaming.c

453

callbacks->tag(context, (uint64_t)(_cbor_load_uint8(source) -

lib/libcbor/src/cbor/streaming.c

479

callbacks->tag(context, (uint64_t)(_cbor_load_uint8(source) -

lib/libcbor/src/cbor/streaming.c

486

callbacks->tag(context, _cbor_load_uint8(source + 1));

lib/libcbor/src/cbor/streaming.c

493

callbacks->tag(context, _cbor_load_uint16(source + 1));

lib/libcbor/src/cbor/streaming.c

500

callbacks->tag(context, _cbor_load_uint32(source + 1));

lib/libcbor/src/cbor/streaming.c

507

callbacks->tag(context, _cbor_load_uint64(source + 1));

lib/libcbor/src/cbor/streaming.c

544

callbacks->boolean(context, false);

lib/libcbor/src/cbor/streaming.c

550

callbacks->boolean(context, true);

lib/libcbor/src/cbor/streaming.c

556

callbacks->null(context);

lib/libcbor/src/cbor/streaming.c

562

callbacks->undefined(context);

lib/libcbor/src/cbor/streaming.c

572

callbacks->float2(context, _cbor_load_half(source + 1));

lib/libcbor/src/cbor/streaming.c

580

callbacks->float4(context, _cbor_load_float(source + 1));

lib/libcbor/src/cbor/streaming.c

588

callbacks->float8(context, _cbor_load_double(source + 1));

lib/libcbor/src/cbor/streaming.c

599

callbacks->indef_break(context);

lib/libcbor/src/cbor/streaming.c

79

callbacks->uint8(context, _cbor_load_uint8(source));

lib/libcbor/src/cbor/streaming.c

86

callbacks->uint8(context, _cbor_load_uint8(source + 1));

lib/libcbor/src/cbor/streaming.c

94

callbacks->uint16(context, _cbor_load_uint16(source + 1));

lib/libcbor/src/cbor/streaming.h

31

const struct cbor_callbacks* callbacks, void* context);

lib/libexpat/lib/expat.h

456

const XML_Char *context,

lib/libexpat/lib/expat.h

878

XML_ExternalEntityParserCreate(XML_Parser parser, const XML_Char *context,

lib/libexpat/lib/xmlparse.c

1740

XML_ExternalEntityParserCreate(XML_Parser oldParser, const XML_Char *context,

lib/libexpat/lib/xmlparse.c

1832

if (! context)

lib/libexpat/lib/xmlparse.c

1889

if (context) {

lib/libexpat/lib/xmlparse.c

1892

|| ! setContext(parser, context)) {

lib/libexpat/lib/xmlparse.c

3454

const XML_Char *context;

lib/libexpat/lib/xmlparse.c

3456

context = getContext(parser);

lib/libexpat/lib/xmlparse.c

3458

if (! context)

lib/libexpat/lib/xmlparse.c

3461

parser->m_externalEntityRefHandlerArg, context, entity->base,

lib/libexpat/lib/xmlparse.c

562

static XML_Bool setContext(XML_Parser parser, const XML_Char *context);

lib/libexpat/lib/xmlparse.c

7432

setContext(XML_Parser parser, const XML_Char *context) {

lib/libexpat/lib/xmlparse.c

7433

if (context == NULL) {

lib/libexpat/lib/xmlparse.c

7438

const XML_Char *s = context;

lib/libexpat/lib/xmlparse.c

7440

while (*context != XML_T('\0')) {

lib/libexpat/lib/xmlparse.c

7451

context = s;

lib/libexpat/lib/xmlparse.c

7480

for (context = s + 1; *context != CONTEXT_SEP && *context != XML_T('\0');

lib/libexpat/lib/xmlparse.c

7481

context++)

lib/libexpat/lib/xmlparse.c

7482

if (! poolAppendChar(&parser->m_tempPool, *context))

lib/libexpat/lib/xmlparse.c

7491

if (*context != XML_T('\0'))

lib/libexpat/lib/xmlparse.c

7492

++context;

lib/libexpat/lib/xmlparse.c

7493

s = context;

lib/libexpat/tests/basic_tests.c

3400

external_bom_checker(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/basic_tests.c

3408

XML_Parser ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/basic_tests.c

5837

external_inherited_parser(XML_Parser p, const XML_Char *context,

lib/libexpat/tests/basic_tests.c

5855

XML_Parser parser = XML_ExternalEntityParserCreate(p, context, NULL);

lib/libexpat/tests/handlers.c

1009

external_entity_not_standalone(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1022

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1046

external_entity_value_aborter(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1060

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1083

external_entity_public(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1093

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1110

external_entity_devaluer(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1125

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1139

external_entity_oneshot_loader(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1148

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1164

external_entity_loader2(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1173

extparser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1191

external_entity_faulter2(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1200

extparser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1219

external_entity_unfinished_attlist(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1233

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1246

external_entity_handler(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1266

p2 = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1277

external_entity_duff_loader(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1290

new_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1309

external_entity_dbl_handler(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1328

new_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1341

new_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1366

external_entity_dbl_handler_2(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1384

new_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1392

new_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1404

external_entity_alloc_set_encoding(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1417

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1433

external_entity_reallocator(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1444

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1461

external_entity_alloc(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

1471

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

1482

const XML_Char *context,

lib/libexpat/tests/handlers.c

1490

if (context != NULL)

lib/libexpat/tests/handlers.c

1500

= XML_ExternalEntityParserCreate(parser, context, encodingName);

lib/libexpat/tests/handlers.c

1512

const XML_Char *context,

lib/libexpat/tests/handlers.c

1532

XML_Parser entParser = XML_ExternalEntityParserCreate(parser, context, 0);

lib/libexpat/tests/handlers.c

423

external_entity_optioner(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

434

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

449

external_entity_loader(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

458

extparser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

476

external_entity_faulter(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

485

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

504

external_entity_null_loader(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

508

UNUSED_P(context);

lib/libexpat/tests/handlers.c

516

external_entity_resetter(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

526

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

575

external_entity_suspender(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

584

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

611

external_entity_suspend_xmldecl(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

622

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

648

external_entity_suspending_faulter(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

660

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

686

const XML_Char *context,

lib/libexpat/tests/handlers.c

691

UNUSED_P(context);

lib/libexpat/tests/handlers.c

703

external_entity_cr_catcher(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

712

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

724

external_entity_bad_cr_catcher(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

733

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

747

external_entity_rsqb_catcher(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

756

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

770

external_entity_good_cdata_ascii(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

782

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

798

external_entity_param_checker(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

808

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

823

external_entity_ref_param_checker(XML_Parser parameter, const XML_Char *context,

lib/libexpat/tests/handlers.c

837

ext_parser = XML_ExternalEntityParserCreate(g_parser, context, NULL);

lib/libexpat/tests/handlers.c

849

external_entity_param(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

865

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

890

external_entity_load_ignore(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

899

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

911

external_entity_load_ignore_utf16(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

925

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

937

external_entity_load_ignore_utf16_be(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

951

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.c

963

external_entity_valuer(XML_Parser parser, const XML_Char *context,

lib/libexpat/tests/handlers.c

976

ext_parser = XML_ExternalEntityParserCreate(parser, context, NULL);

lib/libexpat/tests/handlers.h

173

const XML_Char *context,

lib/libexpat/tests/handlers.h

179

const XML_Char *context,

lib/libexpat/tests/handlers.h

192

const XML_Char *context,

lib/libexpat/tests/handlers.h

197

XML_Parser parser, const XML_Char *context, const XML_Char *base,

lib/libexpat/tests/handlers.h

200

const XML_Char *context,

lib/libexpat/tests/handlers.h

206

const XML_Char *context,

lib/libexpat/tests/handlers.h

212

const XML_Char *context,

lib/libexpat/tests/handlers.h

218

const XML_Char *context,

lib/libexpat/tests/handlers.h

224

const XML_Char *context,

lib/libexpat/tests/handlers.h

230

const XML_Char *context,

lib/libexpat/tests/handlers.h

236

const XML_Char *context,

lib/libexpat/tests/handlers.h

242

const XML_Char *context,

lib/libexpat/tests/handlers.h

248

const XML_Char *context,

lib/libexpat/tests/handlers.h

265

const XML_Char *context,

lib/libexpat/tests/handlers.h

271

const XML_Char *context,

lib/libexpat/tests/handlers.h

277

const XML_Char *context,

lib/libexpat/tests/handlers.h

283

const XML_Char *context,

lib/libexpat/tests/handlers.h

289

const XML_Char *context,

lib/libexpat/tests/handlers.h

295

XML_Parser parser, const XML_Char *context, const XML_Char *base,

lib/libexpat/tests/handlers.h

299

const XML_Char *context,

lib/libexpat/tests/handlers.h

305

const XML_Char *context,

lib/libexpat/tests/handlers.h

311

const XML_Char *context,

lib/libexpat/tests/handlers.h

317

const XML_Char *context,

lib/libexpat/tests/handlers.h

323

const XML_Char *context,

lib/libexpat/tests/handlers.h

335

const XML_Char *context,

lib/libexpat/tests/handlers.h

348

const XML_Char *context,

lib/libexpat/tests/handlers.h

362

const XML_Char *context,

lib/libexpat/tests/handlers.h

368

const XML_Char *context,

lib/libexpat/tests/handlers.h

374

const XML_Char *context,

lib/libexpat/tests/handlers.h

380

const XML_Char *context,

lib/libexpat/tests/handlers.h

386

const XML_Char *context,

lib/libexpat/tests/handlers.h

392

const XML_Char *context,

lib/libexpat/tests/handlers.h

398

const XML_Char *context,

lib/libexpat/tests/handlers.h

404

const XML_Char *context,

lib/libexpat/tests/handlers.h

410

const XML_Char *context,

lib/libexpat/tests/handlers.h

416

XML_Parser parser, const XML_Char *context, const XML_Char *base,

lib/libexpat/tests/handlers.h

427

const XML_Char *context,

lib/libexpat/tests/minicheck.c

179

handle_failure(SRunner *runner, int verbosity, const char *context,

lib/libexpat/tests/minicheck.c

186

printf("FAIL [%s]: %s (%s at %s:%d)\n", context, _check_current_function,

lib/libexpat/tests/minicheck.c

192

srunner_run_all(SRunner *runner, const char *context, int verbosity) {

lib/libexpat/tests/minicheck.c

207

handle_failure(runner, verbosity, context, "during setup");

lib/libexpat/tests/minicheck.c

214

handle_failure(runner, verbosity, context, "during actual test");

lib/libexpat/tests/minicheck.c

223

handle_failure(runner, verbosity, context, "during teardown");

lib/libexpat/tests/minicheck.h

145

void srunner_run_all(SRunner *runner, const char *context, int verbosity);

lib/libexpat/tests/misc_tests.c

633

const char *const context = XML_GetInputContext(parser, &offset, &size);

lib/libexpat/tests/misc_tests.c

636

assert_true(context != NULL);

lib/libexpat/tests/misc_tests.c

639

return portable_strndup(context + offset, byte_count);

lib/libexpat/tests/misc_tests.c

641

assert_true(context == NULL);

lib/libexpat/tests/runtests.c

103

char context[100];

lib/libexpat/tests/runtests.c

107

snprintf(context, sizeof(context), "chunksize=%d deferral=%d",

lib/libexpat/tests/runtests.c

109

context[sizeof(context) - 1] = '\0';

lib/libexpat/tests/runtests.c

110

srunner_run_all(sr, context, verbosity);

lib/libssl/ssl_lib.c

1999

const char *label, size_t label_len, const unsigned char *context,

lib/libssl/ssl_lib.c

2004

context = NULL;

lib/libssl/ssl_lib.c

2007

return tls13_exporter(s->tls13, label, label_len, context,

lib/libssl/ssl_lib.c

2011

return tls12_exporter(s, label, label_len, context, context_len,

lib/libssl/tls12_key_schedule.c

212

CBB cbb, context;

lib/libssl/tls12_key_schedule.c

247

if (!CBB_add_u16_length_prefixed(&cbb, &context))

lib/libssl/tls12_key_schedule.c

250

if (!CBB_add_bytes(&context, context_value,

lib/libssl/tls13_client.c

1008

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_client.c

1024

&context))

lib/libssl/tls13_client.c

348

struct tls13_secret context;

lib/libssl/tls13_client.c

380

context.data = buf;

lib/libssl/tls13_client.c

381

context.len = hash_len;

lib/libssl/tls13_client.c

385

secrets->zeros.len, &context))

lib/libssl/tls13_client.c

390

shared_key_len, &context))

lib/libssl/tls13_client.c

725

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_client.c

744

&context))

lib/libssl/tls13_client.c

783

context.data = transcript_hash;

lib/libssl/tls13_client.c

784

context.len = transcript_hash_len;

lib/libssl/tls13_client.c

786

if (!tls13_derive_application_secrets(secrets, &context))

lib/libssl/tls13_internal.h

152

const struct tls13_secret *context);

lib/libssl/tls13_internal.h

155

const uint8_t *label, size_t label_len, const struct tls13_secret *context);

lib/libssl/tls13_internal.h

159

const struct tls13_secret *context);

lib/libssl/tls13_internal.h

162

const uint8_t *label, size_t label_len, const struct tls13_secret *context);

lib/libssl/tls13_internal.h

165

size_t psk_len, const struct tls13_secret *context);

lib/libssl/tls13_internal.h

167

const uint8_t *ecdhe, size_t ecdhe_len, const struct tls13_secret *context);

lib/libssl/tls13_internal.h

169

const struct tls13_secret *context);

lib/libssl/tls13_key_schedule.c

161

const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

164

strlen(label), context);

lib/libssl/tls13_key_schedule.c

170

const uint8_t *label, size_t label_len, const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

194

if (!CBB_add_bytes(&child, context->data, context->len))

lib/libssl/tls13_key_schedule.c

212

const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

214

return tls13_hkdf_expand_label(out, digest, secret, label, context);

lib/libssl/tls13_key_schedule.c

220

size_t label_len, const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

223

label_len, context);

lib/libssl/tls13_key_schedule.c

228

uint8_t *psk, size_t psk_len, const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

248

context))

lib/libssl/tls13_key_schedule.c

252

context))

lib/libssl/tls13_key_schedule.c

270

const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

292

context))

lib/libssl/tls13_key_schedule.c

296

context))

lib/libssl/tls13_key_schedule.c

315

const struct tls13_secret *context)

lib/libssl/tls13_key_schedule.c

337

context))

lib/libssl/tls13_key_schedule.c

341

context))

lib/libssl/tls13_key_schedule.c

345

context))

lib/libssl/tls13_key_schedule.c

349

context))

lib/libssl/tls13_key_schedule.c

365

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_key_schedule.c

373

"traffic upd", &context);

lib/libssl/tls13_key_schedule.c

379

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_key_schedule.c

387

"traffic upd", &context);

lib/libssl/tls13_key_schedule.c

395

struct tls13_secret context, export_out, export_secret;

lib/libssl/tls13_key_schedule.c

406

memset(&context, 0, sizeof(context));

lib/libssl/tls13_key_schedule.c

421

if (!tls13_secret_init(&context, md_len))

lib/libssl/tls13_key_schedule.c

436

if (!EVP_DigestFinal_ex(md_ctx, context.data, &md_out_len))

lib/libssl/tls13_key_schedule.c

447

&export_secret, "exporter", &context))

lib/libssl/tls13_key_schedule.c

454

tls13_secret_cleanup(&context);

lib/libssl/tls13_record_layer.c

470

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_record_layer.c

486

if (!tls13_hkdf_expand_label(&rp->iv, hash, traffic_key, "iv", &context))

lib/libssl/tls13_record_layer.c

488

if (!tls13_hkdf_expand_label(&key, hash, traffic_key, "key", &context))

lib/libssl/tls13_server.c

1023

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_server.c

1040

&context))

lib/libssl/tls13_server.c

374

struct tls13_secret context;

lib/libssl/tls13_server.c

403

context.data = buf;

lib/libssl/tls13_server.c

404

context.len = hash_len;

lib/libssl/tls13_server.c

408

secrets->zeros.len, &context))

lib/libssl/tls13_server.c

413

shared_key_len, &context))

lib/libssl/tls13_server.c

786

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_server.c

802

&context))

lib/libssl/tls13_server.c

843

struct tls13_secret context = { .data = "", .len = 0 };

lib/libssl/tls13_server.c

848

context.data = ctx->hs->tls13.transcript_hash;

lib/libssl/tls13_server.c

849

context.len = ctx->hs->tls13.transcript_hash_len;

lib/libssl/tls13_server.c

851

if (!tls13_derive_application_secrets(secrets, &context))

libexec/login_radius/raddauth.c

356

MD5_CTX context;

libexec/login_radius/raddauth.c

406

MD5_Init(&context);

libexec/login_radius/raddauth.c

407

MD5_Update(&context, md5buf, secretlen + AUTH_VECTOR_LEN);

libexec/login_radius/raddauth.c

408

MD5_Final(digest, &context);

libexec/login_radius/raddauth.c

470

MD5_CTX context;

libexec/login_radius/raddauth.c

493

MD5_Init(&context);

libexec/login_radius/raddauth.c

494

MD5_Update(&context, (u_char *)&auth, ntohs(auth.length));

libexec/login_radius/raddauth.c

495

MD5_Update(&context, auth_secret, strlen(auth_secret));

libexec/login_radius/raddauth.c

496

MD5_Final(test_vector, &context);

libexec/snmpd/snmpd_metrics/mib.c

3242

char *context = NULL;

libexec/snmpd/snmpd_metrics/mib.c

3286

context = optarg;

libexec/snmpd/snmpd_metrics/mib.c

3333

if ((sac = agentx_context(sas, context)) == NULL)

regress/lib/libpthread/pthread_kill/pthread_kill.c

18

act_handler(int signal, siginfo_t *siginfo, void *context)

regress/lib/libpthread/pthread_kill/pthread_kill.c

28

signal, siginfo, context);

regress/lib/libpthread/siginfo/siginfo.c

19

act_handler(int signal, siginfo_t *siginfo, void *context)

regress/lib/libpthread/siginfo/siginfo.c

28

context, siginfo->si_addr, siginfo->si_code,

regress/lib/libpthread/signodefer/signodefer.c

19

act_handler(int signal, siginfo_t *siginfo, void *context)

regress/lib/libpthread/signodefer/signodefer.c

33

sigcount, signal, siginfo, context);

regress/lib/libssl/interop/botan/client.cpp

124

const std::string &type, const std::string &context)

regress/lib/libssl/interop/server.c

211

uint32_t context;

regress/lib/libssl/interop/server.c

214

context = arc4random();

regress/lib/libssl/interop/server.c

216

(unsigned char *)&context, sizeof(context)) <= 0)

regress/sys/btcfi/foobar.c

18

handler(int sig, siginfo_t *si, void *context)

regress/sys/dev/kcov/kcov.c

280

test_close(struct context *ctx)

regress/sys/dev/kcov/kcov.c

293

test_coverage(struct context *ctx)

regress/sys/dev/kcov/kcov.c

304

struct context *ctx = arg;

regress/sys/dev/kcov/kcov.c

314

test_dying(struct context *ctx)

regress/sys/dev/kcov/kcov.c

343

test_exec(struct context *ctx)

regress/sys/dev/kcov/kcov.c

379

test_fdsend(struct context *ctx)

regress/sys/dev/kcov/kcov.c

412

test_fork(struct context *ctx)

regress/sys/dev/kcov/kcov.c

43

static int test_close(struct context *);

regress/sys/dev/kcov/kcov.c

44

static int test_coverage(struct context *);

regress/sys/dev/kcov/kcov.c

447

test_open(struct context *ctx)

regress/sys/dev/kcov/kcov.c

45

static int test_dying(struct context *);

regress/sys/dev/kcov/kcov.c

46

static int test_exec(struct context *);

regress/sys/dev/kcov/kcov.c

47

static int test_fdsend(struct context *);

regress/sys/dev/kcov/kcov.c

479

test_remote(struct context *ctx)

regress/sys/dev/kcov/kcov.c

48

static int test_fork(struct context *);

regress/sys/dev/kcov/kcov.c

49

static int test_open(struct context *);

regress/sys/dev/kcov/kcov.c

50

static int test_remote(struct context *);

regress/sys/dev/kcov/kcov.c

51

static int test_remote_close(struct context *);

regress/sys/dev/kcov/kcov.c

52

static int test_remote_interrupt(struct context *);

regress/sys/dev/kcov/kcov.c

523

test_remote_close(struct context *ctx)

regress/sys/dev/kcov/kcov.c

53

static int test_state(struct context *);

regress/sys/dev/kcov/kcov.c

547

test_remote_interrupt(struct context *ctx)

regress/sys/dev/kcov/kcov.c

571

test_state(struct context *ctx)

regress/sys/dev/kcov/kcov.c

70

int (*fn)(struct context *);

regress/sys/dev/kcov/kcov.c

86

struct context ctx;

regress/sys/kern/noexec/noexec.c

191

struct context *ctx = arg;

regress/sys/kern/noexec/noexec.c

347

struct context ctx = {.argc = argc, .argv = argv};

regress/sys/kern/pipe/test-close.c

45

struct context ctx1, ctx2;

regress/sys/kern/pipe/test-close.c

89

const struct context *ctx = arg;

regress/sys/kern/pipe/test-kqueue.c

123

struct context ctx;

regress/sys/kern/pipe/test-kqueue.c

164

ctx_setup(struct context *ctx, enum kqueue_mode mode, int flags)

regress/sys/kern/pipe/test-kqueue.c

194

ctx_teardown(struct context *ctx)

regress/sys/kern/pipe/test-kqueue.c

214

ctx_thread_alive(struct context *ctx)

regress/sys/kern/pipe/test-kqueue.c

225

ctx_thread_start(struct context *ctx)

regress/sys/kern/pipe/test-kqueue.c

235

ctx_lock(struct context *ctx)

regress/sys/kern/pipe/test-kqueue.c

245

ctx_unlock(struct context *ctx)

regress/sys/kern/pipe/test-kqueue.c

257

struct context *ctx = arg;

regress/sys/kern/pipe/test-kqueue.c

53

static void ctx_setup(struct context *, enum kqueue_mode, int);

regress/sys/kern/pipe/test-kqueue.c

54

static void ctx_teardown(struct context *);

regress/sys/kern/pipe/test-kqueue.c

55

static int ctx_thread_alive(struct context *);

regress/sys/kern/pipe/test-kqueue.c

56

static void ctx_thread_start(struct context *);

regress/sys/kern/pipe/test-kqueue.c

57

static void ctx_lock(struct context *);

regress/sys/kern/pipe/test-kqueue.c

58

static void ctx_unlock(struct context *);

regress/sys/kern/pipe/test-kqueue.c

68

struct context ctx;

regress/sys/kern/pipe/test-kqueue.c

99

struct context ctx;

regress/sys/kern/pipe/test-run-down.c

103

ctx_teardown(struct context *ctx)

regress/sys/kern/pipe/test-run-down.c

126

ctx_lock(struct context *ctx)

regress/sys/kern/pipe/test-run-down.c

136

ctx_unlock(struct context *ctx)

regress/sys/kern/pipe/test-run-down.c

148

struct context ctx;

regress/sys/kern/pipe/test-run-down.c

188

struct context *ctx = arg;

regress/sys/kern/pipe/test-run-down.c

37

static void ctx_setup(struct context *, size_t);

regress/sys/kern/pipe/test-run-down.c

38

static void ctx_teardown(struct context *);

regress/sys/kern/pipe/test-run-down.c

39

static void ctx_lock(struct context *);

regress/sys/kern/pipe/test-run-down.c

40

static void ctx_unlock(struct context *);

regress/sys/kern/pipe/test-run-down.c

80

ctx_setup(struct context *ctx, size_t bufsiz)

regress/sys/kern/pipe/test-thundering-herd.c

157

block_proc(const struct context *ctx)

regress/sys/kern/pipe/test-thundering-herd.c

54

static pid_t block_proc(const struct context *);

regress/sys/kern/pipe/test-thundering-herd.c

88

struct context ctx;

regress/sys/uvm/vnode/extern.h

26

int ctx_abort(struct context *);

regress/sys/uvm/vnode/extern.h

30

int test_deadlock(struct context *);

regress/sys/uvm/vnode/test-deadlock.c

45

test_deadlock(struct context *ctx)

regress/sys/uvm/vnode/vnode.c

42

int (*t_func)(struct context *);

regress/sys/uvm/vnode/vnode.c

48

struct context ctx;

regress/sys/uvm/vnode/vnode.c

91

ctx_abort(struct context *ctx)

sbin/isakmpd/message.c

1091

u_int8_t proto = GET_ISAKMP_PROP_PROTO(p->context->p);

sbin/isakmpd/message.c

1092

u_int8_t *prop = p->context->p;

sbin/isakmpd/message.c

1178

payload_node->context = p;

sbin/isakmpd/message.c

2093

*propp = tp->context;

sbin/isakmpd/message.c

2094

*sap = (*propp)->context;

sbin/isakmpd/message.c

2138

propp = tp->context;

sbin/isakmpd/message.c

2139

sap = propp->context;

sbin/isakmpd/message.c

2367

GET_ISAKMP_PROP_PROTO(proto->chosen->context->p),

sbin/isakmpd/message.c

2386

memcpy(proposals[i], proto->chosen->context->p,

sbin/isakmpd/message.c

949

u_int8_t *sa = p->context->p;

sbin/isakmpd/message.h

60

struct payload *context;

sbin/isakmpd/sa.c

1030

if (match->proto != GET_ISAKMP_PROP_PROTO(xf->context->p)) {

sbin/isakmpd/sa.c

1093

struct payload *prop = xf->context;

sbin/pfctl/parse.y

4120

MD5_CTX context;

sbin/pfctl/parse.y

4125

MD5Init(&context);

sbin/pfctl/parse.y

4126

MD5Update(&context, (unsigned char *)$1,

sbin/pfctl/parse.y

4128

MD5Final((unsigned char *)$$, &context);

sbin/restore/dirs.c

117

static struct inotab *allocinotab(FILE *, struct context *, long);

sbin/restore/dirs.c

683

allocinotab(FILE *mf, struct context *ctxp, long seekpt)

sbin/restore/tape.c

81

struct context curfile; /* describes next file available on the tape */

sys/arch/arm64/dev/rtkit.c

547

char context[24];

sys/arch/arm64/dev/rtkit.c

563

memcpy(context, syslog_msg, sizeof(context));

sys/arch/arm64/dev/rtkit.c

564

context[sizeof(context) - 1] = 0;

sys/arch/arm64/dev/rtkit.c

566

syslog_msg += sizeof(context);

sys/arch/arm64/dev/rtkit.c

579

printf("RTKit syslog %d: %s:%s\n", idx, context, state->syslog_msg);

sys/arch/arm64/stand/efiboot/efiboot.c

809

efi_timer(EFI_EVENT event, VOID *context)

sys/arch/armv7/stand/efiboot/efiboot.c

719

efi_timer(EFI_EVENT event, VOID *context)

sys/arch/riscv64/dev/plic.c

171

int context;

sys/arch/riscv64/dev/plic.c

249

for (i = 0, context = 0; i < ncell; i += 2, context++) {

sys/arch/riscv64/dev/plic.c

272

context * PLIC_ENABLE_STRIDE;

sys/arch/riscv64/dev/plic.c

274

context * PLIC_CONTEXT_STRIDE;

sys/arch/riscv64/stand/efiboot/efiboot.c

695

efi_timer(EFI_EVENT event, VOID *context)

sys/arch/sparc64/include/hypervisor.h

56

int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags);

sys/arch/sparc64/include/hypervisor.h

57

int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags);

sys/arch/sparc64/include/hypervisor.h

60

int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte,

sys/arch/sparc64/include/hypervisor.h

62

int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags);

sys/crypto/sha1.c

109

SHA1Init(SHA1_CTX *context)

sys/crypto/sha1.c

112

context->count = 0;

sys/crypto/sha1.c

113

context->state[0] = 0x67452301;

sys/crypto/sha1.c

114

context->state[1] = 0xEFCDAB89;

sys/crypto/sha1.c

115

context->state[2] = 0x98BADCFE;

sys/crypto/sha1.c

116

context->state[3] = 0x10325476;

sys/crypto/sha1.c

117

context->state[4] = 0xC3D2E1F0;

sys/crypto/sha1.c

124

SHA1Update(SHA1_CTX *context, const void *dataptr, unsigned int len)

sys/crypto/sha1.c

130

j = (u_int32_t)((context->count >> 3) & 63);

sys/crypto/sha1.c

131

context->count += (len << 3);

sys/crypto/sha1.c

133

memcpy(&context->buffer[j], data, (i = 64 - j));

sys/crypto/sha1.c

134

SHA1Transform(context->state, context->buffer);

sys/crypto/sha1.c

136

SHA1Transform(context->state, &data[i]);

sys/crypto/sha1.c

141

memcpy(&context->buffer[j], &data[i], len - i);

sys/crypto/sha1.c

148

SHA1Final(unsigned char digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context)

sys/crypto/sha1.c

154

finalcount[i] = (unsigned char)((context->count >>

sys/crypto/sha1.c

157

SHA1Update(context, "\200", 1);

sys/crypto/sha1.c

158

while ((context->count & 504) != 448) {

sys/crypto/sha1.c

159

SHA1Update(context, "\0", 1);

sys/crypto/sha1.c

161

SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */

sys/crypto/sha1.c

164

digest[i] = (unsigned char)((context->state[i >> 2] >>

sys/crypto/sha1.c

168

explicit_bzero(context, sizeof(*context));

sys/crypto/sha1.h

21

void SHA1Init(SHA1_CTX * context);

sys/crypto/sha1.h

23

void SHA1Update(SHA1_CTX *context, const void *data, unsigned int len);

sys/crypto/sha1.h

24

void SHA1Final(unsigned char digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context);

sys/crypto/sha2.c

257

SHA256Init(SHA2_CTX *context)

sys/crypto/sha2.c

259

memcpy(context->state.st32, sha256_initial_hash_value,

sys/crypto/sha2.c

261

memset(context->buffer, 0, SHA256_BLOCK_LENGTH);

sys/crypto/sha2.c

262

context->bitcount[0] = 0;

sys/crypto/sha2.c

426

SHA256Update(SHA2_CTX *context, const void *dataptr, size_t len)

sys/crypto/sha2.c

435

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

sys/crypto/sha2.c

442

memcpy(&context->buffer[usedspace], data, freespace);

sys/crypto/sha2.c

443

context->bitcount[0] += freespace << 3;

sys/crypto/sha2.c

446

SHA256Transform(context->state.st32, context->buffer);

sys/crypto/sha2.c

449

memcpy(&context->buffer[usedspace], data, len);

sys/crypto/sha2.c

450

context->bitcount[0] += len << 3;

sys/crypto/sha2.c

458

SHA256Transform(context->state.st32, data);

sys/crypto/sha2.c

459

context->bitcount[0] += SHA256_BLOCK_LENGTH << 3;

sys/crypto/sha2.c

465

memcpy(context->buffer, data, len);

sys/crypto/sha2.c

466

context->bitcount[0] += len << 3;

sys/crypto/sha2.c

473

SHA256Final(u_int8_t *digest, SHA2_CTX *context)

sys/crypto/sha2.c

477

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

sys/crypto/sha2.c

480

context->bitcount[0] = swap64(context->bitcount[0]);

sys/crypto/sha2.c

484

context->buffer[usedspace++] = 0x80;

sys/crypto/sha2.c

488

memset(&context->buffer[usedspace], 0,

sys/crypto/sha2.c

492

memset(&context->buffer[usedspace], 0,

sys/crypto/sha2.c

496

SHA256Transform(context->state.st32, context->buffer);

sys/crypto/sha2.c

499

memset(context->buffer, 0,

sys/crypto/sha2.c

504

memset(context->buffer, 0, SHA256_SHORT_BLOCK_LENGTH);

sys/crypto/sha2.c

507

*context->buffer = 0x80;

sys/crypto/sha2.c

510

*(u_int64_t *)&context->buffer[SHA256_SHORT_BLOCK_LENGTH] = context->bitcount[0];

sys/crypto/sha2.c

513

SHA256Transform(context->state.st32, context->buffer);

sys/crypto/sha2.c

520

context->state.st32[j] = swap32(context->state.st32[j]);

sys/crypto/sha2.c

524

memcpy(digest, context->state.st32, SHA256_DIGEST_LENGTH);

sys/crypto/sha2.c

526

explicit_bzero(context, sizeof(*context));

sys/crypto/sha2.c

533

SHA512Init(SHA2_CTX *context)

sys/crypto/sha2.c

535

memcpy(context->state.st64, sha512_initial_hash_value,

sys/crypto/sha2.c

537

memset(context->buffer, 0, SHA512_BLOCK_LENGTH);

sys/crypto/sha2.c

538

context->bitcount[0] = context->bitcount[1] = 0;

sys/crypto/sha2.c

706

SHA512Update(SHA2_CTX *context, const void *dataptr, size_t len)

sys/crypto/sha2.c

715

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

sys/crypto/sha2.c

722

memcpy(&context->buffer[usedspace], data, freespace);

sys/crypto/sha2.c

723

ADDINC128(context->bitcount, freespace << 3);

sys/crypto/sha2.c

726

SHA512Transform(context->state.st64, context->buffer);

sys/crypto/sha2.c

729

memcpy(&context->buffer[usedspace], data, len);

sys/crypto/sha2.c

730

ADDINC128(context->bitcount, len << 3);

sys/crypto/sha2.c

738

SHA512Transform(context->state.st64, data);

sys/crypto/sha2.c

739

ADDINC128(context->bitcount, SHA512_BLOCK_LENGTH << 3);

sys/crypto/sha2.c

745

memcpy(context->buffer, data, len);

sys/crypto/sha2.c

746

ADDINC128(context->bitcount, len << 3);

sys/crypto/sha2.c

753

SHA512Last(SHA2_CTX *context)

sys/crypto/sha2.c

757

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

sys/crypto/sha2.c

760

context->bitcount[0] = swap64(context->bitcount[0]);

sys/crypto/sha2.c

761

context->bitcount[1] = swap64(context->bitcount[1]);

sys/crypto/sha2.c

765

context->buffer[usedspace++] = 0x80;

sys/crypto/sha2.c

769

memset(&context->buffer[usedspace], 0,

sys/crypto/sha2.c

773

memset(&context->buffer[usedspace], 0,

sys/crypto/sha2.c

777

SHA512Transform(context->state.st64, context->buffer);

sys/crypto/sha2.c

780

memset(context->buffer, 0, SHA512_BLOCK_LENGTH - 2);

sys/crypto/sha2.c

784

memset(context->buffer, 0, SHA512_SHORT_BLOCK_LENGTH);

sys/crypto/sha2.c

787

*context->buffer = 0x80;

sys/crypto/sha2.c

790

*(u_int64_t *)&context->buffer[SHA512_SHORT_BLOCK_LENGTH] = context->bitcount[1];

sys/crypto/sha2.c

791

*(u_int64_t *)&context->buffer[SHA512_SHORT_BLOCK_LENGTH+8] = context->bitcount[0];

sys/crypto/sha2.c

794

SHA512Transform(context->state.st64, context->buffer);

sys/crypto/sha2.c

798

SHA512Final(u_int8_t *digest, SHA2_CTX *context)

sys/crypto/sha2.c

801

SHA512Last(context);

sys/crypto/sha2.c

809

context->state.st64[j] = swap64(context->state.st64[j]);

sys/crypto/sha2.c

813

memcpy(digest, context->state.st64, SHA512_DIGEST_LENGTH);

sys/crypto/sha2.c

816

explicit_bzero(context, sizeof(*context));

sys/crypto/sha2.c

822

SHA384Init(SHA2_CTX *context)

sys/crypto/sha2.c

824

memcpy(context->state.st64, sha384_initial_hash_value,

sys/crypto/sha2.c

826

memset(context->buffer, 0, SHA384_BLOCK_LENGTH);

sys/crypto/sha2.c

827

context->bitcount[0] = context->bitcount[1] = 0;

sys/crypto/sha2.c

831

SHA384Update(SHA2_CTX *context, const void *data, size_t len)

sys/crypto/sha2.c

833

SHA512Update(context, data, len);

sys/crypto/sha2.c

837

SHA384Final(u_int8_t *digest, SHA2_CTX *context)

sys/crypto/sha2.c

840

SHA512Last(context);

sys/crypto/sha2.c

848

context->state.st64[j] = swap64(context->state.st64[j]);

sys/crypto/sha2.c

852

memcpy(digest, context->state.st64, SHA384_DIGEST_LENGTH);

sys/crypto/sha2.c

854

explicit_bzero(context, sizeof(*context));

sys/dev/ic/aac.c

648

aac_complete(void *context)

sys/dev/ic/aac.c

650

struct aac_softc *sc = (struct aac_softc *)context;

sys/dev/ic/athvar.h

368

#define ATH_TASK_INIT(task, func, context) \

sys/dev/ic/athvar.h

371

(task)->t_context = (context); \

sys/dev/ic/dwhdmi.c

739

struct dwhdmi_softc * const sc = arg->context;

sys/dev/ic/dwhdmi.c

763

pfil->context = sc;

sys/dev/pci/arc.c

1198

cmd->context = ccb->ccb_cmd_post;

sys/dev/pci/arc.c

482

u_int32_t context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

934

struct aca_dump_context context = {

sys/dev/pci/drm/amd/amdgpu/amdgpu_aca.c

939

return aca_banks_update(adev, type, handler_aca_bank_dump, NULL, (void *)&context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

189

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

63

struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

80

context, atomic_inc_return(&fence_seq));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

3061

process_info->eviction_fence->base.context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

383

dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

411

dma_resv_replace_fences(resv, fence->context, stub,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

128

adev->psp.xgmi_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

129

adev->psp.xgmi_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

131

adev->psp.ras_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

132

adev->psp.ras_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

134

adev->psp.hdcp_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

135

adev->psp.hdcp_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

137

adev->psp.dtm_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

138

adev->psp.dtm_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

140

adev->psp.rap_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

141

adev->psp.rap_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

144

adev->psp.securedisplay_context.context.bin_desc.feature_version,

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

145

adev->psp.securedisplay_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

792

else if (fence->context == af->context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

850

if (!guilty_fence || (fence->context != guilty_fence->context))

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

152

job->base.s_fence->scheduled.context : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

162

af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

298

((*id)->last_flush->context != fence_context &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.c

371

((*id)->last_flush->context != fence_context &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

289

fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

290

fw_info->feature = adev->psp.xgmi_context.context

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

294

fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

295

fw_info->feature = adev->psp.ras_context.context

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

299

fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

300

fw_info->feature = adev->psp.hdcp_context.context

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

304

fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

305

fw_info->feature = adev->psp.dtm_context.context

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

309

fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

310

fw_info->feature = adev->psp.rap_context.context

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

314

fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

316

adev->psp.securedisplay_context.context.bin_desc

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1258

int psp_ta_unload(struct psp_context *psp, struct ta_context *context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1263

psp_prep_ta_unload_cmd_buf(cmd, context->session_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1267

context->resp_status = cmd->resp.status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1322

struct ta_context *context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1324

cmd->cmd_id = context->ta_load_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1327

cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1330

lower_32_bits(context->mem_context.shared_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1332

upper_32_bits(context->mem_context.shared_mc_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1333

cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1362

struct ta_context *context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1367

psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1372

context->resp_status = cmd->resp.status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1379

int psp_ta_load(struct psp_context *psp, struct ta_context *context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1386

psp_copy_fw(psp, context->bin_desc.start_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1387

context->bin_desc.size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1390

context->mem_context.shared_bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1391

context->mem_context.shared_mc_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1392

amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1394

psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1399

context->resp_status = cmd->resp.status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1402

context->session_id = cmd->resp.session_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1411

return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1425

if (!psp->xgmi_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1428

ret = psp_ta_unload(psp, &psp->xgmi_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1430

psp->xgmi_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1441

!psp->xgmi_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1442

!psp->xgmi_context.context.bin_desc.start_addr)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1448

psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1449

psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1451

if (!psp->xgmi_context.context.mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1452

ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1458

ret = psp_ta_load(psp, &psp->xgmi_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1460

psp->xgmi_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1466

xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1483

xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1503

xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1522

psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1592

xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1709

xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1731

(struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1767

ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1821

ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1829

ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1860

if (!psp->ras_context.context.initialized || !info)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1882

if (!psp->ras_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1885

ret = psp_ta_unload(psp, &psp->ras_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1887

psp->ras_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1907

if (!adev->psp.ras_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1908

!adev->psp.ras_context.context.bin_desc.start_addr) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1966

psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1967

psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1969

if (!psp->ras_context.context.mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1970

ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1975

ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1990

ret = psp_ta_load(psp, &psp->ras_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1993

psp->ras_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2000

psp->ras_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2014

if (!psp->ras_context.context.initialized || !info)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2063

if (!psp->ras_context.context.initialized ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2089

if (!psp->hdcp_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2090

!psp->hdcp_context.context.bin_desc.start_addr) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2095

psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2096

psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2098

if (!psp->hdcp_context.context.mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2099

ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2104

ret = psp_ta_load(psp, &psp->hdcp_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2106

psp->hdcp_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2121

if (!psp->hdcp_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2124

return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2137

if (!psp->hdcp_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2140

ret = psp_ta_unload(psp, &psp->hdcp_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2142

psp->hdcp_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2163

if (!psp->dtm_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2164

!psp->dtm_context.context.bin_desc.start_addr) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2169

psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2170

psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2172

if (!psp->dtm_context.context.mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2173

ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2178

ret = psp_ta_load(psp, &psp->dtm_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2180

psp->dtm_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2195

if (!psp->dtm_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2198

return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2211

if (!psp->dtm_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2214

ret = psp_ta_unload(psp, &psp->dtm_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2216

psp->dtm_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2234

if (!psp->rap_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2235

!psp->rap_context.context.bin_desc.start_addr) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2240

psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2241

psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2243

if (!psp->rap_context.context.mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2244

ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2249

ret = psp_ta_load(psp, &psp->rap_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2251

psp->rap_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2260

psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2275

if (!psp->rap_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2278

ret = psp_ta_unload(psp, &psp->rap_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2280

psp->rap_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2290

if (!psp->rap_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2300

psp->rap_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2306

ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2336

if (!psp->securedisplay_context.context.bin_desc.size_bytes ||

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2337

!psp->securedisplay_context.context.bin_desc.start_addr) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2352

psp->securedisplay_context.context.mem_context.shared_mem_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2354

psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2356

if (!psp->securedisplay_context.context.initialized) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2358

&psp->securedisplay_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2363

ret = psp_ta_load(psp, &psp->securedisplay_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2364

if (!ret && !psp->securedisplay_context.context.resp_status) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2365

psp->securedisplay_context.context.initialized = true;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2369

psp->securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2385

psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2395

psp->securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2411

if (!psp->securedisplay_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2414

ret = psp_ta_unload(psp, &psp->securedisplay_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2416

psp->securedisplay_context.context.initialized = false;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2425

if (!psp->securedisplay_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2433

ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

296

psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

299

psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

302

psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

305

psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

308

psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

311

psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3257

psp->xgmi_context.context.initialized) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3834

psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3835

psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3836

psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3839

psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3840

psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3841

psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3844

psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3845

psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3846

psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3849

psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3850

psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3851

psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3854

psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3855

psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3856

psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3859

psp->securedisplay_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3861

psp->securedisplay_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3863

psp->securedisplay_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3884

adev->psp.xgmi_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3886

adev->psp.xgmi_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3888

adev->psp.xgmi_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3892

adev->psp.ras_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3894

adev->psp.ras_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3896

adev->psp.ras_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3897

(uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3900

adev->psp.hdcp_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3902

adev->psp.hdcp_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3904

adev->psp.hdcp_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3908

adev->psp.dtm_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3910

adev->psp.dtm_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3912

adev->psp.dtm_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3913

(uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3916

adev->psp.securedisplay_context.context.bin_desc.fw_version =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3918

adev->psp.securedisplay_context.context.bin_desc.size_bytes =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3920

adev->psp.securedisplay_context.context.bin_desc.start_addr =

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3921

(uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

223

struct ta_context context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

228

struct ta_context context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

235

struct ta_context context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

551

int psp_ta_unload(struct psp_context *psp, struct ta_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

552

int psp_ta_load(struct psp_context *psp, struct ta_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

555

struct ta_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

154

struct ta_context *context = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

179

set_ta_context_funcs(psp, ta_type, &context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

191

if (!context->mem_context.shared_buf) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

192

ret = psp_ta_init_shared_buf(psp, &context->mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

200

if (ret || context->resp_status) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

203

ret, context->resp_status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

210

context->ta_type = ta_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

211

context->bin_desc.fw_version = get_bin_version(ta_bin);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

212

context->bin_desc.size_bytes = ta_bin_len;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

213

context->bin_desc.start_addr = ta_bin;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

222

if (ret || context->resp_status) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

224

ret, context->resp_status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

230

if (copy_to_user((char *)buf, (void *)&context->session_id, sizeof(uint32_t)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

235

if (ret && context->mem_context.shared_buf)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

236

psp_ta_free_shared_buf(&context->mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

252

struct ta_context *context = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

267

set_ta_context_funcs(psp, ta_type, &context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

268

context->session_id = ta_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

276

if (ret || context->resp_status) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

278

ret, context->resp_status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

283

if (context->mem_context.shared_buf)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

284

psp_ta_free_shared_buf(&context->mem_context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

301

struct ta_context *context = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

330

set_ta_context_funcs(psp, ta_type, &context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

332

if (!context || !context->initialized) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

344

context->session_id = ta_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

347

ret = prep_ta_mem_context(&context->mem_context, shared_buf, shared_buf_len);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

352

if (ret || context->resp_status) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

354

ret, context->resp_status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

361

if (copy_to_user((char *)&buf[copy_pos], context->mem_context.shared_buf, shared_buf_len))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

78

*pcontext = &psp->ras_context.context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rap.c

125

if (!adev->psp.rap_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_rap.c

81

adev->psp.rap_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

62

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

64

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

66

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

68

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

70

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_reset.h

85

struct amdgpu_reset_context *context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

149

u64 context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_securedisplay.c

181

if (!adev->psp.securedisplay_context.context.initialized)

sys/dev/pci/drm/amd/amdgpu/amdgpu_securedisplay.c

83

*cmd = (struct ta_securedisplay_cmd *)psp->securedisplay_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

137

hash_for_each_possible(sync->fences, e, node, f->context) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

144

if (likely(e->fence->context == f->context)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_sync.c

181

hash_add(sync->fences, &e->node, f->context);

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

171

__field(u64, context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

180

__entry->context = job->base.s_fence->finished.context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

186

__get_str(timeline), __entry->context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

195

__field(u64, context)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

203

__entry->context = job->base.s_fence->finished.context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

209

__get_str(timeline), __entry->context,

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

558

__entry->ctx = fence->context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

768

FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

769

FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

193

f->context, f->seqno);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

929

f->context, f->seqno);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

113

fence_drv->context = dma_fence_context_alloc(1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.c

274

fence_drv->context, seq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq_fence.h

50

u64 context;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

566

adev->psp.ras_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

568

adev->psp.xgmi_context.context.bin_desc.fw_version);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

910

af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0;

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

63

(psp->securedisplay_context.context.bin_desc.fw_version >=

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

65

adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

108

adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

120

adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

64

adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10670

if (dm_state && dm_state->context) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10671

dc_state = dm_state->context;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11363

dm_state->context,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11406

dm_state->context,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11824

dm_state->context)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11896

dm_state->context)) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12651

ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12660

ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12677

status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3079

struct dc_state *context __free(state_release) = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3087

context = dc_state_create_current_copy(dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3088

if (context == NULL)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3092

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3093

struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3102

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context))

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3105

res = dc_state_remove_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3110

params.streams = context->streams;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3111

params.stream_count = context->stream_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3502

dc_state_release(dm_state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3503

dm_state->context = dc_state_create(dm->dc, NULL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4809

if (old_state && old_state->context)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4810

new_state->context = dc_state_create_copy(old_state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4812

if (!new_state->context) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4825

if (dm_state && dm_state->context)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4826

dc_state_release(dm_state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4862

state->context = dc_state_create_current_copy(adev->dm.dc);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4863

if (!state->context) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4875

dc_state_release(state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4882

dc_state_release(state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4890

dc_state_release(state->context);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6865

static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6870

if (context->stream_count < 2)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6872

for (i = 0; i < context->stream_count ; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6873

if (!context->streams[i])

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6882

set_master_stream(context->streams, context->stream_count);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6884

for (i = 0; i < context->stream_count ; i++) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6885

stream = context->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

992

struct dc_state *context;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

362

if (!psp->securedisplay_context.context.initialized) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

113

if (!psp->hdcp_context.context.initialized) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

118

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

138

if (!psp->hdcp_context.context.initialized) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

143

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

501

if (!psp->dtm_context.context.initialized) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

506

dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1686

memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1689

struct dc_stream_state *stream = dm_state->context->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1738

struct dc_stream_state *stream = dm_state->context->streams[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1757

struct dc_stream_state *stream = dm_state->context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

55

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

60

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

61

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

62

const struct dc_stream_status *stream_status = &context->stream_status[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

67

if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

79

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

84

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/clk_mgr.c

85

const struct dc_stream_status stream_status = context->stream_status[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

165

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

171

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

196

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

201

int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

208

if (context->bw_ctx.bw.dce.dispclk_khz >

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

218

< context->bw_ctx.bw.dce.dispclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

390

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

392

struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

394

dce110_fill_display_configs(context, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

401

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

408

int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

410

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

422

dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

37

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

39

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

120

const struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

123

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

127

pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

132

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

135

const struct dc_stream_state *stream = context->streams[j];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

141

if (stream == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

142

pipe_ctx = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

179

&context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

197

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

199

struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

206

context->bw_ctx.bw.dce.all_displays_in_sync;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

208

context->bw_ctx.bw.dce.nbp_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

210

context->bw_ctx.bw.dce.cpuc_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

212

context->bw_ctx.bw.dce.cpup_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

214

context->bw_ctx.bw.dce.blackout_recovery_time_us;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

222

ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

228

pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

234

context->bw_ctx.bw.dce.sclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

243

pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

247

= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

249

dce110_fill_display_configs(context, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

256

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

261

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

267

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

276

context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

279

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

92

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

97

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

98

struct dc_stream_state *stream = context->streams[j];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

34

const struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

40

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

42

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

192

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

197

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

203

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

215

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

119

dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

85

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

90

int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

91

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

101

struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

103

dce110_fill_display_configs(context, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

110

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

117

int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

119

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

131

dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

99

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

188

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

194

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

209

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

105

struct dc_state *context, bool safe_to_lower)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

117

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

127

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

153

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

184

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

217

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

221

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

246

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

281

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

324

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

325

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

329

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

331

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

344

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

349

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

450

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

456

clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

459

clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

462

clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

465

clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

30

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

34

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

37

struct dc_state *context, bool safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

49

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

54

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

133

total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

160

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

161

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

165

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

167

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

85

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

89

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

107

struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

120

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

132

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

136

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

156

display_count = rn_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

217

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

227

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

240

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

55

static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

61

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

62

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

91

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

95

display_count = rn_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

194

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

198

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

223

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

304

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

305

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

309

dcn20_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

313

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

100

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

118

display_count = vg_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

173

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

180

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

64

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

70

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

71

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

96

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

114

static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

127

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

135

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

140

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

168

display_count = dcn31_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

225

dcn31_disable_otg_wa(clk_mgr_base, context, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

229

dcn31_disable_otg_wa(clk_mgr_base, context, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

236

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

244

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

638

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

641

display_count = dcn31_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

78

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

84

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

85

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

46

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

175

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

181

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

182

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

211

static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

219

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

229

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

274

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

279

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

289

display_count = dcn314_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

369

dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

378

dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

385

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

393

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

58

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

100

static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

117

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

126

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

131

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

141

display_count = dcn315_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

208

dcn315_disable_otg_wa(clk_mgr_base, context, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

216

dcn315_disable_otg_wa(clk_mgr_base, context, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

223

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

231

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

59

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

65

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

66

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

102

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

110

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

121

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

136

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

141

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

163

display_count = dcn316_get_active_display_cnt_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

216

dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

224

dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

231

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

239

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

71

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

77

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

78

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

267

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

315

struct dc_state *context, bool safe_to_lower)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

323

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

325

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

350

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

372

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

426

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

508

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

518

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

520

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

528

mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

622

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

626

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

652

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

729

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

808

dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

814

dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

815

dcn32_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

829

dcn32_update_clocks_update_dentist(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

834

dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

844

dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

36

struct dc_state *context, bool safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1196

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1199

display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1230

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1234

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1293

dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1295

dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

158

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

164

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

165

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

189

static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

200

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

204

? &context->res_ctx.pipe_ctx[i]

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

246

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

255

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

263

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

281

struct dc_state *context, bool safe_to_lower)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

291

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

293

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

300

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

341

static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

344

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

348

for (i = 0; i < context->stream_count; ++i) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

349

const struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

378

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

383

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

394

display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

435

dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

485

dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

494

dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

503

dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

509

dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

515

dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

520

dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

53

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1079

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1129

block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1160

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1166

block_sequence[num_steps].params.update_dentist_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1177

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1194

block_sequence[num_steps].params.update_dentist_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1199

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1219

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1228

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1229

&context->bw_ctx.bw.dcn.clk,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1237

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1238

&context->bw_ctx.bw.dcn.clk,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1245

dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1331

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1342

new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1343

new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1344

new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1352

context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

413

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

422

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

424

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

432

mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

525

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

534

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

536

&context->res_ctx, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

557

struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

565

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

567

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

569

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

574

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

615

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

736

params->update_dppclk_dto_params.context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

743

params->update_dtbclk_dto_params.context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

749

params->update_dentist_params.context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

766

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

787

int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

802

display_count = clk_mgr_helper_get_active_display_cnt(dc, context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

56

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

62

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

67

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1193

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1202

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1210

dc->hwss.interdependent_update_lock(dc, context, lock);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1213

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1226

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1260

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1312

static void disable_dangling_plane(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1329

if ((context->res_ctx.pipe_ctx[i].top_pipe) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1331

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=

sys/dev/pci/drm/amd/display/dc/core/dc.c

1334

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=

sys/dev/pci/drm/amd/display/dc/core/dc.c

1337

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1338

if (old_stream == context->streams[j]) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

1344

dc->current_state->stream_count != context->stream_count)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1352

new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1384

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1385

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

1422

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

1432

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

1987

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

1995

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2004

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2014

if (context != NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2015

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2017

context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2022

if (should_update_pipe_for_stream(context, pipe, streams[j]) &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2029

void dc_trigger_sync(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2031

if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2034

enable_timing_multisync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2035

program_timing_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2039

static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2045

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2072

static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2083

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2088

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2092

if (resource_calculate_det_for_stream(context, pipe) <

sys/dev/pci/drm/amd/display/dc/core/dc.c

2110

static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2132

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2133

dc_streams[i] = context->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2136

disable_vbios_mode_if_required(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2137

dc->hwss.enable_accelerated_mode(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2142

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2152

if (context->stream_count > get_seamless_boot_stream_count(context) ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2153

context->stream_count == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2154

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2160

dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2162

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2165

dc->hwss.update_dsc_pg(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2167

disable_dangling_plane(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2172

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2173

if (context->streams[i]->mode_changed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2175

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2177

dc, context->streams[i],

sys/dev/pci/drm/amd/display/dc/core/dc.c

2178

context->stream_status[i].plane_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2179

context); /* use new pipe config in new context */

sys/dev/pci/drm/amd/display/dc/core/dc.c

2180

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2181

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2191

result = dc->hwss.apply_ctx_to_hw(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2199

dc_trigger_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2202

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2203

uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2205

context->streams[i]->update_flags.raw = 0xFFFFFFFF;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2206

context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2209

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2212

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2214

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2215

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2224

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2225

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2229

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2231

dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2233

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2235

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2236

const struct dc_link *link = context->streams[i]->link;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2238

if (!context->streams[i]->mode_changed)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2242

apply_ctx_interdependent_lock(dc, context, context->streams[i], true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2244

dc, context->streams[i],

sys/dev/pci/drm/amd/display/dc/core/dc.c

2245

context->stream_status[i].plane_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2246

context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2247

apply_ctx_interdependent_lock(dc, context, context->streams[i], false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2248

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2256

pipe = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2258

for (l = 0 ; pipe && l < context->stream_count; l++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2259

if (context->streams[l] &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2260

context->streams[l] == pipe->stream &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

2267

context->streams[i]->timing.h_addressable,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2268

context->streams[i]->timing.v_addressable,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2269

context->streams[i]->timing.h_total,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2270

context->streams[i]->timing.v_total,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2271

context->streams[i]->timing.pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2274

dc_enable_stereo(dc, context, dc_streams, context->stream_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2276

if (get_seamless_boot_stream_count(context) == 0 ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2277

context->stream_count == 0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2279

hwss_wait_for_no_pipes_pending(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2284

hwss_wait_for_odm_update_pending_complete(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2286

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2290

dc_trigger_sync(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2294

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2297

TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2299

TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2301

context->stream_mask = get_stream_mask(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2303

if (context->stream_mask != dc->current_state->stream_mask)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2304

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2306

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2307

context->streams[i]->mode_changed = false;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2310

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2311

context->streams[i]->update_flags.raw = 0x0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2315

dc->current_state = context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2342

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2402

context = dc_state_create_current_copy(dc);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2403

if (!context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2406

context->power_source = params->power_source;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2408

res = dc_validate_with_context(dc, set, params->stream_count, context, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2415

dc, context, context->streams, context->stream_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2426

!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2427

res = commit_minimal_transition_state(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2434

res = dc_commit_state_no_check(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2437

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2438

if (params->streams[i]->stream_id == context->streams[j]->stream_id)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2439

params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2442

struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2448

status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, params->streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2456

dc_state_release(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2501

static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2507

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2510

if (!pipe->plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))

sys/dev/pci/drm/amd/display/dc/core/dc.c

2544

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2546

if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2557

TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2559

TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2561

if (is_flip_pending_in_pipes(dc, context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

2565

if (context->res_ctx.pipe_ctx[i].stream == NULL ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

2566

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

2567

context->res_ctx.pipe_ctx[i].pipe_idx = i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2568

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2573

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2576

dc->hwss.update_dsc_pg(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2632

const struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

2638

const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

2801

const struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

2806

if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3223

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3409

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3413

if (get_seamless_boot_stream_count(context) > 0 && (surface_count > 0 || stream->dpms_off)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3423

if (get_seamless_boot_stream_count(context) == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3458

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3473

context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3485

copy_stream_update_to_stream(dc, context, stream, stream_update);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3520

context = dc_state_create_copy(dc->current_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3521

if (context == NULL) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3529

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3530

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3533

if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3540

if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3555

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3566

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3571

update_seamless_boot_flags(dc, context, surface_count, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3573

*new_context = context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3581

dc_state_release(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3591

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3597

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3690

resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3703

if (get_seamless_boot_stream_count(context) == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3757

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3792

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3811

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3847

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3893

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3899

build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3906

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3912

srf_updates, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3919

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3921

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3924

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3935

context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3947

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

3956

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3960

dc_state_is_fams2_in_use(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

3983

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

3990

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

3994

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3997

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4005

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4009

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4022

stream_status = dc_state_get_stream_status(context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4029

context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4035

context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4036

context->dc_dmub_cmd,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4037

&(context->dmub_cmd_count));

sys/dev/pci/drm/amd/display/dc/core/dc.c

4039

context->dc_dmub_cmd,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4040

context->dmub_cmd_count,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4041

context->block_sequence,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4042

&(context->block_sequence_steps),

sys/dev/pci/drm/amd/display/dc/core/dc.c

4045

context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4047

context->block_sequence,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4048

context->block_sequence_steps);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4066

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4076

determine_pipe_unlock_order(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4088

dc->res_pool->funcs->prepare_mcache_programming(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4091

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4095

set_p_state_switch_method(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4098

dc_update_visual_confirm_color(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4105

if (get_seamless_boot_stream_count(context) == 0)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4106

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4109

dc->hwss.update_dsc_pg(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4111

context_clock_trace(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4118

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4132

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4134

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4177

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4180

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4182

dc->hwss.interdependent_update_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4185

dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4188

dc->hwss.fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4197

dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4201

commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4209

dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4211

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4214

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4218

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4222

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4228

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4232

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4239

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4259

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4262

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4281

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4285

should_update_pipe_for_stream(context, pipe_ctx, stream)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4296

stream_get_status(context, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4300

dc, pipe_ctx->stream, stream_status->plane_count, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4305

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4323

dc->hwss.program_front_end_for_ctx(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4328

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4336

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4342

&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4343

&context->res_ctx.pipe_ctx[i].dlg_regs,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4344

&context->res_ctx.pipe_ctx[i].ttu_regs);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4356

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4358

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4361

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4375

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4377

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4380

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

sys/dev/pci/drm/amd/display/dc/core/dc.c

4404

dc->hwss.interdependent_update_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4444

dc->hwss.enable_phantom_streams(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4449

dc->hwss.post_unlock_program_front_end(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4458

dc->hwss.disable_phantom_streams(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4463

dc->hwss.commit_subvp_config(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4469

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4471

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4474

dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4476

dc->hwss.fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4481

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4487

!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||

sys/dev/pci/drm/amd/display/dc/core/dc.c

4496

current_stream_mask = get_stream_mask(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4497

if (current_stream_mask != context->stream_mask) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4498

context->stream_mask = current_stream_mask;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4604

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4617

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4618

policy->force_odm[i] = context->streams[i]->debug.force_odm_combine_segments;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4619

if (context->streams[i]->debug.allow_transition_for_forced_odm)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4620

context->streams[i]->debug.force_odm_combine_segments = 0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4625

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4635

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4636

context->streams[i]->debug.force_odm_combine_segments = policy->force_odm[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

4648

static void force_vsync_flip_in_minimal_transition_context(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

4654

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

4655

stream_status = &context->stream_status[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5047

const struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5066

!is_surface_in_context(context, srf_updates[i].surface)))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5132

struct dc_state *context;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5166

&context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5171

if (!commit_minimal_transition_state(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5172

dc_state_release(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5180

dc, dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/core/dc.c

5181

commit_minimal_transition_state_in_dc_update(dc, context, stream,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5191

context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5196

dc, dc->current_state, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5207

context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5209

if (dc->current_state != context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5210

swap_and_release_current_context(dc, context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5587

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5621

if (dc->res_pool && context) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5623

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5624

subvp_pipe_type[i] = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5679

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5685

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

5705

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc.c

6277

struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6281

profile.power_level = !context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6282

if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6284

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6287

profile.power_level = dc->res_pool->funcs->get_power_profile(context);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6300

unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6302

struct dc *dc = context->clk_mgr->ctx->dc;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6305

return dc->res_pool->funcs->get_det_buffer_size(context);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

186

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

191

context->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

192

context->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

193

context->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

194

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

195

context->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

196

context->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

199

context->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

200

context->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

201

context->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

202

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

203

context->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

204

context->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1146

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1156

opp_head = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1159

dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1166

void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1173

otg_master = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1175

dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1185

hwss_wait_for_all_blank_complete(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1188

void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1193

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1195

if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

632

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

635

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

649

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

662

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

664

if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

665

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

676

if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

705

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

715

if (!dc_state_is_fams2_in_use(dc, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

730

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

761

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

900

block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1700

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1705

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1706

context->res_ctx.pipe_ctx[i].stream != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1707

if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2483

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2491

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2499

resource_build_test_pattern_params(&context->res_ctx, otg_master);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2506

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2514

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2747

static void swap_dio_link_enc_to_muxable_ctx(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2752

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2753

int stream_count = context->stream_count;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2761

struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2762

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2770

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2775

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2797

swap_dio_link_enc_to_muxable_ctx(context, pool, new_enc_index, enc_index);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2828

static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2834

if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2848

void resource_remove_otg_master_for_stream_output(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2853

&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2862

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2869

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2873

&context->res_ctx, otg_master, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2877

remove_dio_link_enc_from_ctx(&context->res_ctx, otg_master, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2881

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2886

resource_unreference_clock_source(&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2892

stream->ctx->dc, context, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2923

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3047

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3054

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3194

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3211

pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3215

pool->funcs->release_pipe(context, last_opp_head, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3316

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3334

pool->funcs->release_pipe(context, last_dpp_pipe, pool);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3567

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3571

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3572

struct dc_stream_state *stream_has_pll = context->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3862

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3879

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3892

context, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3894

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3901

&context->res_ctx, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3907

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3927

&context->res_ctx, pool, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3933

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3936

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3942

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3952

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3960

update_audio_usage(&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3972

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3973

if (context->streams[i] == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3974

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3975

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3976

context->stream_status[i].audio_inst =

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3994

static bool planes_changed_for_existing_stream(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4002

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4003

if (context->streams[i] == stream) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4004

stream_status = &context->stream_status[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4077

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4083

int old_stream_count = context->stream_count;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4095

struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4115

if (stream == context->streams[j]) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4157

if (planes_changed_for_existing_stream(context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4164

context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4184

if (dc_state_get_stream_subvp_type(context, del_streams[i]) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4186

if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4191

res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4192

dc_state_release_phantom_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4194

if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4199

res = dc_state_remove_stream(dc, context, del_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4224

res = dc_state_add_stream(dc, context, add_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4228

if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4236

if (planes_changed_for_existing_stream(context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4240

if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4248

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4249

dc_state_set_stream_subvp_cursor_limit(context->streams[i], context, false);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4252

res = dc_validate_global_state(dc, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4257

dc->hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4835

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4841

&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4854

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4860

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4868

&context->res_ctx, pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5256

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5264

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5274

pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5284

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5290

pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5297

pipe_ctx_check = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5318

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5326

pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5489

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5496

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5502

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5508

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5514

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5520

remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5524

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5535

static bool resource_allocate_mcache(struct dc_state *context, const struct dc_mcache_params *mcache_params)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5537

if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5538

context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5609

bool resource_is_hpo_acquired(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5614

if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {

sys/dev/pci/drm/amd/display/dc/dc.h

1896

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc.h

2718

struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc.h

2720

unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc.h

467

bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1692

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1709

memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub_cmd_fams2_global_config));

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1717

for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1719

struct dmub_rb_cmd_fams2 *stream_sub_state_cmd = &cmd[i+1+context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1734

&context->bw_ctx.bw.dcn.fams2_stream_base_params[i],

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1738

&context->bw_ctx.bw.dcn.fams2_stream_sub_params[i],

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1747

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1750

cmd[2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1751

num_cmds += 2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1758

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1774

if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1781

memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1785

for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1788

&context->bw_ctx.bw.dcn.fams2_stream_base_params[i],

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1793

&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[i],

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1805

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1809

dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1811

dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

420

static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

429

struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

438

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

461

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

470

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

479

for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

480

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

485

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

487

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

494

dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

576

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

581

struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

655

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

667

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

676

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

693

populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

711

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

724

phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

728

phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

776

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

784

struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

843

struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

846

phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

871

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

890

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

896

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

903

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

904

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

916

populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

922

populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

928

update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

935

wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

197

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

89

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

99

void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

469

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

474

void dc_trigger_sync(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

602

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

184

static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

190

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

215

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

220

int max_pix_clk = get_max_pixel_clock_for_all_paths(context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

227

if (context->bw_ctx.bw.dce.dispclk_khz >

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

237

< context->bw_ctx.bw.dce.dispclk_khz)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

496

const struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

502

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

505

const struct dc_stream_state *stream = context->streams[j];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

511

if (stream == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

512

pipe_ctx = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

548

static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

553

for (j = 0; j < context->stream_count; j++) {

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

554

struct dc_stream_state *stream = context->streams[j];

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

600

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

602

struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

604

pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

606

dce110_fill_display_configs(context, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

614

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

616

struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

619

context->bw_ctx.bw.dce.all_displays_in_sync;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

621

context->bw_ctx.bw.dce.nbp_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

623

context->bw_ctx.bw.dce.cpuc_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

625

context->bw_ctx.bw.dce.cpup_state_change_enable == false;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

627

context->bw_ctx.bw.dce.blackout_recovery_time_us;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

629

pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

634

context->bw_ctx.bw.dce.sclk_khz);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

643

pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

647

= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

650

dce110_get_min_vblank_time_us(context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

656

dce110_fill_display_configs(context, pp_display_cfg);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

661

&context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

673

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

678

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

684

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

696

dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

700

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

705

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

711

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

720

context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

723

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

727

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

732

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

738

level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

750

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

754

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

759

int max_pix_clk = get_max_pixel_clock_for_all_paths(context);

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

760

int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

788

dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1057

hack_bounding_box(v, &dc->debug, context);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1063

&& context->stream_count == 1

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1078

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1079

context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1145

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1147

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1149

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1151

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1152

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1153

context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1154

context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1155

context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1157

context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1160

context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1162

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1163

context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1165

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1167

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1169

if (context->bw_ctx.bw.dcn.clk.dispclk_khz <

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1171

context->bw_ctx.bw.dcn.clk.dispclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1175

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1177

context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1180

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1184

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1188

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1192

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1200

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1261

hsplit_pipe = resource_find_free_secondary_pipe_legacy(&context->res_ctx, pool, pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1263

split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1294

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1296

context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

556

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

566

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

568

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

570

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

572

context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

573

context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

580

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

582

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

584

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

586

context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

587

context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

601

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

603

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

605

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

607

context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

608

context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

621

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

623

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

625

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

627

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

628

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

630

context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

631

context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

634

context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

705

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

710

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

731

context->stream_count >= 2)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

734

if (context->stream_count == 1 &&

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

736

hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

750

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

760

struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

894

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1030

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1039

wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1040

wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1042

wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1045

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1049

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1051

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1057

static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1064

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1081

else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1082

struct dc_link *link = context->streams[0]->sink->link;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1083

struct dc_stream_status *stream_status = &context->stream_status[0];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1085

bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1095

if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1141

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1151

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1153

context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1154

context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1155

context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1156

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1158

if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1159

context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1161

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1162

context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1163

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1164

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1170

context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1172

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1174

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1176

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1177

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1180

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1182

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1184

pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1185

pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1186

pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1187

pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1189

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1191

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1192

context->res_ctx.pipe_ctx[i].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1194

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1195

context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1198

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1199

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1200

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1202

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1204

context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1206

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1207

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1213

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1216

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1217

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1218

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1219

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1221

context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1222

- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1225

bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1227

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1234

context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1235

&context->res_ctx.pipe_ctx[i].dlg_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1236

&context->res_ctx.pipe_ctx[i].ttu_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1241

context->bw_ctx.bw.dcn.clk.p_state_change_support,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1244

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1245

&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1249

context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1315

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1321

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1539

dc_state_get_pipe_subvp_type(context, &res_ctx->pipe_ctx[i]) == SUBVP_PHANTOM))

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1730

void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1742

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1746

pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1750

context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1751

if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1753

context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1759

context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1760

if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1762

context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1768

pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1769

pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1782

context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1785

context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1791

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1792

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1797

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1798

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1800

context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1801

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1802

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1803

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1804

context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1805

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1806

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1807

context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1811

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1812

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1814

context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1815

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1816

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1817

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1818

context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1819

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1820

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1824

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1825

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1827

context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1828

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1829

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1830

context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1831

context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1832

context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1833

context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1836

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1837

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1838

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1839

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1840

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1841

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1842

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1843

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1844

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2028

static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2042

out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2057

dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2058

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2066

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2078

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2088

p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2089

context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2091

context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2095

ASSERT(context != dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2098

return dcn20_validate_bandwidth_internal(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2101

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2102

full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2104

if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2106

context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2111

context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2114

voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2115

dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2117

if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2118

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2126

context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2155

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2164

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2235

static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2249

patch_bounding_box(dc, &context->bw_ctx.dml.soc);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2252

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2256

pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2260

context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2261

if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2263

context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2269

context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2270

if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2272

context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2282

context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2285

context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2299

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2300

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2304

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2305

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2309

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2310

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2315

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2316

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2319

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2336

ASSERT(context != dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2338

out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2353

dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2354

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2362

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

36

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

40

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

45

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

49

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

64

bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

76

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h

79

bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

289

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

295

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

296

context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

297

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

299

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

304

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

309

int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

311

double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

312

bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

318

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

319

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

321

if (context->streams[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

322

stream_status = dc_state_get_stream_status(context, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

329

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

330

dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

332

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

334

context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

341

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

342

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

344

maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

345

dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

346

pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

350

if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

351

dcfclk = context->bw_ctx.dml.soc.min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

355

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

364

pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

366

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

367

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

368

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

370

context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

371

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

372

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

373

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

374

context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

375

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

376

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

377

context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

409

unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

412

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

415

if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

423

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

433

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

436

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

437

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

440

context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

441

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

442

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

443

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

444

context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

445

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

446

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

447

context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

453

context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

454

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

462

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

463

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

464

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

465

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

466

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

467

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

468

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

469

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

470

context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

473

context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

476

context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

479

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

482

pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

483

pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

486

pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

487

pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

498

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

500

context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

501

context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

505

context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

511

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

515

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

518

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

519

dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

621

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

632

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

634

dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

637

if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

41

void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

44

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

64

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

427

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

448

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

449

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

453

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

454

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

458

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

459

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

464

calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

465

&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

468

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

471

pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

472

pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

475

pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

476

pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

485

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h

37

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

454

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

465

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

471

if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_vactive)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

472

context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

475

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

477

context->bw_ctx.dml.soc.sr_exit_time_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

483

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

489

double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

494

if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

495

dcfclk = context->bw_ctx.dml.soc.min_dcfclk;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

502

context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

508

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

511

get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

513

if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time &&

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

522

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

523

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

524

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

525

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

526

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

527

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

528

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

529

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

530

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

531

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

532

context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

533

context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

534

context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

535

context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

538

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

541

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

544

pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

545

pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

548

pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

549

pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

559

dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

561

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

562

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

565

context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

566

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

567

context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

568

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

569

context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

570

context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

571

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

573

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

574

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

577

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

580

context->res_ctx.pipe_ctx[i].det_buffer_size_kb =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

581

get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

582

if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

583

context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

584

total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

587

context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - total_det;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

38

void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

39

void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

42

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h

56

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

307

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

312

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

319

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

392

context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

402

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

405

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

407

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

408

} else if (context->stream_count >= 3 && upscaled) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

409

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

413

context->bw_ctx.dml.ip.odm_combine_4to1_supported = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

416

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

425

context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

36

int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1001

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1038

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1042

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1049

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1050

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1074

schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1079

if (dcn32_subvp_drr_admissable(dc, context))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1080

schedulable = subvp_drr_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1081

else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1082

schedulable = subvp_vblank_schedulable(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1093

static void assign_subvp_index(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1099

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1102

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1169

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1179

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1180

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1182

&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1190

&context->res_ctx, dpp_pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1201

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1232

pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1267

static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1273

resource_update_pipes_for_stream_with_slice_count(context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1279

resource_update_pipes_for_plane_with_slice_count(context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1285

static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1292

init_pipe_slice_table_from_context(&slice_table, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1294

&slice_table, dc, context, vba,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1296

update_pipes_with_slice_table(dc, context, &slice_table);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1301

struct dc_state *context, struct vba_vars_st *v, int *split,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1304

struct dc_stream_state *stream = context->streams[0];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1324

if (context->stream_count != 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1359

init_pipe_slice_table_from_context(&slice_table, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1361

&slice_table, dc, context, v,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1379

if (context->stream_status[0].plane_count != 1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1382

if (memcmp(&context->stream_status[0].plane_states[0]->clip_rect,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1395

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1411

new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1413

if (new_vlevel < context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1416

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1417

context->bw_ctx.dml.vba.VoltageLevel = *vlevel;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1425

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1429

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1430

if (context->streams[i]->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1438

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1446

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1461

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1464

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1467

*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1469

if (*vlevel < context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1470

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1475

if (!dcn32_apply_merge_split_flags_helper(dc, context, repopulate_pipes, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1487

if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1488

!dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && !is_test_pattern_enabled(context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1489

(*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpeedPerState[0] &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1496

while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1497

dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1505

if (*vlevel == context->bw_ctx.dml.soc.num_states &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1506

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1508

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1515

*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1518

dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1520

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1524

pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1525

*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1530

for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1537

if (*vlevel < context->bw_ctx.dml.soc.num_states

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1538

&& subvp_validate_static_schedulability(dc, context, *vlevel))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1542

if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1561

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1562

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1564

*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1567

*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1569

if (*vlevel < context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1570

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1575

dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1585

*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1589

assign_subvp_index(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1593

if (should_apply_odm_power_optimization(dc, context, vba, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1595

dc, context, pipes, split, merge, vlevel, *pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1600

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1605

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1607

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1645

static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1652

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1657

dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1659

context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1660

context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1661

context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1662

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1663

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1664

context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1665

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1666

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1672

context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1674

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1675

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1676

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1677

if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1678

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1680

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1682

usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1685

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1686

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1688

unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1696

context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1697

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1698

context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1701

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1703

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1705

pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1707

pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1709

pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1711

pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1714

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1716

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1717

context->res_ctx.pipe_ctx[i].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1719

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1721

context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1724

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1725

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1726

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1727

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1729

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1730

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1732

context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1735

context->res_ctx.pipe_ctx[i].has_vactive_margin = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1737

context->res_ctx.pipe_ctx[i].has_vactive_margin = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1741

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1742

(context->res_ctx.pipe_ctx[i].top_pipe == NULL ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1743

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1744

context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1746

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1747

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1749

if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1751

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1755

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1759

if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1761

&context->res_ctx.pipe_ctx[i].stream->timing,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1762

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1768

context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1769

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1770

context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1771

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1772

context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1773

context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1774

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1775

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1778

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1779

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1780

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1782

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1785

context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1787

context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1790

if (context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1791

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1796

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1799

context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1800

&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1803

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1804

&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1811

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1817

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1818

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1826

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1827

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

183

static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1841

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1842

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1939

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1946

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1950

dc, context, vba, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1959

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2006

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2033

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2062

hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2068

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2085

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2090

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2104

pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2109

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2115

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2119

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2127

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2128

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2129

context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2132

resource_build_test_pattern_params(&context->res_ctx, otg_master);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2139

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2150

int vlevel = context->bw_ctx.dml.soc.num_states;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2151

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2160

dc_state_remove_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2161

dc_state_release_phantom_streams_and_planes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2163

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2165

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2166

resource_update_pipes_for_stream_with_slice_count(context, dc->current_state, dc->res_pool, context->streams[i], 1);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2167

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2174

dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2175

context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2178

if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2185

(vlevel == context->bw_ctx.dml.soc.num_states ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2197

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2200

context->bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2201

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2203

context->bw_ctx.dml.validate_max_state = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2205

if (vlevel < context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2208

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2214

dml_log_mode_support_params(&context->bw_ctx.dml);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2216

if (vlevel == context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2220

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2238

if (!dcn32_apply_merge_split_flags_helper(dc, context, &repopulate_pipes, split, merge))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2242

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2252

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2254

dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2261

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2264

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2266

if (vlevel == context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2270

flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2273

for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2302

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2309

double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2310

double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2312

bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2315

int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2316

unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2317

bool subvp_in_use = dcn32_subvp_in_use(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2330

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2331

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2336

context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2341

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2343

context->bw_ctx.dml.soc.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2346

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2348

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2349

maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2351

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2355

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2356

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2358

if (context->streams[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2359

stream_status = dc_state_get_stream_status(context, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2367

fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2369

stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2372

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2375

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2377

context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2384

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2389

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2391

context->bw_ctx.dml.soc.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2394

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2398

maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2399

dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2401

context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2407

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2408

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2410

if (context->streams[i])

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2411

stream_status = dc_state_get_stream_status(context, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2416

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2437

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2440

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2441

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2442

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2443

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2445

context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2446

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2447

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2448

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2449

context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2450

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2451

context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2452

context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2453

context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2454

context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2502

pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2504

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2512

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2515

if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2523

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2533

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2536

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2537

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2538

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2541

context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2542

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2543

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2544

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2545

context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2546

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2547

context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2548

context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2553

context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2554

context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2561

context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2562

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2566

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2576

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2577

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2578

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2580

context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2581

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2582

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2583

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2584

context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2585

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2586

context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2587

context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2588

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2589

context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2593

context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2596

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2599

pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2600

pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2603

pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2604

pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2614

context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2618

context->bw_ctx.dml.soc.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2621

dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2625

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2630

context->bw_ctx.dml.soc.fclk_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

276

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

282

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

284

enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

290

vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

291

context->bw_ctx.dml.soc.dram_clock_change_latency_us =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

293

dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

297

dcn32_subvp_in_use(dc, context))

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

298

vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

300

if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

334

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

343

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3433

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3447

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3470

if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

348

if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3489

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3497

if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3498

for (i = 0; i < context->stream_status[0].plane_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3499

if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

350

get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3500

context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

352

get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3523

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3526

const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3529

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

354

get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

356

get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3560

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3563

const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3568

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3600

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3603

if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3607

if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3609

context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3610

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

467

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

478

unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

479

unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

480

unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

481

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

488

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

515

phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

527

phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

558

static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

565

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

600

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

606

unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

607

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

630

!dc_state_get_stream_cursor_subvp_limit(pipe->stream, context) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

632

(!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

633

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

634

(refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

644

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

680

static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

687

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

691

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

703

free_pipes = dcn32_get_num_free_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

726

static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

737

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

743

phantom = dc_state_get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

745

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

797

static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

819

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

828

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

836

drr_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

843

if (dc_state_get_pipe_subvp_type(context, drr_pipe) == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

850

phantom_stream = dc_state_get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

898

static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

925

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

926

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

944

phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

947

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

986

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

995

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

35

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

40

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

48

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

54

void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

62

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

72

void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

74

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

76

void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

438

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

443

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

450

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

530

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

544

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

547

} else if (context->stream_count >=

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

550

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

552

} else if (context->stream_count >= 3 && upscaled) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

553

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

557

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

568

context->bw_ctx.dml.vba.ODMCombinePolicy =

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

578

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

587

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

591

if (context->stream_count == 0 || plane_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

593

} else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

594

struct dc_link *link = context->streams[0]->sink->link;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

601

bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

604

bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

617

(int)context->bw_ctx.dml.vba.StutterPeriod);

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

619

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

38

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

42

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

471

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

476

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

483

dcn31_populate_dml_pipes_from_context(dc, context, pipes,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

563

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

577

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

580

} else if (context->stream_count >=

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

583

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

585

} else if (context->stream_count >= 3 && upscaled) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

586

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

590

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

601

context->bw_ctx.dml.vba.ODMCombinePolicy =

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

611

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

617

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

622

if (context->stream_count == 0 || plane_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

624

} else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

625

struct dc_link *link = context->streams[0]->sink->link;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

632

bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

638

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

13

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

17

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

469

const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

477

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

498

const struct dc_state *context, unsigned int stream_index)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

500

const struct scaler_data *scaler_data = get_scaler_data_for_plane(dml_ctx, plane_state, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

501

struct dc_stream_state *stream = context->streams[stream_index];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

644

static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

651

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

652

if (context->streams[i]->stream_id == stream_id) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

653

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

654

if (context->stream_status[i].plane_states[j] == plane) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

681

const struct dc_plane_state *plane, const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

687

if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

727

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

747

for (stream_index = 0; stream_index < context->stream_count; stream_index++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

748

disp_cfg_stream_location = map_stream_to_dml21_display_cfg(dml_ctx, context->streams[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

754

populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

755

populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

756

populate_dml21_stream_overrides_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

762

dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[stream_index]->stream_id;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

765

if (context->stream_status[stream_index].plane_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

767

populate_dml21_dummy_surface_cfg(&dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->streams[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

768

populate_dml21_dummy_plane_cfg(&dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->streams[stream_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

771

for (plane_index = 0; plane_index < context->stream_status[stream_index].plane_count; plane_index++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

772

disp_cfg_plane_location = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_index]->stream_id, context->stream_status[stream_index].plane_states[plane_index], context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

779

populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

780

populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

783

if (dml21_wrapper_get_plane_id(context, context->streams[stream_index]->stream_id, context->stream_status[stream_index].plane_states[plane_index], &dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

804

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

807

context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

808

context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

809

context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

810

context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

811

context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

812

context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

813

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.deepsleep_dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

814

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming->fclk_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

815

context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

816

context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz > 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

817

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

818

context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

819

context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

820

context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

821

context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

822

context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

882

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

21

bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

22

void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

25

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

27

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

108

dc_main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, main_stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

109

dc_main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

118

num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc_main_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

121

struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

123

num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

127

dc_phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

129

dc_phantom_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

137

dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_pipes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

146

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

152

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

162

void dml21_populate_mall_allocation_size(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

175

if (in_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, dc_pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

177

context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

181

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

196

static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

201

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

203

if (pipe_ctx->stream && dc_state_get_paired_subvp_stream(context, pipe_ctx->stream) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

204

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

212

void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

217

dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

220

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

231

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

232

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

234

dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

236

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

243

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

250

phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

273

dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

280

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

287

phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

315

dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

320

void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

334

main_stream = dml_ctx->config.callbacks.get_stream_from_id(context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

337

main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, main_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

345

context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

362

context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

374

dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

378

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

385

memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

386

memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

387

memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

388

memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

391

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

397

union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

398

union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

400

struct dc_stream_state *stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

402

if (context->stream_status[i].plane_count == 0 ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

403

dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

420

memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

435

static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

436

static_base_state->stream_v1.base.otg_inst = context->stream_status[i].primary_otg_inst;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

439

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

441

if (context->res_ctx.pipe_ctx[k].stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

442

context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

443

context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

459

phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

463

phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

478

if (context->res_ctx.pipe_ctx[k].stream &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

479

context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

480

context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

503

memcpy(&context->bw_ctx.bw.dcn.fams2_global_config,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

507

context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

510

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

85

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

22

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

25

void dml21_populate_mall_allocation_size(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

34

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

40

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

44

void dml21_handle_phantom_streams_planes(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.h

47

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

101

memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

104

context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

106

context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

107

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

108

context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

125

num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

132

dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

135

dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

140

memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

142

memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

151

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

152

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

154

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

157

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

161

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

164

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

169

context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

171

context->bw_ctx.bw.dcn.clk.num_ways = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

175

static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

181

for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

182

for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

183

dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

204

static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

214

if (!context)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

217

if (context->stream_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

218

dml21_build_fams2_programming(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

223

dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

224

dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

228

result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

242

dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

244

dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

248

dml21_prepare_mcache_params(dml_ctx, context, mcache_params);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

251

dml_ctx->config.callbacks.allocate_mcache(context, mcache_params);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

257

dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

258

dml21_copy_clocks_to_dc_state(dml_ctx, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

259

dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

260

dml21_build_fams2_programming(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

266

static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

276

if (!context || context->stream_count == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

280

dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

281

dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

285

dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

297

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

304

out = dml21_check_mode_support(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

306

out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

311

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

322

if (context->stream_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

339

mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

347

num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

355

dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

366

mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

372

dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

387

num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

87

static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

98

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

61

bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

65

void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

101

static void merge_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

107

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

125

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

146

static bool all_pipes_have_stream_and_plane(struct dml2_context *ctx, const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

151

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

162

static bool mpo_in_use(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

166

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

167

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

228

static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context, unsigned int *index)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

235

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

238

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

256

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_NONE && refresh_rate < 120 &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

263

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

32

unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

357

static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

368

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

375

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

376

phantom = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

431

bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

449

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

457

if (ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

461

phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

50

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

507

static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

534

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

535

pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

54

ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

552

if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

554

schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

556

phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, subvp_pipe->stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

559

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

601

bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

604

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

611

enum mall_stream_type pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

632

schedulable = subvp_subvp_schedulable(ctx, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

639

schedulable = subvp_vblank_schedulable(ctx, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

810

static bool remove_all_phantom_planes_for_stream(struct dml2_context *ctx, struct dc_stream_state *stream, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

816

for (i = 0; i < context->stream_count; i++)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

817

if (context->streams[i] == stream) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

818

stream_status = &context->stream_status[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

832

if (!ctx->config.svp_pstate.callbacks.remove_phantom_plane(ctx->config.svp_pstate.callbacks.dc, stream, del_planes[i], context))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

834

ctx->config.svp_pstate.callbacks.release_phantom_plane(ctx->config.svp_pstate.callbacks.dc, context, del_planes[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h

42

unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h

48

bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc_state *context, enum dml_dram_clock_change_support pstate_change_type);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.h

50

bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1060

const struct dc_plane_state *in, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1063

struct scaler_data *scaler_data = get_scaler_data_for_plane(in, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1146

static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1155

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1156

if (context->streams[i]->stream_id == stream_id) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1157

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1158

if (context->stream_status[i].plane_states[j] == plane &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1171

const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1177

if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1267

static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1279

current_pipe_context = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1290

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1312

dml2_populate_pipe_to_plane_index_mapping(dml2, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1313

dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1315

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1320

if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1321

current_pipe_context = &context->res_ctx.pipe_ctx[k];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1325

disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1326

stream_mall_type = dc_state_get_stream_subvp_type(context, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1333

populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1334

populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1337

disp_cfg_stream_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1339

switch (context->streams[i]->debug.force_odm_combine_segments) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1350

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1353

if (context->stream_status[i].plane_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1356

populate_dummy_dml_surface_cfg(&dml_dispcfg->surface, disp_cfg_plane_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1358

context->streams[i], &dml2->v20.dml_core_ctx.soc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1364

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1366

context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1373

populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1376

context->stream_status[i].plane_states[j], context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1393

if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1398

populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1399

populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1400

switch (context->streams[i]->debug.force_odm_combine_segments) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1416

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

979

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

982

struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

987

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.h

37

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

169

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

174

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

176

if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

182

void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

184

context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

185

context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

186

context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

187

context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

188

context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

189

context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

190

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

191

context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

279

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

285

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

286

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

289

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

291

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

293

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

294

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

296

context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

299

if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

305

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

306

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

307

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

310

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

316

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

321

populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

323

pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

326

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

327

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

329

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

331

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

334

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

335

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

336

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

337

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

343

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

347

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

348

(context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

349

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

350

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

353

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

356

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

361

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

362

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

364

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

366

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

370

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

371

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

414

void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

421

if (context->stream_count != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

422

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

423

if (context->streams[i]->num_wb_info != 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

430

bw_writeback = &context->bw_ctx.bw.dcn.bw_writeback;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

431

wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[i];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

440

if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

443

(1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

122

void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

41

void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

43

void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

45

bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

71

void dml2_dc_construct_pipes(struct dc_state *context, struct dml_mode_support_info_st *dml_mode_support_st,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

84

bool dml2_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.h

96

enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

356

static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

363

if (!context)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

366

struct dml2_context *dml2 = context->bw_ctx.dml2;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

369

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

370

min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

376

result = dml_mode_support_wrapper(dml2, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

381

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

389

if (!context->streams[0]->sink->link->dc->caps.is_apu) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

398

static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

401

struct dml2_context *dml2 = context->bw_ctx.dml2;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

408

if (context->stream_count == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

419

context->bw_ctx.bw.dcn.clk.dtbclk_en = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

420

dml2_copy_clocks_to_dc_state(&out_clks, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

435

result = call_dml_mode_support_and_programming(context, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

441

dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

449

need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

452

call_dml_mode_support_and_programming(context, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

454

dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

456

need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

477

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

481

dml2_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_count);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

484

dml2_copy_clocks_to_dc_state(&out_clks, context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

485

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

486

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

487

if (context->streams[0]->sink->link->dc->caps.is_apu)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

488

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

490

memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c));

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

491

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

492

dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

494

context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

496

cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

498

if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

502

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

508

static bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

513

if (!context || context->stream_count == 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

516

dml2 = context->bw_ctx.dml2;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

526

map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

548

bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

559

out = dml21_validate(in_dc, context, dml2, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

567

out = dml2_validate_only(context, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

569

out = dml2_validate_and_build_resource(in_dc, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

660

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

663

dml21_prepare_mcache_programming(in_dc, context, dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

111

bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

127

bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

131

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

296

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

308

void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

76

bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

110

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

112

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

116

context,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

122

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

124

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

128

context,

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

39

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

43

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1518

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1583

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1603

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1623

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1659

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1701

dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1710

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1719

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1821

static void get_edp_streams(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1828

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1829

if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1830

edp_streams[*edp_stream_num] = context->streams[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1908

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1932

hws->funcs.init_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1934

get_edp_streams(context, edp_streams, &edp_stream_num);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1962

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1987

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1988

if (context->streams[i]->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2049

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2055

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2065

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2066

context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2067

context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2068

context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2074

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2075

context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2076

context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2200

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2205

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2216

if (context->stream_count != 1)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2266

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2270

if (should_enable_fbc(dc, context, &pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2274

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2290

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2299

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2348

if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2362

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2386

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2398

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2424

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2438

build_audio_output(context, pipe_ctx, &audio_output);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2453

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2460

bool is_hpo_acquired = resource_is_hpo_acquired(context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2464

reset_syncd_pipes_from_disabled_pipes(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2468

hws->funcs.reset_hw_ctx_wrap(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2471

if (context->stream_count <= 0)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2481

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2501

dce110_setup_audio_dto(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2510

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2528

context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2536

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2803

static void dce110_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2889

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2893

dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2897

context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2903

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2907

dce110_set_displaymarks(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2912

context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3030

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3041

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3052

context->stream_count);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3063

enable_fbc(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3068

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

123

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

40

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

44

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

62

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

72

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

76

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

116

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

120

if (dce60_should_enable_fbc(dc, context, &pipe_idx)) {

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

124

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

385

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

396

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

407

context->stream_count);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

418

dce60_enable_fbc(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

51

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

56

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

67

if (context->stream_count != 1)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1180

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1284

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1569

void dcn10_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1577

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1578

if (context->streams[i]->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1586

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1612

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1629

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1643

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1684

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1689

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1948

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1957

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

220

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

230

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

241

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2733

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2980

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3021

if (context->bw_ctx.bw.dcn.clk.dispclk_khz <

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3026

context->bw_ctx.bw.dcn.clk.dppclk_khz <=

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3204

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3229

dcn10_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3231

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3251

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3258

pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3284

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3289

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3296

if (context->stream_status[i].plane_count == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3302

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3306

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3307

dc->hwss.optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3315

static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3319

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3320

if (context->streams[i]->timing.timing_3d_format

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3333

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3342

if (context->stream_count == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3343

context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3347

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3351

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3354

dcn10_stereo_hw_frame_pack_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3371

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3380

if (context->stream_count == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3381

context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3385

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3389

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3393

dcn10_stereo_hw_frame_pack_wa(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4056

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4058

struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4064

context, clock_type, &clock_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4085

context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4094

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4097

dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

110

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

113

void dcn10_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

117

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

124

void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

203

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

206

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

45

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

49

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

52

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

84

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

88

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

92

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1191

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1313

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1682

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1690

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1786

(context == dc->current_state && plane_state->update_flags.bits.position_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1787

(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1906

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1917

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1930

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1947

dcn20_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1950

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1954

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1956

dcn20_enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1975

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2046

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2056

if (resource_is_pipe_topology_changed(dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2057

resource_log_pipe_topology_update(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2061

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2075

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2088

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2089

&context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2099

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2113

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2114

&& !context->res_ctx.pipe_ctx[i].top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2115

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2116

&& context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2117

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2121

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2122

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2132

(context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2133

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i])

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2149

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2154

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2162

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2167

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2178

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2179

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2187

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2193

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2201

context->stream_status[0].plane_count > 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2246

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2256

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2261

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2271

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2274

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2285

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2294

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2311

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2320

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2327

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2328

dcn20_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2346

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2352

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2362

context->stream_status[0].plane_count > 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2376

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2380

unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2385

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2389

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2392

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2393

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2403

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2409

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2413

if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2414

compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2417

compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2427

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2433

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2436

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2437

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2444

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2450

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2455

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2457

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2459

true, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2460

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2468

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2470

if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2473

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2486

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2492

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2496

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2500

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2540

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2556

mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2812

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2903

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2912

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3136

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3196

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3218

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3233

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3235

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

833

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

869

opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

920

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

993

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

117

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

165

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

169

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

39

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

42

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

72

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

75

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

78

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

81

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

84

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

92

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

229

struct dc_state *context = dc->current_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

306

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

341

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

343

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

100

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

104

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

110

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

114

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

129

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

289

struct dc_state *context, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

294

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

41

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

45

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

47

void dcn21_PLAT_58856_wa(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

57

struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1188

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1190

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1192

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1197

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1200

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1203

dc_dmub_srv_p_state_delegate(dc, false, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

430

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

447

mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

453

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

461

dcn30_set_writeback(dc, wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

527

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

543

dcn30_set_writeback(dc, wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

575

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

584

for (i_stream = 0; i_stream < context->stream_count; i_stream++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

585

if (context->streams[i_stream] == stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

586

stream_status = &context->stream_status[i_stream];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

603

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

626

dc->hwss.update_writeback(dc, &wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

629

dc->hwss.enable_writeback(dc, &wb_info, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

38

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

42

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

46

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

98

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

514

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

615

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

624

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

657

link_enc_cfg_set_transient_mode(dc, dc->current_state, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

53

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

57

struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

58

void dcn31_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

172

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

365

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

373

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

398

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

420

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

429

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

42

void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1131

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1223

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1231

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1243

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1252

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1253

dc_state = context;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1265

reset_sync_context_for_pipe(dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1274

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1429

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1436

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1438

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1439

dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1514

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1524

if (context->res_ctx.is_dsc_acquired[i]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1536

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1544

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1556

(pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1569

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1576

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1583

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1596

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1601

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1618

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1625

hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1789

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1791

bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1795

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1797

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1802

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1805

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1807

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1808

dc_dmub_srv_p_state_delegate(dc, false, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1810

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1814

context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1819

struct dc_state *context, bool lock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1826

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1831

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1842

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1848

hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

345

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

354

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

356

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

362

dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

372

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

385

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

386

pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

395

if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

406

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

600

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

609

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

614

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

616

if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

628

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

647

stream_status = dc_state_get_stream_status(context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

651

if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

667

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

670

unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

674

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

700

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

721

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

730

hws->funcs.update_mall_sel(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

734

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

743

if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

101

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

111

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

114

void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

116

void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

127

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

130

struct dc_state *context, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

133

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

48

void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

66

void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

68

void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

70

void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

81

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

94

void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1026

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1037

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1110

if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1125

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1360

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1365

dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1374

dcn20_prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1381

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1387

dcn20_optimize_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1390

dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

428

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

620

void dcn35_init_pipes(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

629

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

630

if (context->streams[i]->apply_seamless_boot_optimization) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

638

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

664

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

681

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

695

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

736

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

741

dc->hwss.disable_plane(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

816

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

922

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

934

if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

947

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

60

void dcn35_init_pipes(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

63

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

66

void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

68

void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

79

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

83

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

38

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

43

dcn35_calc_blocks_to_gate(dc, context, update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

58

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c

63

dcn35_calc_blocks_to_ungate(dc, context, update_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

32

void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h

34

void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1371

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1374

bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1380

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1385

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1391

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1399

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1404

dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1409

compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1416

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1417

dcn401_fams2_update_config(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1418

dcn401_fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1421

if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1424

context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1430

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1437

dcn401_fams2_global_control_lock(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1438

dcn401_fams2_update_config(dc, context, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1439

dcn401_fams2_global_control_lock(dc, context, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1444

&context->bw_ctx.bw.dcn.watermarks,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1449

hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1454

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1459

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1463

context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1465

if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1467

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1479

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1511

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1518

fams2_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1520

dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1523

static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1554

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1562

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1573

otg_master, &context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1597

update_dsc_for_odm_change(dc, context, otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1664

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1675

&context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1681

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1698

struct dc_state *context, bool lock)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1706

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1711

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1718

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1723

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1740

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1744

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1802

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1808

hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1814

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1901

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1910

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1961

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1972

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1985

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2002

dcn401_program_tg(dc, pipe_ctx, context, hws);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2005

hws->funcs.update_odm(dc, context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2009

hws->funcs.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2011

dc->hwss.enable_plane(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2029

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2100

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2110

if (resource_is_pipe_topology_changed(dc->current_state, context))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2111

resource_log_pipe_topology_update(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2115

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2131

if (context->res_ctx.pipe_ctx[i].plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2144

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2145

&context->res_ctx.pipe_ctx[i]);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2155

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2169

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2170

&& !context->res_ctx.pipe_ctx[i].top_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2171

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2172

&& context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2173

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2178

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2179

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2188

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2189

(context->res_ctx.pipe_ctx[i].plane_state &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2190

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) ==

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2206

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

hws->funcs.update_odm(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2219

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

hws->funcs.program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2235

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2236

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2244

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2250

hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2258

context->stream_status[0].plane_count > 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2266

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2278

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2283

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2293

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2296

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2307

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2316

dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2334

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2343

if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2350

dc->hwss.update_phantom_vp_position(dc, context, pipe);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2351

dcn401_program_pipe(dc, pipe, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

dc->hwseq->funcs.update_force_pstate(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2375

hwseq->funcs.program_mall_pipe_config(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2386

context->stream_status[0].plane_count > 1) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2401

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2407

if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2411

dc->hwss.prepare_bandwidth(dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2415

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

719

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

735

*opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

759

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

780

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

822

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

883

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

101

void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

102

void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

103

bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

49

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

70

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

74

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

77

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

79

void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

83

void dcn401_update_odm(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

86

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

87

void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

88

void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

92

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

95

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

99

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

221

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

223

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

228

int num_planes, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

230

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

232

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

234

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

248

void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

255

struct dc_state *context, bool lock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

294

void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

295

bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

296

void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

333

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

336

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

347

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

349

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

351

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

405

void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

406

void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

407

void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

409

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

419

struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

436

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

440

void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

442

void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

456

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

459

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

464

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

473

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

476

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

520

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

539

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

558

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

561

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

564

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

567

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

102

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

141

void (*update_odm)(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

145

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

151

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

160

void (*PLAT_58856_wa)(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

164

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

165

void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

166

void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

167

void (*update_mall_sel)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

172

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

176

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

181

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

78

void (*init_pipes)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

79

void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

101

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

110

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

137

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

151

void (*release_pipe)(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

184

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

210

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

220

int (*get_power_profile)(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

221

unsigned int (*get_det_buffer_size)(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

226

bool (*program_mcache_pipe_config)(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

86

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

89

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

94

struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/dcn_calcs.h

624

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

286

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

303

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

466

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

470

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

110

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

121

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

160

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

323

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

574

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

579

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

584

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

607

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/inc/resource.h

610

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

614

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

637

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

656

bool resource_is_hpo_acquired(struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

370

static const struct dc_tunnel_settings *get_dp_tunnel_settings(const struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

377

if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) {

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

378

dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

825

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

828

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

842

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

851

stream = context->res_ctx.pipe_ctx[i].stream;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

862

context->bw_ctx.bw.dce.dispclk_khz = 681000;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

863

context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

871

context->bw_ctx.bw.dce.dispclk_khz = 352000;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

873

context->bw_ctx.bw.dce.dispclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

875

context->bw_ctx.bw.dce.yclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

882

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

886

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

887

if (context->stream_status[i].plane_count == 0)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

890

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

893

if (context->stream_status[i].plane_states[0]->format

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

903

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

905

if (!dce100_validate_surface_sets(context))

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

46

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.h

50

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1005

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1006

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1007

context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1008

context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1009

context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1010

context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1011

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1012

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1013

context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1014

context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1015

context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1016

context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1017

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1018

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1019

context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1020

context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1021

context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1022

context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1023

context->bw_ctx.bw.dce.stutter_mode_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1024

context->bw_ctx.bw.dce.cpuc_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1025

context->bw_ctx.bw.dce.cpup_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1026

context->bw_ctx.bw.dce.nbp_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1027

context->bw_ctx.bw.dce.all_displays_in_sync,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1028

context->bw_ctx.bw.dce.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1029

context->bw_ctx.bw.dce.sclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1030

context->bw_ctx.bw.dce.sclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1031

context->bw_ctx.bw.dce.yclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1032

context->bw_ctx.bw.dce.blackout_recovery_time_us);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1048

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1052

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1053

if (context->stream_status[i].plane_count == 0)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1056

if (context->stream_status[i].plane_count > 2)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1059

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1061

context->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1080

if (context->streams[i]->timing.pixel_encoding

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1094

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1096

if (!dce110_validate_surface_sets(context))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

942

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

945

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

965

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

978

context->res_ctx.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

980

&context->bw_ctx.bw.dce))

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

986

context->streams[0]->timing.h_addressable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

987

context->streams[0]->timing.v_addressable,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

988

context->streams[0]->timing.pix_clk_100hz / 10);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

991

&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1002

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1005

if (context->stream_status[i].plane_states[0]->format

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1034

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

1036

if (!dce112_validate_surface_sets(context))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

871

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

874

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

888

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

901

context->res_ctx.pipe_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

903

&context->bw_ctx.bw.dce))

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

912

&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

926

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

927

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

928

context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

929

context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

930

context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

931

context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

932

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

933

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

934

context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

935

context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

936

context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

937

context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

938

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

939

context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

940

context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

941

context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

942

context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

943

context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

944

context->bw_ctx.bw.dce.stutter_mode_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

945

context->bw_ctx.bw.dce.cpuc_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

946

context->bw_ctx.bw.dce.cpup_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

947

context->bw_ctx.bw.dce.nbp_state_change_enable,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

948

context->bw_ctx.bw.dce.all_displays_in_sync,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

949

context->bw_ctx.bw.dce.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

950

context->bw_ctx.bw.dce.sclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

951

context->bw_ctx.bw.dce.sclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

952

context->bw_ctx.bw.dce.yclk_khz,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

953

context->bw_ctx.bw.dce.blackout_recovery_time_us);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

960

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

966

&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

978

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

986

&context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

994

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

998

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

999

if (context->stream_status[i].plane_count == 0)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

42

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.h

47

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1048

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1051

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1131

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1137

voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1153

static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1162

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1163

if (context->stream_status[i].plane_count == 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1166

if (context->stream_status[i].plane_count > 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1169

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1172

for (j = 0; j < context->stream_status[i].plane_count; j++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1174

context->stream_status[i].plane_states[j];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1196

if (context->stream_count > 1 && mpo_enabled)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1310

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1313

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1595

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1607

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1611

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1615

wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1617

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1618

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1626

dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1758

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1764

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1781

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1793

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1817

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1826

struct vba_vars_st *v = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1829

if (context->stream_count > 1) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1836

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1860

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1878

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1881

for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1886

if (vlevel > context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1897

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1899

bool split4mpc = context->stream_count == 1 && plane_count == 1

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1902

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2005

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2021

dcn20_merge_pipes_for_validate(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2024

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2034

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2036

if (vlevel > context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2039

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2046

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2054

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2055

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2058

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2062

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2073

&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2079

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2083

dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2087

if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2089

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2092

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2095

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2109

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2110

context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2127

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2138

voltage_supported = dcn20_validate_bandwidth_fp(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2210

void dcn20_release_pipe(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2215

dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

119

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

122

enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

125

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

128

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

156

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

163

enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

66

void dcn20_release_pipe(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

767

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

783

dcn20_merge_pipes_for_validate(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

786

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

800

context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

802

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

804

if (vlevel > context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

812

context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

814

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

815

if (vlevel > context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

819

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

822

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

824

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

846

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

854

if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

855

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

858

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

862

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

874

hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

878

dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

882

if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

884

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

887

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

890

&context->res_ctx, dc->res_pool,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

903

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

904

context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

926

static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

937

voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.h

49

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1320

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1325

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1328

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1375

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1380

struct display_mode_lib *dml = &context->bw_ctx.dml;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1388

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1392

struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1398

wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1409

wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1584

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1590

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1591

pipe = &context->res_ctx.pipe_ctx[old_index];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1599

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1600

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1614

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1615

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1626

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1639

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1645

context->bw_ctx.dml.vba.maxMpcComb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1646

context->bw_ctx.dml.vba.VoltageLevel = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1647

context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1648

dc->res_pool->funcs->update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1649

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1656

dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1664

context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1666

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1668

if (vlevel < context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1669

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1672

(validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states ||

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1681

context->bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1682

context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1685

vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1686

if (vlevel < context->bw_ctx.dml.soc.num_states) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1689

vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1691

context->bw_ctx.dml.validate_max_state = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1694

dml_log_mode_support_params(&context->bw_ctx.dml);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1696

if (vlevel == context->bw_ctx.dml.soc.num_states)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1701

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1722

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1767

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1796

hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1802

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1819

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1824

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1838

pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1843

dc, &context->res_ctx,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1849

dcn20_build_mapped_resource(dc, context, pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1853

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1862

if (!dcn20_validate_dsc(dc, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1868

pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1869

context->bw_ctx.dml.vba.VoltageLevel = vlevel;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1883

static int get_refresh_rate(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1889

if (context == NULL || context->streams[0] == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1893

timing = &context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1912

static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1923

if (context == NULL || context->streams[0] == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1927

timing = &context->streams[0]->timing;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1942

static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1947

if (context == NULL || context->streams[0] == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1950

refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1951

min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1959

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1965

if (context == NULL || context->streams[0] == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1968

if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1977

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1981

if (context->stream_count != 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1984

refresh_rate = get_refresh_rate(context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1988

if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1991

if (!context->streams[0]->allow_freesync)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1994

if (context->streams[0]->vrr_active_variable && (dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE))

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1997

stream_status = dc_state_get_stream_status(context, context->streams[0]);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2010

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2012

ASSERT(dc != NULL && context != NULL);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2013

if (dc == NULL || context == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2017

context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2020

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2023

dcn30_fpu_update_soc_for_wm_a(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2028

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2034

dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2039

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2058

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2076

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2085

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

103

bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

104

void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

105

int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

50

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

59

enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

63

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

70

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

74

void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.h

79

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1374

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1380

dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1617

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1626

pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1642

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1647

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1652

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1702

context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1710

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1713

} else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1715

context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1716

} else if (context->stream_count >= 3 && upscaled) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1717

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1724

const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1726

return context->bw_ctx.dml.ip.det_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1730

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1736

dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1752

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1757

dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1762

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1781

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1798

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1806

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

41

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

44

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

49

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

58

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

67

const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1670

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1677

pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1700

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1720

out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1737

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1745

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.h

43

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1634

static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1637

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1640

if (context->stream_count != 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1642

if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1665

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1670

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1672

const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1674

bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1677

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1705

&context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1783

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1785

if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1786

context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1793

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1799

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1812

static int dcn315_get_power_profile(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1814

return !context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1611

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1616

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1618

const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1621

dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1668

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1670

if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1671

context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1672

ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1678

context->bw_ctx.dml.ip.det_buffer_size_kbytes =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1681

context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1641

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1647

struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1653

phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1677

dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1685

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1691

struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1693

phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1702

dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1705

dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1712

void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1723

phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1727

dcn32_enable_phantom_plane(dc, context, phantom_stream, index);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1730

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1736

dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1746

static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1760

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1761

context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1771

out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1787

dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1790

dcn32_override_min_req_memclk(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1793

dcn32_override_min_req_dcfclk(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1801

dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1815

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1823

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1824

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1826

if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1827

dc_state_set_stream_cursor_subvp_limit(stream, context, false);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1832

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1833

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1836

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1838

if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1840

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1841

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1843

if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1845

!dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1847

dc_state_set_stream_cursor_subvp_limit(stream, context, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1856

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1857

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1860

status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1867

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1872

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1885

dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1890

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1891

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1892

mall_type = dc_state_get_stream_subvp_type(context, stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1909

mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1935

mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1968

switch (dc_state_get_pipe_subvp_type(context, pipe)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2014

dcn32_set_det_allocations(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2019

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2020

context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2022

context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2056

void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2062

dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

102

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

106

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

111

struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

123

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

126

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

129

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

132

struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

134

bool dcn32_mpo_in_use(struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

136

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

158

void dcn32_release_pipe(struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

163

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

166

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

169

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

177

double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

181

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

183

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

185

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

187

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

96

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

108

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

114

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

132

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

154

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

159

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

171

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

176

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

178

if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

184

bool dcn32_mpo_in_use(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

188

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

189

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

196

bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

201

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

243

static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

251

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

252

if (context->stream_status[i].plane_count > 1)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

255

if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

260

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

262

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

277

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

312

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

322

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

324

if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

330

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

331

if (dc_state_get_stream_subvp_type(context, context->streams[i]) == SUBVP_PHANTOM)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

334

if (context->stream_status[i].plane_count > 0)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

335

plane_segments = stream_segments / context->stream_status[i].plane_count;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

340

if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

348

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

350

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

351

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

359

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

360

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

368

override_det_for_subvp(dc, context, pipe_segments);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

370

if (!context->res_ctx.pipe_ctx[i].stream)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

381

void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

385

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

414

dcn32_determine_det_override(dc, context, pipes);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

515

struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

524

if (context == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

533

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

539

if (context->stream_count > 2)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

541

else if (context->stream_count == 2) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

543

dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

546

fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

548

is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, fpo_candidate_stream, dc->debug.fpo_vactive_min_active_margin_us);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

553

fpo_candidate_stream = context->streams[0];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

555

fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

585

(context->stream_count > 1 && !(dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_ENABLE))))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

644

bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

656

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

657

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

704

bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

711

struct vba_vars_st *vba = &context->bw_ctx.dml.vba;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

717

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

718

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

750

void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

754

struct resource_context *res_ctx = &context->res_ctx;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

776

void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

778

if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

779

context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

92

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

94

if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

98

return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1736

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1741

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1742

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1749

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1764

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1771

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1716

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1721

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1722

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1729

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1736

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1743

ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1717

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1722

out = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1723

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1730

dcn35_decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1738

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1745

ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1638

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1646

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1647

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1649

if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1650

dc_state_set_stream_cursor_subvp_limit(stream, context, false);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1655

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1656

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1659

if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1661

for (i = 0; i < context->stream_count; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1662

stream = context->streams[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1664

if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1666

!dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1668

dc_state_set_stream_cursor_subvp_limit(stream, context, true);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1677

status = dml2_validate(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1678

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1686

struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1689

dml2_prepare_mcache_programming(dc, context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1690

context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1756

static int dcn401_get_power_profile(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1758

int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1761

for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1762

if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1763

uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1765

if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

26

struct dc_state *context,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

29

void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);

sys/dev/pci/drm/amd/display/include/logger_interface.h

52

struct dc_state *context);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

1005

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

130

if (!psp->dtm_context.context.initialized) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

136

dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

177

if (!psp->dtm_context.context.initialized) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

183

dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

258

if (!psp->hdcp_context.context.initialized) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

266

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

301

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

333

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

378

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

404

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

447

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

482

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

509

if (!psp->hdcp_context.context.initialized) {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

519

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

556

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

57

dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

590

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

622

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

682

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

728

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

761

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

796

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

844

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

873

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

925

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

93

dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.c

969

hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

938

bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

940

return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

73

bool mod_power_only_edp(const struct dc_state *context,

sys/dev/pci/drm/amd/pm/powerplay/inc/ppinterrupt.h

41

void *context; /* Pointer to callback function context */

sys/dev/pci/drm/apple/iomfb.c

110

enum dcp_context_id context)

sys/dev/pci/drm/apple/iomfb.c

112

switch (context) {

sys/dev/pci/drm/apple/iomfb.c

160

enum dcp_context_id context = dcp_call_context(dcp, oob);

sys/dev/pci/drm/apple/iomfb.c

161

struct dcp_channel *ch = dcp_get_channel(dcp, context);

sys/dev/pci/drm/apple/iomfb.c

177

void *out = dcp->shmem + dcp_tx_offset(context) + offset;

sys/dev/pci/drm/apple/iomfb.c

186

trace_iomfb_push(dcp, call, context, offset, depth);

sys/dev/pci/drm/apple/iomfb.c

194

dcpep_msg(context, data_len, offset));

sys/dev/pci/drm/apple/iomfb.c

217

void dcp_ack(struct apple_dcp *dcp, enum dcp_context_id context)

sys/dev/pci/drm/apple/iomfb.c

219

struct dcp_channel *ch = dcp_get_channel(dcp, context);

sys/dev/pci/drm/apple/iomfb.c

223

dcpep_ack(context));

sys/dev/pci/drm/apple/iomfb.c

257

static void dcpep_handle_cb(struct apple_dcp *dcp, enum dcp_context_id context,

sys/dev/pci/drm/apple/iomfb.c

264

struct dcp_channel *ch = dcp_get_channel(dcp, context);

sys/dev/pci/drm/apple/iomfb.c

286

dcp_ack(dcp, context);

sys/dev/pci/drm/apple/iomfb.c

289

static void dcpep_handle_ack(struct apple_dcp *dcp, enum dcp_context_id context,

sys/dev/pci/drm/apple/iomfb.c

293

struct dcp_channel *ch = dcp_get_channel(dcp, context);

sys/dev/pci/drm/apple/iomfb.c

298

dev_warn(dcp->dev, "ignoring ack on context %X\n", context);

sys/dev/pci/drm/apple/iomfb_internal.h

110

void dcp_ack(struct apple_dcp *dcp, enum dcp_context_id context);

sys/dev/pci/drm/apple/trace.h

228

const struct dcp_method_entry *method, int context,

sys/dev/pci/drm/apple/trace.h

230

TP_ARGS(dcp, method, context, offset, depth),

sys/dev/pci/drm/apple/trace.h

235

__field(int, context)

sys/dev/pci/drm/apple/trace.h

242

__entry->context = context; __entry->offset = offset;

sys/dev/pci/drm/apple/trace.h

247

__get_str(devname), __get_str(name), __entry->context,

sys/dev/pci/drm/dma-resv.c

310

if ((old->context == fence->context && old_usage >= usage &&

sys/dev/pci/drm/dma-resv.c

343

void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context,

sys/dev/pci/drm/dma-resv.c

357

if (old->context != context)

sys/dev/pci/drm/drm_edid.c

2338

typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);

sys/dev/pci/drm/drm_edid.c

2342

void *context)

sys/dev/pci/drm/drm_edid.c

2349

if (read_block(context, block, block_num, EDID_LENGTH))

sys/dev/pci/drm/drm_edid.c

2374

read_block_fn read_block, void *context,

sys/dev/pci/drm/drm_edid.c

2397

status = edid_block_read(edid, 0, read_block, context);

sys/dev/pci/drm/drm_edid.c

2439

status = edid_block_read(block, i, read_block, context);

sys/dev/pci/drm/drm_edid.c

2669

void *context)

sys/dev/pci/drm/drm_edid.c

2675

edid = _drm_do_get_edid(connector, read_block, context, &size);

sys/dev/pci/drm/drm_linux.c

1956

struct mutex *lock, uint64_t context, uint64_t seqno)

sys/dev/pci/drm/drm_linux.c

1960

fence->context = context;

sys/dev/pci/drm/drm_linux.c

1970

struct mutex *lock, uint64_t context, uint64_t seqno)

sys/dev/pci/drm/drm_linux.c

1972

dma_fence_init(fence, ops, lock, context, seqno);

sys/dev/pci/drm/drm_linux.c

2306

dma_fence_array_create(int num_fences, struct dma_fence **fences, u64 context,

sys/dev/pci/drm/drm_linux.c

2317

context, seqno);

sys/dev/pci/drm/drm_linux.c

2386

if ((*df)->context != fence->context)

sys/dev/pci/drm/drm_linux.c

2402

uint64_t context;

sys/dev/pci/drm/drm_linux.c

2412

context = prev->context;

sys/dev/pci/drm/drm_linux.c

2415

context = dma_fence_context_alloc(1);

sys/dev/pci/drm/drm_linux.c

2420

context = dma_fence_context_alloc(1);

sys/dev/pci/drm/drm_linux.c

2424

context, seqno);

sys/dev/pci/drm/drm_privacy_screen_x86.c

22

void *context, void **return_value)

sys/dev/pci/drm/drm_suballoc.c

415

idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1);

sys/dev/pci/drm/drm_suballoc.c

449

(unsigned long long)i->fence->context);

sys/dev/pci/drm/drm_syncobj.c

1787

if (iter->context != fence->context) {

sys/dev/pci/drm/i915/display/intel_cdclk.c

2503

const char *context)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2506

context, cdclk_config->cdclk, cdclk_config->vco,

sys/dev/pci/drm/i915/display/intel_cdclk.c

2545

enum pipe pipe, const char *context)

sys/dev/pci/drm/i915/display/intel_cdclk.c

2555

intel_cdclk_dump_config(display, cdclk_config, context);

sys/dev/pci/drm/i915/display/intel_cdclk.h

40

const char *context);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

178

const char *context)

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.c

195

str_yes_no(pipe_config->hw.enable), context);

sys/dev/pci/drm/i915/display/intel_crtc_state_dump.h

15

const char *context);

sys/dev/pci/drm/i915/display/intel_display_reset.c

25

modeset_stuck_fn modeset_stuck, void *context)

sys/dev/pci/drm/i915/display/intel_display_reset.c

37

modeset_stuck(context);

sys/dev/pci/drm/i915/display/intel_display_reset.h

13

typedef void modeset_stuck_fn(void *context);

sys/dev/pci/drm/i915/display/intel_display_reset.h

17

modeset_stuck_fn modeset_stuck, void *context);

sys/dev/pci/drm/i915/display/intel_overlay.c

1420

overlay->context = engine->kernel_context;

sys/dev/pci/drm/i915/display/intel_overlay.c

191

struct intel_context *context;

sys/dev/pci/drm/i915/display/intel_overlay.c

243

rq = i915_request_create(overlay->context);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1938

struct intel_sseu *context)

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1957

if (overflows_type(user->slice_mask, context->slice_mask) ||

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1958

overflows_type(user->subslice_mask, context->subslice_mask) ||

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1960

context->min_eus_per_subslice) ||

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1962

context->max_eus_per_subslice))

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1975

context->slice_mask = user->slice_mask;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1976

context->subslice_mask = user->subslice_mask;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1977

context->min_eus_per_subslice = user->min_eus_per_subslice;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1978

context->max_eus_per_subslice = user->max_eus_per_subslice;

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1984

unsigned int req_s = hweight8(context->slice_mask);

sys/dev/pci/drm/i915/gem/i915_gem_context.c

1985

unsigned int req_ss = hweight8(context->subslice_mask);

sys/dev/pci/drm/i915/gem/i915_gem_context.h

245

struct intel_sseu *context);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2278

if (intel_context_is_parallel(eb->context))

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2287

if (!eb->context->vm->has_read_only) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2310

shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2341

err = intel_engine_cmd_parser(eb->context->engine,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2358

if (intel_context_is_parallel(eb->context))

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2375

if (intel_context_nopreempt(rq->context))

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2390

if (rq->context->engine->emit_init_breadcrumb) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2391

err = rq->context->engine->emit_init_breadcrumb(rq);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2396

err = rq->context->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2405

GEM_BUG_ON(intel_context_is_parallel(rq->context));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2407

err = rq->context->engine->emit_bb_start(rq,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

252

struct intel_context *context; /* logical state for the request */

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2555

struct intel_context *ce = eb->context, *child;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2606

struct intel_context *ce = eb->context, *child;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2738

eb->context = ce;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2764

i915_vm_put(eb->context->vm);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2771

intel_gt_pm_put(eb->context->engine->gt, eb->wakeref);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2772

for_each_child(eb->context, child)

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2774

intel_context_put(eb->context);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3108

if (likely(!intel_context_is_closed(eb->context))) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3117

if (intel_context_is_parallel(eb->context)) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3216

GEM_BUG_ON(!intel_context_is_parent(eb->context));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3230

eb->context->parallel.fence_context,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3231

eb->context->parallel.seqno++,

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

326

return intel_engine_requires_cmd_parser(eb->context->engine) ||

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

327

(intel_engine_using_cmd_parser(eb->context->engine) &&

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3287

if (intel_context_is_parallel(eb->context)) {

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3306

return eb->context;

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3308

for_each_child(eb->context, child)

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

3354

GEM_BUG_ON(intel_context_is_parallel(eb->context));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

781

err = mutex_lock_interruptible(&eb->context->vm->mutex);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

783

err = i915_gem_evict_vm(eb->context->vm, &eb->ww, NULL);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

784

mutex_unlock(&eb->context->vm->mutex);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

792

err = mutex_lock_interruptible(&eb->context->vm->mutex);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

796

err = i915_gem_evict_vm(eb->context->vm, &eb->ww, &busy_bo);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

797

mutex_unlock(&eb->context->vm->mutex);

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

889

struct i915_address_space *vm = eb->context->vm;

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

202

if (!to_gt(i915)->migrate.context || intel_gt_is_wedged(to_gt(i915)))

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

215

intel_engine_pm_get(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

216

ret = intel_context_migrate_clear(to_gt(i915)->migrate.context, deps,

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

229

intel_engine_pm_get(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

230

ret = intel_context_migrate_copy(to_gt(i915)->migrate.context,

sys/dev/pci/drm/i915/gem/i915_gem_ttm_move.c

242

intel_engine_pm_put(to_gt(i915)->migrate.context->engine);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

116

static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

150

static int wc_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

173

static int wc_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

194

static int gpu_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

23

static int cpu_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

252

static bool always_valid(struct context *ctx)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

257

static bool needs_fence_registers(struct context *ctx)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

267

static bool needs_mi_store_dword(struct context *ctx)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

277

int (*set)(struct context *ctx, unsigned long offset, u32 v);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

278

int (*get)(struct context *ctx, unsigned long offset, u32 *v);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

279

bool (*valid)(struct context *ctx);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

314

struct context ctx;

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

54

static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c

82

static int gtt_set(struct context *ctx, unsigned long offset, u32 v)

sys/dev/pci/drm/i915/gem/selftests/i915_gem_mman.c

1217

err = intel_context_migrate_clear(to_gt(i915)->migrate.context, NULL,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

486

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

748

return i915_ggtt_offset(rq->context->state) +

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

115

if (rq->context != ce)

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

353

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

414

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

440

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_breadcrumbs.c

505

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_context.c

506

GEM_BUG_ON(rq->context == ce);

sys/dev/pci/drm/i915/gt/intel_context.c

581

if (rq->context != ce)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1326

frame->rq.context = ce;

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2031

DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2192

rq->context->lrc.ccid,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2193

intel_context_is_closed(rq->context) ? "!" : "",

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2194

intel_context_is_banned(rq->context) ? "*" : "");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2206

rq->context->lrc.ccid,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2207

intel_context_is_closed(rq->context) ? "!" : "",

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2208

intel_context_is_banned(rq->context) ? "*" : "");

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2319

if (rq->context->lrc_reg_state) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2321

hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

2498

struct intel_timeline *tl = request->context->timeline;

sys/dev/pci/drm/i915/gt/intel_engine_heartbeat.c

110

rq->fence.context,

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

123

GEM_BUG_ON(rq->context->active_count != 1);

sys/dev/pci/drm/i915/gt/intel_engine_pm.c

125

rq->context->wakeref = intel_wakeref_track(&engine->gt->wakeref);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1015

inflight = intel_context_inflight(&ve->context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1055

GEM_BUG_ON(READ_ONCE(ve->context.inflight));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1057

lrc_update_offsets(&ve->context, engine);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1149

return rq->context->lrc.ccid == READ_ONCE(el->yield);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1247

if (unlikely(intel_context_is_banned(rq->context) || bad_request(rq)))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1323

last->fence.context,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1350

last->fence.context, last->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1421

GEM_BUG_ON(rq->context != &ve->context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1436

rq->fence.context,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1521

if (last->context == rq->context)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1543

if (ctx_single_port_submission(last->context) ||

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1544

ctx_single_port_submission(rq->context))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1557

!can_merge_ctx(last->context,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1558

rq->context));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

176

struct intel_context context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1968

rq->context->lrc_reg_state;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

1983

rq->fence.context,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2032

prev_ce = (*prev)->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2034

active_ce = (*execlists->active)->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2300

if (rq->context->lrc.ccid == ccid) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2309

if (rq->context->lrc.ccid == ccid) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2346

cap->rq = active_request(cap->rq->context->timeline, cap->rq);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2717

struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(rq->context->vm);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2775

GEM_BUG_ON(!intel_context_is_pinned(request->context));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2792

if (!i915_vm_is_4lvl(request->context->vm)) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3042

ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3345

if (inflight->context == rq->context)

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3351

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3352

inflight->fence.context, inflight->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3614

GEM_BUG_ON(ve->context.inflight);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3660

lrc_fini(&ve->context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3661

intel_context_fini(&ve->context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3675

container_of(kref, typeof(*ve), context.ref);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3677

GEM_BUG_ON(!list_empty(&ve->context.signals));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3690

queue_rcu_work(ve->context.engine->i915->unordered_wq, &ve->rcu);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3717

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3726

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3734

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3741

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3752

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3810

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3896

if (intel_context_inflight(&ve->context))

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3907

rq->fence.context,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3997

intel_context_init(&ve->context, &ve->base);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

404

rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4076

return &ve->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

4079

intel_context_put(&ve->context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

432

struct intel_context * const ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

451

rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

476

struct intel_context * const ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

530

struct intel_context * const ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

560

struct virtual_engine *ve = container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

651

struct intel_context * const ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

675

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

743

rq->context->lrc.ccid,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

744

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

811

if (ce == rq->context) {

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

818

ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

987

if (!can_merge_ctx(prev->context, next->context))

sys/dev/pci/drm/i915/gt/intel_gt.c

593

GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));

sys/dev/pci/drm/i915/gt/intel_gt.c

594

if (!rq->context->state)

sys/dev/pci/drm/i915/gt/intel_gt.c

599

state = shmem_create_from_object(rq->context->state->obj);

sys/dev/pci/drm/i915/gt/intel_gt.c

601

state = uao_create_from_object(rq->context->state->obj);

sys/dev/pci/drm/i915/gt/intel_gt.c

627

ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_migrate.c

1093

if (!m->context)

sys/dev/pci/drm/i915/gt/intel_migrate.c

1098

ce = intel_context_get(m->context);

sys/dev/pci/drm/i915/gt/intel_migrate.c

1130

if (!m->context)

sys/dev/pci/drm/i915/gt/intel_migrate.c

1135

ce = intel_context_get(m->context);

sys/dev/pci/drm/i915/gt/intel_migrate.c

1155

ce = fetch_and_zero(&m->context);

sys/dev/pci/drm/i915/gt/intel_migrate.c

277

m->context = ce;

sys/dev/pci/drm/i915/gt/intel_migrate.c

314

ce = __migrate_engines(m->context->engine->gt);

sys/dev/pci/drm/i915/gt/intel_migrate.c

322

ce->vm = i915_vm_get(m->context->vm);

sys/dev/pci/drm/i915/gt/intel_migrate.c

370

const u64 encode = rq->context->vm->pte_encode(0, pat_index,

sys/dev/pci/drm/i915/gt/intel_migrate.c

699

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/intel_migrate.c

998

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/intel_migrate_types.h

12

struct intel_context *context;

sys/dev/pci/drm/i915/gt/intel_reset.c

119

ctx = rcu_dereference(rq->context->gem_context);

sys/dev/pci/drm/i915/gt/intel_reset.c

144

intel_context_ban(rq->context, rq);

sys/dev/pci/drm/i915/gt/intel_reset.c

70

if (intel_context_is_closed(rq->context))

sys/dev/pci/drm/i915/gt/intel_reset.c

74

ctx = rcu_dereference(rq->context->gem_context);

sys/dev/pci/drm/i915/gt/intel_reset.c

79

return intel_context_is_banned(rq->context);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

1025

GEM_BUG_ON(!intel_context_is_pinned(request->context));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

659

if (rq->context == ce) {

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

959

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/intel_rps.c

1029

if (test_bit(CONTEXT_LOW_LATENCY, &rq->context->flags))

sys/dev/pci/drm/i915/gt/intel_rps.c

1053

rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/gt/intel_rps.c

1068

rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/gt/intel_timeline.h

47

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.h

49

return i915_syncmap_set(&tl->sync, context, seqno);

sys/dev/pci/drm/i915/gt/intel_timeline.h

55

return __intel_timeline_sync_set(tl, fence->context, fence->seqno);

sys/dev/pci/drm/i915/gt/intel_timeline.h

59

u64 context, u32 seqno)

sys/dev/pci/drm/i915/gt/intel_timeline.h

61

return i915_syncmap_is_later(&tl->sync, context, seqno);

sys/dev/pci/drm/i915/gt/intel_timeline.h

67

return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

101

rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2074

clear_bit(CONTEXT_BANNED, &rq->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2082

intel_context_ban(rq->context, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2118

clear_bit(CONTEXT_BANNED, &rq[0]->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2134

clear_bit(CONTEXT_BANNED, &rq[1]->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2141

intel_context_ban(rq[1]->context, rq[1]);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2189

clear_bit(CONTEXT_BANNED, &rq[0]->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2203

clear_bit(CONTEXT_BANNED, &rq[1]->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2224

intel_context_ban(rq[2]->context, rq[2]);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2285

clear_bit(CONTEXT_BANNED, &rq->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2293

intel_context_ban(rq->context, rq);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2341

clear_bit(CONTEXT_BANNED, &rq->context->flags);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

2349

intel_context_set_banned(rq->context);

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3791

request[nc]->fence.context,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3796

request[nc]->fence.context,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3958

request[n]->fence.context,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

3963

request[n]->fence.context,

sys/dev/pci/drm/i915/gt/selftest_execlists.c

91

rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

100

offset_in_page(sizeof(u32) * rq->fence.context);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1101

engine->name, rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1102

rq->fence.seqno, rq->context->guc_id.id, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1111

rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1112

rq->fence.seqno, rq->context->guc_id.id);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

1128

rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

255

return READ_ONCE(h->seqno[rq->fence.context % (PAGE_SIZE/sizeof(u32))]);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

781

engine->name, rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

782

rq->fence.seqno, rq->context->guc_id.id, err);

sys/dev/pci/drm/i915/gt/selftest_hangcheck.c

878

rq->fence.context,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

1028

if (!gt->migrate.context)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

151

GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

234

if (!m->context)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

239

ce = intel_context_get(m->context);

sys/dev/pci/drm/i915/gt/selftest_migrate.c

263

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

430

return intel_context_migrate_copy(migrate->context, NULL,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

44

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

469

return intel_context_migrate_clear(migrate->context, NULL,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

492

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

514

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

550

struct drm_i915_private *i915 = migrate->context->engine->i915;

sys/dev/pci/drm/i915/gt/selftest_migrate.c

804

if (!gt->migrate.context)

sys/dev/pci/drm/i915/gt/selftest_migrate.c

903

err = __perf_clear_blt(gt->migrate.context,

sys/dev/pci/drm/i915/gt/selftest_migrate.c

994

err = __perf_copy_blt(gt->migrate.context,

sys/dev/pci/drm/i915/gt/selftest_timeline.c

863

lockdep_unpin_lock(&from->context->timeline->mutex, from->cookie);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

864

mutex_unlock(&from->context->timeline->mutex);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

868

mutex_lock(&to->context->timeline->mutex);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

869

to->cookie = lockdep_pin_lock(&to->context->timeline->mutex);

sys/dev/pci/drm/i915/gt/selftest_timeline.c

958

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/selftests/mock_timeline.c

11

void mock_timeline_init(struct intel_timeline *timeline, u64 context)

sys/dev/pci/drm/i915/gt/selftests/mock_timeline.c

14

timeline->fence_context = context;

sys/dev/pci/drm/i915/gt/selftests/mock_timeline.h

14

void mock_timeline_init(struct intel_timeline *timeline, u64 context);

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c

175

engine = rq->context->engine;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

139

struct intel_context context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3486

container_of(ce, typeof(*ve), context);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

386

return intel_context_to_parent(rq->context);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

3884

GEM_BUG_ON(!intel_context_is_pinned(rq->context));

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5519

rq->context->guc_id.id,

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5642

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5689

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5733

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5783

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5827

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5859

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5943

intel_context_init(&ve->context, &ve->base);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5995

return &ve->context;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

5998

intel_context_put(&ve->context);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

793

rq->context->lrc_reg_state[CTX_RING_TAIL] =

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

804

return intel_context_is_parallel(rq->context);

sys/dev/pci/drm/i915/gvt/scheduler.c

131

struct intel_context *ctx = workload->req->context;

sys/dev/pci/drm/i915/gvt/scheduler.c

264

return intel_context_force_single_submission(rq->context);

sys/dev/pci/drm/i915/gvt/scheduler.c

369

if (GRAPHICS_VER(req->engine->i915) == 9 && is_inhibit_context(req->context))

sys/dev/pci/drm/i915/gvt/scheduler.c

597

(struct execlist_ring_context *)rq->context->lrc_reg_state;

sys/dev/pci/drm/i915/gvt/scheduler.c

66

struct intel_context *ctx = workload->req->context;

sys/dev/pci/drm/i915/gvt/scheduler.c

942

struct intel_context *ctx = workload->req->context;

sys/dev/pci/drm/i915/i915_active.c

998

GEM_BUG_ON(!intel_context_is_barrier(rq->context));

sys/dev/pci/drm/i915/i915_config.c

12

i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context)

sys/dev/pci/drm/i915/i915_config.c

14

if (CONFIG_DRM_I915_FENCE_TIMEOUT && context)

sys/dev/pci/drm/i915/i915_config.h

15

u64 context);

sys/dev/pci/drm/i915/i915_deps.c

196

if (!entry->context || entry->context != fence->context)

sys/dev/pci/drm/i915/i915_gpu_error.c

1473

erq->context = request->fence.context;

sys/dev/pci/drm/i915/i915_gpu_error.c

1481

if (!intel_context_is_closed(request->context)) {

sys/dev/pci/drm/i915/i915_gpu_error.c

1484

ctx = rcu_dereference(request->context->gem_context);

sys/dev/pci/drm/i915/i915_gpu_error.c

1681

ee->simulated |= record_context(&ee->context, ce);

sys/dev/pci/drm/i915/i915_gpu_error.c

1703

vma = engine_coredump_add_context(ee, rq->context, gfp);

sys/dev/pci/drm/i915/i915_gpu_error.c

1775

engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id);

sys/dev/pci/drm/i915/i915_gpu_error.c

1779

engine->name, rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/i915_gpu_error.c

2110

if (first && first->context.pid) {

sys/dev/pci/drm/i915/i915_gpu_error.c

2115

first->context.comm, first->context.pid);

sys/dev/pci/drm/i915/i915_gpu_error.c

521

prefix, erq->pid, erq->context, erq->seqno,

sys/dev/pci/drm/i915/i915_gpu_error.c

921

error_print_context(m, " Active context: ", &ee->context);

sys/dev/pci/drm/i915/i915_gpu_error.c

963

ee->context.comm,

sys/dev/pci/drm/i915/i915_gpu_error.c

964

ee->context.pid);

sys/dev/pci/drm/i915/i915_gpu_error.h

112

} context;

sys/dev/pci/drm/i915/i915_gpu_error.h

50

u32 context;

sys/dev/pci/drm/i915/i915_request.c

1025

rq->context = ce;

sys/dev/pci/drm/i915/i915_request.c

1294

if (!intel_context_use_semaphores(to->context))

sys/dev/pci/drm/i915/i915_request.c

1336

fence->context,

sys/dev/pci/drm/i915/i915_request.c

1343

return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);

sys/dev/pci/drm/i915/i915_request.c

1352

GEM_BUG_ON(intel_context_is_barrier(from->context));

sys/dev/pci/drm/i915/i915_request.c

1437

fence->context),

sys/dev/pci/drm/i915/i915_request.c

1469

return intel_context_is_parallel(rq->context);

sys/dev/pci/drm/i915/i915_request.c

1474

return intel_context_to_parent(rq->context);

sys/dev/pci/drm/i915/i915_request.c

1509

if (fence->context == rq->fence.context)

sys/dev/pci/drm/i915/i915_request.c

1616

if (fence->context == rq->fence.context)

sys/dev/pci/drm/i915/i915_request.c

1620

if (fence->context &&

sys/dev/pci/drm/i915/i915_request.c

1636

if (fence->context)

sys/dev/pci/drm/i915/i915_request.c

1706

struct intel_huc *huc = &rq->context->engine->gt->uc.huc;

sys/dev/pci/drm/i915/i915_request.c

1709

if (!rcu_access_pointer(rq->context->gem_context))

sys/dev/pci/drm/i915/i915_request.c

1768

bool same_context = prev->context == rq->context;

sys/dev/pci/drm/i915/i915_request.c

1942

ctx = rcu_dereference(rq->context->gem_context);

sys/dev/pci/drm/i915/i915_request.c

2320

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/i915_request.c

345

struct intel_context *ce = rq->context;

sys/dev/pci/drm/i915/i915_request.c

456

intel_context_exit(rq->context);

sys/dev/pci/drm/i915/i915_request.c

457

intel_context_unpin(rq->context);

sys/dev/pci/drm/i915/i915_request.c

529

if (!intel_context_inflight(signal->context))

sys/dev/pci/drm/i915/i915_request.c

536

if (rq->context == signal->context) {

sys/dev/pci/drm/i915/i915_request.c

687

if (unlikely(!intel_context_is_schedulable(request->context)))

sys/dev/pci/drm/i915/i915_request.c

820

intel_context_cancel_request(rq->context, rq);

sys/dev/pci/drm/i915/i915_request.h

213

struct intel_context *context;

sys/dev/pci/drm/i915/i915_request.h

675

test_bit(CONTEXT_IS_PARKING, &rq->context->flags));

sys/dev/pci/drm/i915/i915_request.h

68

rq__->fence.context, rq__->fence.seqno, \

sys/dev/pci/drm/i915/i915_request.h

682

return rcu_dereference_protected(rq->context->gem_context, true);

sys/dev/pci/drm/i915/selftests/i915_request.c

1232

GEM_BUG_ON(request[idx]->context->vm != batch->vm);

sys/dev/pci/drm/i915/selftests/i915_request.c

1362

GEM_BUG_ON(request[idx]->context->vm != batch->vm);

sys/dev/pci/drm/i915/selftests/i915_request.c

409

rq->fence.context, rq->fence.seqno,

sys/dev/pci/drm/i915/selftests/i915_request.c

425

rq->fence.context, rq->fence.seqno);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

163

static int check_one(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

167

err = i915_syncmap_set(sync, context, seqno);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

173

context, (*sync)->height, (*sync)->prefix);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

179

context);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

193

if (!i915_syncmap_is_later(sync, context, seqno)) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

195

context, seqno);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

217

u64 context = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

225

err = check_one(&sync, context,

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

238

static int check_leaf(struct i915_syncmap **sync, u64 context, u32 seqno)

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

242

err = i915_syncmap_set(sync, context, seqno);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

248

context, (*sync)->height, (*sync)->prefix);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

254

context, (*sync)->bitmap, hweight32((*sync)->bitmap));

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

262

if (!i915_syncmap_is_later(sync, context, seqno)) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

264

context, seqno);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

297

u64 context = BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

300

err = check_leaf(&sync, context, 0);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

321

if (__sync_child(join)[__sync_branch_idx(join, context)] != sync) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

346

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

348

err = i915_syncmap_set(&sync, context, 0);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

354

context, order, step, sync->height, sync->prefix);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

363

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

365

if (!i915_syncmap_is_later(&sync, context, 0)) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

367

context, order, step);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

373

if (i915_syncmap_is_later(&sync, context + idx, 0)) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

375

context + idx, order, step);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

385

u64 context = step * BIT_ULL(order);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

387

if (!i915_syncmap_is_later(&sync, context, 0)) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

389

context, order, step);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

414

u64 context = i915_prandom_u64_state(&prng) & ~MASK;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

417

if (i915_syncmap_is_later(&sync, context, 0)) /* Skip repeats */

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

421

err = i915_syncmap_set(&sync, context + idx, 0);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

427

context, sync->height, sync->prefix);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

434

context, idx,

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

469

u64 context = idx * BIT_ULL(order) + idx;

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

471

err = i915_syncmap_set(&sync, context, 0);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

477

context, order, idx,

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

562

u64 context = i915_prandom_u64_state(&prng);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

564

err = i915_syncmap_set(&sync, context, 0);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

582

u64 context = i915_prandom_u64_state(&ctx);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

584

if (i915_syncmap_is_later(&sync, context, seqno) != expect) {

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

586

context, last_seqno, seqno, expect);

sys/dev/pci/drm/i915/selftests/i915_syncmap.c

591

err = i915_syncmap_set(&sync, context, seqno);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

120

return i915_vma_offset(hws) + seqno_offset(rq->fence.context);

sys/dev/pci/drm/i915/selftests/igt_spinner.c

223

u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);

sys/dev/pci/drm/i915/selftests/intel_memory_region.c

1064

err = intel_context_migrate_clear(engine->gt->migrate.context, NULL,

sys/dev/pci/drm/include/drm/drm_edid.h

476

int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),

sys/dev/pci/drm/include/drm/drm_edid.h

477

void *context);

sys/dev/pci/drm/include/linux/dma-fence.h

119

if (a->context != b->context)

sys/dev/pci/drm/include/linux/dma-fence.h

19

uint64_t context;

sys/dev/pci/drm/include/linux/dma-resv.h

473

void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context,

sys/dev/pci/drm/include/uapi/drm/drm.h

300

int context;

sys/dev/pci/drm/include/uapi/drm/drm.h

405

int context; /**< Context handle */

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

1568

#define i915_execbuffer2_set_context_id(eb2, context) \

sys/dev/pci/drm/include/uapi/drm/i915_drm.h

1569

(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK

sys/dev/pci/drm/include/uapi/drm/radeon_drm.h

428

drm_radeon_context_regs_t context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

105

__entry->fence_context = fence->finished.context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

123

__entry->fence_context = sched_job->s_fence->finished.context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

125

__entry->ctx = fence->context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

144

__entry->fence_context = sched_job->s_fence->finished.context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

146

__entry->ctx = fence->context;

sys/dev/pci/drm/scheduler/gpu_scheduler_trace.h

76

__entry->fence_context = sched_job->s_fence->finished.context;

sys/dev/pci/drm/scheduler/sched_entity.c

426

if (fence->context == entity->fence_context ||

sys/dev/pci/drm/scheduler/sched_entity.c

427

fence->context == entity->fence_context + 1) {

sys/dev/pci/drm/scheduler/sched_main.c

1506

if (bad->s_fence->scheduled.context ==

sys/dev/pci/drm/scheduler/sched_main.c

753

guilty_context = s_job->s_fence->scheduled.context;

sys/dev/pci/drm/scheduler/sched_main.c

756

if (found_guilty && s_job->s_fence->scheduled.context == guilty_context)

sys/dev/pci/drm/scheduler/sched_main.c

904

if (entry->context != fence->context)

sys/dev/pci/if_ice.c

25190

prof->context = 0;

sys/dev/pci/if_icevar.h

3624

uint64_t context;

sys/dev/pci/if_oce.c

3336

ctx = &cmd.params.req.context;

sys/dev/pci/if_ocereg.h

939

union oce_mq_ctx context;

sys/dev/pci/if_ocereg.h

954

union oce_mq_ext_ctx context;

sys/dev/pci/vmwpvs.c

1015

u_int64_t ctx = c->context;

sys/dev/pci/vmwpvs.c

102

u_int64_t context;

sys/dev/pci/vmwpvs.c

131

u_int64_t context;

sys/dev/pci/vmwpvs.c

889

r->context = ccb->ccb_ctx;

sys/dev/usb/dwc2/dwc2_hcd.c

4115

struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,

sys/dev/usb/dwc2/dwc2_hcd.c

4118

struct usbd_xfer *xfer = context;

sys/dev/usb/dwc2/dwc2_hcd.c

4181

int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)

sys/dev/usb/dwc2/dwc2_hcd.c

4183

struct usbd_xfer *xfer = context;

sys/dev/usb/dwc2/dwc2_hcd.c

531

void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,

sys/dev/usb/dwc2/dwc2_hcd.c

534

struct usbd_xfer *xfer = context;

sys/dev/usb/dwc2/dwc2_hcd.h

824

void *context, gfp_t mem_flags,

sys/dev/usb/dwc2/dwc2_hcd.h

829

int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);

sys/dev/usb/dwc2/dwc2_hcdqueue.c

2159

dwc2_ttthink_to_ns(struct dwc2_hsotg *hsotg, void *context, int ttthink)

sys/dev/usb/dwc2/dwc2_hcdqueue.c

2161

struct usbd_xfer *xfer = context;

sys/dev/usb/if_umb.c

1795

if (memcmp(ci->context, umb_uuid_context_internet,

sys/dev/usb/if_umb.c

1796

sizeof (ci->context))) {

sys/dev/usb/if_umb.c

2862

memcpy(c->context, umb_uuid_context_internet, sizeof (c->context));

sys/dev/usb/mbim.h

514

uint8_t context[MBIM_UUID_LEN];

sys/dev/usb/mbim.h

533

uint8_t context[MBIM_UUID_LEN];

sys/lib/libsa/sha1.c

108

SHA1Init(SHA1_CTX *context)

sys/lib/libsa/sha1.c

111

context->count = 0;

sys/lib/libsa/sha1.c

112

context->state[0] = 0x67452301;

sys/lib/libsa/sha1.c

113

context->state[1] = 0xEFCDAB89;

sys/lib/libsa/sha1.c

114

context->state[2] = 0x98BADCFE;

sys/lib/libsa/sha1.c

115

context->state[3] = 0x10325476;

sys/lib/libsa/sha1.c

116

context->state[4] = 0xC3D2E1F0;

sys/lib/libsa/sha1.c

123

SHA1Update(SHA1_CTX *context, const unsigned char *data, unsigned int len)

sys/lib/libsa/sha1.c

128

j = (u_int32_t)((context->count >> 3) & 63);

sys/lib/libsa/sha1.c

129

context->count += (len << 3);

sys/lib/libsa/sha1.c

131

bcopy(data, &context->buffer[j], (i = 64 - j));

sys/lib/libsa/sha1.c

132

SHA1Transform(context->state, context->buffer);

sys/lib/libsa/sha1.c

134

SHA1Transform(context->state, &data[i]);

sys/lib/libsa/sha1.c

139

bcopy(&data[i], &context->buffer[j], len - i);

sys/lib/libsa/sha1.c

146

SHA1Final(unsigned char digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context)

sys/lib/libsa/sha1.c

152

finalcount[i] = (unsigned char)((context->count >>

sys/lib/libsa/sha1.c

155

SHA1Update(context, (unsigned char *)"\200", 1);

sys/lib/libsa/sha1.c

156

while ((context->count & 504) != 448) {

sys/lib/libsa/sha1.c

157

SHA1Update(context, (unsigned char *)"\0", 1);

sys/lib/libsa/sha1.c

159

SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */

sys/lib/libsa/sha1.c

163

digest[i] = (unsigned char)((context->state[i >> 2] >>

sys/lib/libsa/sha1.c

170

explicit_bzero(context->buffer, 64);

sys/lib/libsa/sha1.c

171

explicit_bzero(context->state, 20);

sys/lib/libsa/sha1.c

172

explicit_bzero(context->count, 8);

sys/lib/libsa/sha1.c

174

SHA1Transform(context->state, context->buffer);

sys/lib/libsa/sha1.h

21

void SHA1Init(SHA1_CTX * context);

sys/lib/libsa/sha1.h

23

void SHA1Update(SHA1_CTX *context, const unsigned char *data, unsigned int len);

sys/lib/libsa/sha1.h

24

void SHA1Final(unsigned char digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context);

sys/lib/libsa/sha2.c

306

SHA224Init(SHA2_CTX *context)

sys/lib/libsa/sha2.c

308

memcpy(context->state.st32, sha224_initial_hash_value,

sys/lib/libsa/sha2.c

310

memset(context->buffer, 0, sizeof(context->buffer));

sys/lib/libsa/sha2.c

311

context->bitcount[0] = 0;

sys/lib/libsa/sha2.c

319

SHA224Final(u_int8_t digest[SHA224_DIGEST_LENGTH], SHA2_CTX *context)

sys/lib/libsa/sha2.c

321

SHA224Pad(context);

sys/lib/libsa/sha2.c

328

BE_32_TO_8(digest + i * 4, context->state.st32[i]);

sys/lib/libsa/sha2.c

330

memcpy(digest, context->state.st32, SHA224_DIGEST_LENGTH);

sys/lib/libsa/sha2.c

332

explicit_bzero(context, sizeof(*context));

sys/lib/libsa/sha2.c

338

SHA256Init(SHA2_CTX *context)

sys/lib/libsa/sha2.c

340

memcpy(context->state.st32, sha256_initial_hash_value,

sys/lib/libsa/sha2.c

342

memset(context->buffer, 0, sizeof(context->buffer));

sys/lib/libsa/sha2.c

343

context->bitcount[0] = 0;

sys/lib/libsa/sha2.c

505

SHA256Update(SHA2_CTX *context, const u_int8_t *data, size_t len)

sys/lib/libsa/sha2.c

513

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

sys/lib/libsa/sha2.c

520

memcpy(&context->buffer[usedspace], data, freespace);

sys/lib/libsa/sha2.c

521

context->bitcount[0] += freespace << 3;

sys/lib/libsa/sha2.c

524

SHA256Transform(context->state.st32, context->buffer);

sys/lib/libsa/sha2.c

527

memcpy(&context->buffer[usedspace], data, len);

sys/lib/libsa/sha2.c

528

context->bitcount[0] += len << 3;

sys/lib/libsa/sha2.c

536

SHA256Transform(context->state.st32, data);

sys/lib/libsa/sha2.c

537

context->bitcount[0] += SHA256_BLOCK_LENGTH << 3;

sys/lib/libsa/sha2.c

543

memcpy(context->buffer, data, len);

sys/lib/libsa/sha2.c

544

context->bitcount[0] += len << 3;

sys/lib/libsa/sha2.c

551

SHA256Pad(SHA2_CTX *context)

sys/lib/libsa/sha2.c

555

usedspace = (context->bitcount[0] >> 3) % SHA256_BLOCK_LENGTH;

sys/lib/libsa/sha2.c

558

context->buffer[usedspace++] = 0x80;

sys/lib/libsa/sha2.c

562

memset(&context->buffer[usedspace], 0,

sys/lib/libsa/sha2.c

566

memset(&context->buffer[usedspace], 0,

sys/lib/libsa/sha2.c

570

SHA256Transform(context->state.st32, context->buffer);

sys/lib/libsa/sha2.c

573

memset(context->buffer, 0, SHA256_SHORT_BLOCK_LENGTH);

sys/lib/libsa/sha2.c

577

memset(context->buffer, 0, SHA256_SHORT_BLOCK_LENGTH);

sys/lib/libsa/sha2.c

580

*context->buffer = 0x80;

sys/lib/libsa/sha2.c

583

BE_64_TO_8(&context->buffer[SHA256_SHORT_BLOCK_LENGTH],

sys/lib/libsa/sha2.c

584

context->bitcount[0]);

sys/lib/libsa/sha2.c

587

SHA256Transform(context->state.st32, context->buffer);

sys/lib/libsa/sha2.c

594

SHA256Final(u_int8_t digest[SHA256_DIGEST_LENGTH], SHA2_CTX *context)

sys/lib/libsa/sha2.c

596

SHA256Pad(context);

sys/lib/libsa/sha2.c

603

BE_32_TO_8(digest + i * 4, context->state.st32[i]);

sys/lib/libsa/sha2.c

605

memcpy(digest, context->state.st32, SHA256_DIGEST_LENGTH);

sys/lib/libsa/sha2.c

607

explicit_bzero(context, sizeof(*context));

sys/lib/libsa/sha2.c

613

SHA512Init(SHA2_CTX *context)

sys/lib/libsa/sha2.c

615

memcpy(context->state.st64, sha512_initial_hash_value,

sys/lib/libsa/sha2.c

617

memset(context->buffer, 0, sizeof(context->buffer));

sys/lib/libsa/sha2.c

618

context->bitcount[0] = context->bitcount[1] = 0;

sys/lib/libsa/sha2.c

781

SHA512Update(SHA2_CTX *context, const u_int8_t *data, size_t len)

sys/lib/libsa/sha2.c

789

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

sys/lib/libsa/sha2.c

796

memcpy(&context->buffer[usedspace], data, freespace);

sys/lib/libsa/sha2.c

797

ADDINC128(context->bitcount, freespace << 3);

sys/lib/libsa/sha2.c

800

SHA512Transform(context->state.st64, context->buffer);

sys/lib/libsa/sha2.c

803

memcpy(&context->buffer[usedspace], data, len);

sys/lib/libsa/sha2.c

804

ADDINC128(context->bitcount, len << 3);

sys/lib/libsa/sha2.c

812

SHA512Transform(context->state.st64, data);

sys/lib/libsa/sha2.c

813

ADDINC128(context->bitcount, SHA512_BLOCK_LENGTH << 3);

sys/lib/libsa/sha2.c

819

memcpy(context->buffer, data, len);

sys/lib/libsa/sha2.c

820

ADDINC128(context->bitcount, len << 3);

sys/lib/libsa/sha2.c

827

SHA512Pad(SHA2_CTX *context)

sys/lib/libsa/sha2.c

831

usedspace = (context->bitcount[0] >> 3) % SHA512_BLOCK_LENGTH;

sys/lib/libsa/sha2.c

834

context->buffer[usedspace++] = 0x80;

sys/lib/libsa/sha2.c

838

memset(&context->buffer[usedspace], 0, SHA512_SHORT_BLOCK_LENGTH - usedspace);

sys/lib/libsa/sha2.c

841

memset(&context->buffer[usedspace], 0, SHA512_BLOCK_LENGTH - usedspace);

sys/lib/libsa/sha2.c

844

SHA512Transform(context->state.st64, context->buffer);

sys/lib/libsa/sha2.c

847

memset(context->buffer, 0, SHA512_BLOCK_LENGTH - 2);

sys/lib/libsa/sha2.c

851

memset(context->buffer, 0, SHA512_SHORT_BLOCK_LENGTH);

sys/lib/libsa/sha2.c

854

*context->buffer = 0x80;

sys/lib/libsa/sha2.c

857

BE_64_TO_8(&context->buffer[SHA512_SHORT_BLOCK_LENGTH],

sys/lib/libsa/sha2.c

858

context->bitcount[1]);

sys/lib/libsa/sha2.c

859

BE_64_TO_8(&context->buffer[SHA512_SHORT_BLOCK_LENGTH + 8],

sys/lib/libsa/sha2.c

860

context->bitcount[0]);

sys/lib/libsa/sha2.c

863

SHA512Transform(context->state.st64, context->buffer);

sys/lib/libsa/sha2.c

870

SHA512Final(u_int8_t digest[SHA512_DIGEST_LENGTH], SHA2_CTX *context)

sys/lib/libsa/sha2.c

872

SHA512Pad(context);

sys/lib/libsa/sha2.c

879

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

sys/lib/libsa/sha2.c

881

memcpy(digest, context->state.st64, SHA512_DIGEST_LENGTH);

sys/lib/libsa/sha2.c

883

explicit_bzero(context, sizeof(*context));

sys/lib/libsa/sha2.c

890

SHA384Init(SHA2_CTX *context)

sys/lib/libsa/sha2.c

892

memcpy(context->state.st64, sha384_initial_hash_value,

sys/lib/libsa/sha2.c

894

memset(context->buffer, 0, sizeof(context->buffer));

sys/lib/libsa/sha2.c

895

context->bitcount[0] = context->bitcount[1] = 0;

sys/lib/libsa/sha2.c

903

SHA384Final(u_int8_t digest[SHA384_DIGEST_LENGTH], SHA2_CTX *context)

sys/lib/libsa/sha2.c

905

SHA384Pad(context);

sys/lib/libsa/sha2.c

912

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

sys/lib/libsa/sha2.c

914

memcpy(digest, context->state.st64, SHA384_DIGEST_LENGTH);

sys/lib/libsa/sha2.c

917

explicit_bzero(context, sizeof(*context));

sys/lib/libsa/sha2.c

922

SHA512_256Init(SHA2_CTX *context)

sys/lib/libsa/sha2.c

924

memcpy(context->state.st64, sha512_256_initial_hash_value,

sys/lib/libsa/sha2.c

926

memset(context->buffer, 0, sizeof(context->buffer));

sys/lib/libsa/sha2.c

927

context->bitcount[0] = context->bitcount[1] = 0;

sys/lib/libsa/sha2.c

935

SHA512_256Final(u_int8_t digest[SHA512_256_DIGEST_LENGTH], SHA2_CTX *context)

sys/lib/libsa/sha2.c

937

SHA512_256Pad(context);

sys/lib/libsa/sha2.c

944

BE_64_TO_8(digest + i * 8, context->state.st64[i]);

sys/lib/libsa/sha2.c

946

memcpy(digest, context->state.st64, SHA512_256_DIGEST_LENGTH);

sys/lib/libsa/sha2.c

949

explicit_bzero(context, sizeof(*context));

sys/net80211/ieee80211_crypto.c

327

size_t label_len, const u_int8_t *context, size_t context_len,

sys/net80211/ieee80211_crypto.c

337

HMAC_SHA1_Update(&ctx, context, context_len);

sys/net80211/ieee80211_crypto.c

356

size_t label_len, const u_int8_t *context, size_t context_len,

sys/net80211/ieee80211_crypto.c

369

HMAC_SHA256_Update(&ctx, context, context_len);

usr.bin/dig/lib/isc/sha1.c

42

isc_sha1_init(isc_sha1_t *context)

usr.bin/dig/lib/isc/sha1.c

44

INSIST(context != NULL);

usr.bin/dig/lib/isc/sha1.c

46

context->ctx = EVP_MD_CTX_new();

usr.bin/dig/lib/isc/sha1.c

47

RUNTIME_CHECK(context->ctx != NULL);

usr.bin/dig/lib/isc/sha1.c

48

if (EVP_DigestInit(context->ctx, EVP_sha1()) != 1) {

usr.bin/dig/lib/isc/sha1.c

54

isc_sha1_update(isc_sha1_t *context, const unsigned char *data,

usr.bin/dig/lib/isc/sha1.c

57

INSIST(context != 0);

usr.bin/dig/lib/isc/sha1.c

58

INSIST(context->ctx != 0);

usr.bin/dig/lib/isc/sha1.c

61

RUNTIME_CHECK(EVP_DigestUpdate(context->ctx,

usr.bin/dig/lib/isc/sha1.c

67

isc_sha1_final(isc_sha1_t *context, unsigned char *digest) {

usr.bin/dig/lib/isc/sha1.c

69

INSIST(context != 0);

usr.bin/dig/lib/isc/sha1.c

70

INSIST(context->ctx != 0);

usr.bin/dig/lib/isc/sha1.c

72

RUNTIME_CHECK(EVP_DigestFinal(context->ctx, digest, NULL) == 1);

usr.bin/dig/lib/isc/sha1.c

73

EVP_MD_CTX_free(context->ctx);

usr.bin/dig/lib/isc/sha1.c

74

context->ctx = NULL;

usr.bin/dig/lib/isc/sha2.c

100

context->ctx = NULL;

usr.bin/dig/lib/isc/sha2.c

104

isc_sha256_init(isc_sha256_t *context) {

usr.bin/dig/lib/isc/sha2.c

105

if (context == (isc_sha256_t *)0) {

usr.bin/dig/lib/isc/sha2.c

108

context->ctx = EVP_MD_CTX_new();

usr.bin/dig/lib/isc/sha2.c

109

RUNTIME_CHECK(context->ctx != NULL);

usr.bin/dig/lib/isc/sha2.c

110

if (EVP_DigestInit(context->ctx, EVP_sha256()) != 1) {

usr.bin/dig/lib/isc/sha2.c

116

isc_sha256_update(isc_sha256_t *context, const uint8_t *data, size_t len) {

usr.bin/dig/lib/isc/sha2.c

123

REQUIRE(context != (isc_sha256_t *)0);

usr.bin/dig/lib/isc/sha2.c

124

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

127

RUNTIME_CHECK(EVP_DigestUpdate(context->ctx,

usr.bin/dig/lib/isc/sha2.c

132

isc_sha256_final(uint8_t digest[ISC_SHA256_DIGESTLENGTH], isc_sha256_t *context) {

usr.bin/dig/lib/isc/sha2.c

134

REQUIRE(context != (isc_sha256_t *)0);

usr.bin/dig/lib/isc/sha2.c

135

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

139

RUNTIME_CHECK(EVP_DigestFinal(context->ctx,

usr.bin/dig/lib/isc/sha2.c

141

EVP_MD_CTX_free(context->ctx);

usr.bin/dig/lib/isc/sha2.c

142

context->ctx = NULL;

usr.bin/dig/lib/isc/sha2.c

146

isc_sha512_init(isc_sha512_t *context) {

usr.bin/dig/lib/isc/sha2.c

147

if (context == (isc_sha512_t *)0) {

usr.bin/dig/lib/isc/sha2.c

150

context->ctx = EVP_MD_CTX_new();

usr.bin/dig/lib/isc/sha2.c

151

RUNTIME_CHECK(context->ctx != NULL);

usr.bin/dig/lib/isc/sha2.c

152

if (EVP_DigestInit(context->ctx, EVP_sha512()) != 1) {

usr.bin/dig/lib/isc/sha2.c

157

void isc_sha512_update(isc_sha512_t *context, const uint8_t *data, size_t len) {

usr.bin/dig/lib/isc/sha2.c

164

REQUIRE(context != (isc_sha512_t *)0);

usr.bin/dig/lib/isc/sha2.c

165

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

168

RUNTIME_CHECK(EVP_DigestUpdate(context->ctx,

usr.bin/dig/lib/isc/sha2.c

172

void isc_sha512_final(uint8_t digest[ISC_SHA512_DIGESTLENGTH], isc_sha512_t *context) {

usr.bin/dig/lib/isc/sha2.c

174

REQUIRE(context != (isc_sha512_t *)0);

usr.bin/dig/lib/isc/sha2.c

175

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

179

RUNTIME_CHECK(EVP_DigestFinal(context->ctx,

usr.bin/dig/lib/isc/sha2.c

181

EVP_MD_CTX_free(context->ctx);

usr.bin/dig/lib/isc/sha2.c

182

context->ctx = NULL;

usr.bin/dig/lib/isc/sha2.c

186

isc_sha384_init(isc_sha384_t *context) {

usr.bin/dig/lib/isc/sha2.c

187

if (context == (isc_sha384_t *)0) {

usr.bin/dig/lib/isc/sha2.c

190

context->ctx = EVP_MD_CTX_new();

usr.bin/dig/lib/isc/sha2.c

191

RUNTIME_CHECK(context->ctx != NULL);

usr.bin/dig/lib/isc/sha2.c

192

if (EVP_DigestInit(context->ctx, EVP_sha384()) != 1) {

usr.bin/dig/lib/isc/sha2.c

198

isc_sha384_update(isc_sha384_t *context, const uint8_t* data, size_t len) {

usr.bin/dig/lib/isc/sha2.c

205

REQUIRE(context != (isc_sha512_t *)0);

usr.bin/dig/lib/isc/sha2.c

206

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

209

RUNTIME_CHECK(EVP_DigestUpdate(context->ctx,

usr.bin/dig/lib/isc/sha2.c

214

isc_sha384_final(uint8_t digest[ISC_SHA384_DIGESTLENGTH], isc_sha384_t *context) {

usr.bin/dig/lib/isc/sha2.c

216

REQUIRE(context != (isc_sha384_t *)0);

usr.bin/dig/lib/isc/sha2.c

217

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

221

RUNTIME_CHECK(EVP_DigestFinal(context->ctx,

usr.bin/dig/lib/isc/sha2.c

223

EVP_MD_CTX_free(context->ctx);

usr.bin/dig/lib/isc/sha2.c

224

context->ctx = NULL;

usr.bin/dig/lib/isc/sha2.c

62

isc_sha224_init(isc_sha224_t *context) {

usr.bin/dig/lib/isc/sha2.c

63

if (context == (isc_sha224_t *)0) {

usr.bin/dig/lib/isc/sha2.c

66

context->ctx = EVP_MD_CTX_new();

usr.bin/dig/lib/isc/sha2.c

67

RUNTIME_CHECK(context->ctx != NULL);

usr.bin/dig/lib/isc/sha2.c

68

if (EVP_DigestInit(context->ctx, EVP_sha224()) != 1) {

usr.bin/dig/lib/isc/sha2.c

74

isc_sha224_update(isc_sha224_t *context, const uint8_t* data, size_t len) {

usr.bin/dig/lib/isc/sha2.c

81

REQUIRE(context != (isc_sha224_t *)0);

usr.bin/dig/lib/isc/sha2.c

82

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

85

RUNTIME_CHECK(EVP_DigestUpdate(context->ctx,

usr.bin/dig/lib/isc/sha2.c

90

isc_sha224_final(uint8_t digest[ISC_SHA224_DIGESTLENGTH], isc_sha224_t *context) {

usr.bin/dig/lib/isc/sha2.c

92

REQUIRE(context != (isc_sha224_t *)0);

usr.bin/dig/lib/isc/sha2.c

93

REQUIRE(context->ctx != (EVP_MD_CTX *)0);

usr.bin/dig/lib/isc/sha2.c

97

RUNTIME_CHECK(EVP_DigestFinal(context->ctx,

usr.bin/dig/lib/isc/sha2.c

99

EVP_MD_CTX_free(context->ctx);

usr.bin/openssl/apps.h

377

int (*cb)(int s, unsigned char *context),

usr.bin/openssl/apps.h

378

unsigned char *context, int naccept);

usr.bin/openssl/s_server.c

1408

&accept_socket, www_body, cfg.context,

usr.bin/openssl/s_server.c

1412

&accept_socket, sv_body, cfg.context,

usr.bin/openssl/s_server.c

1471

sv_body(int s, unsigned char *context)

usr.bin/openssl/s_server.c

1504

if (context)

usr.bin/openssl/s_server.c

1505

SSL_set_session_id_context(con, context,

usr.bin/openssl/s_server.c

1506

strlen((char *) context));

usr.bin/openssl/s_server.c

180

static int sv_body(int s, unsigned char *context);

usr.bin/openssl/s_server.c

186

static int www_body(int s, unsigned char *context);

usr.bin/openssl/s_server.c

1895

www_body(int s, unsigned char *context)

usr.bin/openssl/s_server.c

1929

if (context)

usr.bin/openssl/s_server.c

1930

SSL_set_session_id_context(con, context,

usr.bin/openssl/s_server.c

1931

strlen((char *) context));

usr.bin/openssl/s_server.c

246

unsigned char *context;

usr.bin/openssl/s_server.c

299

cfg.context = (unsigned char *) arg;

usr.bin/openssl/s_socket.c

132

int (*cb)(int s, unsigned char *context),

usr.bin/openssl/s_socket.c

133

unsigned char *context, int naccept)

usr.bin/openssl/s_socket.c

155

i = cb(sock, context);

usr.bin/openssl/sess_id.c

181

if (cfg.context) {

usr.bin/openssl/sess_id.c

182

size_t ctx_len = strlen(cfg.context);

usr.bin/openssl/sess_id.c

188

(unsigned char *)cfg.context, ctx_len);

usr.bin/openssl/sess_id.c

73

char *context;

usr.bin/openssl/sess_id.c

94

.opt.arg = &cfg.context,

usr.bin/patch/pch.c

1016

if (ch != ' ' && context > 0) {

usr.bin/patch/pch.c

1017

if (context < p_context)

usr.bin/patch/pch.c

1018

p_context = context;

usr.bin/patch/pch.c

1019

context = -1000;

usr.bin/patch/pch.c

505

int context = 0;

usr.bin/patch/pch.c

579

context = 0;

usr.bin/patch/pch.c

706

if (context >= 0) {

usr.bin/patch/pch.c

707

if (context < p_context)

usr.bin/patch/pch.c

708

p_context = context;

usr.bin/patch/pch.c

709

context = -1000;

usr.bin/patch/pch.c

740

context++;

usr.bin/patch/pch.c

752

context++;

usr.bin/patch/pch.c

921

context = 0;

usr.bin/patch/pch.c

976

context++;

usr.bin/ssh/auth-krb5.c

56

krb5_init(void *context)

usr.bin/ssh/auth-krb5.c

58

Authctxt *authctxt = (Authctxt *)context;

usr.bin/ssh/gss-genr.c

163

(*ctx)->context = GSS_C_NO_CONTEXT;

usr.bin/ssh/gss-genr.c

179

if ((*ctx)->context != GSS_C_NO_CONTEXT)

usr.bin/ssh/gss-genr.c

180

gss_delete_sec_context(&ms, &(*ctx)->context, GSS_C_NO_BUFFER);

usr.bin/ssh/gss-genr.c

217

GSS_C_NO_CREDENTIAL, &ctx->context, ctx->name, ctx->oid,

usr.bin/ssh/gss-genr.c

249

if ((ctx->major = gss_get_mic(&ctx->minor, ctx->context,

usr.bin/ssh/gss-genr.c

258

const char *context, const struct sshbuf *session_id)

usr.bin/ssh/gss-genr.c

267

(r = sshbuf_put_cstring(b, context)) != 0)

usr.bin/ssh/gss-genr.c

290

if ((*ctx)->context != GSS_C_NO_CONTEXT)

usr.bin/ssh/gss-genr.c

291

gss_delete_sec_context(&minor, &(*ctx)->context,

usr.bin/ssh/gss-serv.c

183

&ctx->context, ctx->creds, recv_tok,

usr.bin/ssh/gss-serv.c

394

ctx->major = gss_verify_mic(&ctx->minor, ctx->context,

usr.bin/ssh/ssh-agent.c

317

dump_dest_constraints(const char *context,

usr.bin/ssh/ssh-agent.c

323

debug_f("%s: %zu constraints", context, ndcs);

usr.bin/ssh/ssh-agent.c

330

debug_f("done for %s", context);

usr.bin/ssh/ssh-gss.h

71

gss_ctx_id_t context; /* both */

usr.bin/ssh/ssh-pkcs11.c

1385

note_key(struct pkcs11_provider *p, CK_ULONG slotidx, const char *context,

usr.bin/ssh/ssh-pkcs11.c

1395

debug2("%s: provider %s slot %lu: %s %s", context, p->name,

usr.sbin/config/files.c

225

checkaux(const char *name, void *context)

usr.sbin/config/files.c

227

struct files *fi = context;

usr.sbin/config/files.c

341

fixcount(const char *name, void *context)

usr.sbin/config/files.c

343

struct nvlist ***p = context;

usr.sbin/config/files.c

362

fixfsel(const char *name, void *context)

usr.sbin/config/files.c

364

struct nvlist ***p = context;

usr.sbin/config/files.c

379

fixsel(const char *name, void *context)

usr.sbin/config/files.c

394

expr_eval(struct nvlist *expr, int (*fn)(const char *, void *), void *context)

usr.sbin/config/files.c

401

return ((*fn)(expr->nv_name, context));

usr.sbin/config/files.c

404

return (!expr_eval(expr->nv_next, fn, context));

usr.sbin/config/files.c

407

lhs = expr_eval(expr->nv_ptr, fn, context);

usr.sbin/config/files.c

408

rhs = expr_eval(expr->nv_next, fn, context);

usr.sbin/config/files.c

412

lhs = expr_eval(expr->nv_ptr, fn, context);

usr.sbin/config/files.c

413

rhs = expr_eval(expr->nv_next, fn, context);

usr.sbin/ldapd/ldapd.h

469

int context, const char *fmt, ...);

usr.sbin/ldapd/logmsg.c

215

switch (context) {

usr.sbin/ldapd/logmsg.c

327

ldap_debug_elements(root->be_sub, context, NULL);

usr.sbin/ldapd/logmsg.c

331

ldap_debug_elements(root->be_next, context, NULL);

usr.sbin/ldapd/logmsg.c

89

ldap_debug_elements(struct ber_element *root, int context, const char *fmt, ...)

usr.sbin/npppd/npppd/chap.c

816

chap_radius_response(void *context, RADIUS_PACKET *pkt, int flags,

usr.sbin/npppd/npppd/chap.c

826

CHAP_ASSERT(context != NULL);

usr.sbin/npppd/npppd/chap.c

830

_this = context;

usr.sbin/npppd/npppd/npppd_radius.c

174

npppd_ppp_radius_acct_reqcb(void *context, RADIUS_PACKET *pkt, int flags,

usr.sbin/npppd/npppd/npppd_radius.c

179

ppp_id = (uintptr_t)context;

usr.sbin/npppd/npppd/npppd_radius.c

419

radius_acct_on_cb(void *context, RADIUS_PACKET *pkt, int flags,

usr.sbin/npppd/npppd/pap.c

470

pap_radius_response(void *context, RADIUS_PACKET *pkt, int flags,

usr.sbin/npppd/npppd/pap.c

478

_this = context;

usr.sbin/npppd/npppd/ppp.c

621

ppp_idle_timeout(int fd, short evtype, void *context)

usr.sbin/npppd/npppd/ppp.c

625

_this = context;

usr.sbin/npppd/npppd/radius_req.c

266

radius_prepare(radius_req_setting *setting, void *context,

usr.sbin/npppd/npppd/radius_req.c

280

lap->context = context;

usr.sbin/npppd/npppd/radius_req.c

410

radius_request_io_event(int fd, short evmask, void *context)

usr.sbin/npppd/npppd/radius_req.c

418

RADIUS_REQ_ASSERT(context != NULL);

usr.sbin/npppd/npppd/radius_req.c

420

lap = context;

usr.sbin/npppd/npppd/radius_req.c

504

lap->response_fn(lap->context, pkt, flags, ctx);

usr.sbin/npppd/npppd/radius_req.c

64

void *context;

usr.sbin/npppd/npppd/radius_req.h

67

typedef void (radius_response)(void *context, RADIUS_PACKET *pkt, int flags, RADIUS_REQUEST_CTX reqctx);

usr.sbin/nsd/tsig-openssl.c

174

HMAC_CTX *context = (HMAC_CTX *) data;

usr.sbin/nsd/tsig-openssl.c

176

HMAC_CTX_free(context);

usr.sbin/nsd/tsig-openssl.c

178

HMAC_CTX_cleanup(context);

usr.sbin/nsd/tsig-openssl.c

179

free(context);

usr.sbin/nsd/tsig-openssl.c

193

HMAC_CTX *context = HMAC_CTX_new();

usr.sbin/nsd/tsig-openssl.c

195

HMAC_CTX *context = (HMAC_CTX *) malloc(sizeof(HMAC_CTX));

usr.sbin/nsd/tsig-openssl.c

197

region_add_cleanup(region, cleanup_context, context);

usr.sbin/nsd/tsig-openssl.c

199

HMAC_CTX_reset(context);

usr.sbin/nsd/tsig-openssl.c

201

HMAC_CTX_init(context);

usr.sbin/nsd/tsig-openssl.c

204

struct tsig_openssl_context* context = region_alloc(region,

usr.sbin/nsd/tsig-openssl.c

205

sizeof(*context));

usr.sbin/nsd/tsig-openssl.c

206

memset(context, 0, sizeof(*context));

usr.sbin/nsd/tsig-openssl.c

207

region_add_cleanup(region, cleanup_context, context);

usr.sbin/nsd/tsig-openssl.c

209

return context;

usr.sbin/nsd/tsig-openssl.c

213

init_context(void *context,

usr.sbin/nsd/tsig-openssl.c

218

HMAC_CTX *ctx = (HMAC_CTX *) context;

usr.sbin/nsd/tsig-openssl.c

22

static void init_context(void *context,

usr.sbin/nsd/tsig-openssl.c

225

struct tsig_openssl_context* c = (struct tsig_openssl_context*)context;

usr.sbin/nsd/tsig-openssl.c

25

static void update(void *context, const void *data, size_t size);

usr.sbin/nsd/tsig-openssl.c

259

update(void *context, const void *data, size_t size)

usr.sbin/nsd/tsig-openssl.c

26

static void final(void *context, uint8_t *digest, size_t *size);

usr.sbin/nsd/tsig-openssl.c

262

HMAC_CTX *ctx = (HMAC_CTX *) context;

usr.sbin/nsd/tsig-openssl.c

265

struct tsig_openssl_context* c = (struct tsig_openssl_context*)context;

usr.sbin/nsd/tsig-openssl.c

273

final(void *context, uint8_t *digest, size_t *size)

usr.sbin/nsd/tsig-openssl.c

276

HMAC_CTX *ctx = (HMAC_CTX *) context;

usr.sbin/nsd/tsig-openssl.c

281

struct tsig_openssl_context* c = (struct tsig_openssl_context*)context;

usr.sbin/nsd/tsig.c

108

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

111

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

114

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

117

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

121

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

124

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

127

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

131

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

134

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

137

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

334

tsig->context = NULL;

usr.sbin/nsd/tsig.c

459

if (!tsig->context) {

usr.sbin/nsd/tsig.c

461

tsig->context = tsig->algorithm->hmac_create_context(

usr.sbin/nsd/tsig.c

467

tsig->algorithm->hmac_init_context(tsig->context,

usr.sbin/nsd/tsig.c

473

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

476

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

491

tsig->algorithm->hmac_update(tsig->context,

usr.sbin/nsd/tsig.c

495

tsig->context,

usr.sbin/nsd/tsig.c

515

tsig->algorithm->hmac_final(tsig->context,

usr.sbin/nsd/tsig.c

528

tsig->algorithm->hmac_final(tsig->context,

usr.sbin/nsd/tsig.h

111

void *context;

usr.sbin/nsd/tsig.h

79

void (*hmac_init_context)(void *context,

usr.sbin/nsd/tsig.h

86

void (*hmac_update)(void *context, const void *data, size_t size);

usr.sbin/nsd/tsig.h

92

void (*hmac_final)(void *context, uint8_t *digest, size_t *size);

usr.sbin/ntpd/client.c

414

MD5_CTX context;

usr.sbin/ntpd/client.c

417

MD5Init(&context);

usr.sbin/ntpd/client.c

418

MD5Update(&context, ((struct sockaddr_in6 *)&p->addr->ss)->

usr.sbin/ntpd/client.c

420

MD5Final(digest, &context);

usr.sbin/relayd/parse.y

186

%type <v.string> context hostname interface table value path

usr.sbin/relayd/parse.y

424

| AGENTX context path {

usr.sbin/relayd/parse.y

460

context : /* nothing */ { $$ = NULL; }

usr.sbin/relayd/parse.y

889

MD5_CTX context;

usr.sbin/relayd/parse.y

891

MD5Init(&context);

usr.sbin/relayd/parse.y

892

MD5Update(&context, (unsigned char *)$1,

usr.sbin/relayd/parse.y

895

&context);

usr.sbin/snmpd/application_agentx.c

720

struct ax_ostring *context, string;

usr.sbin/snmpd/application_agentx.c

745

if ((context = appl_agentx_string2ostring(ctx, &string)) == NULL) {

usr.sbin/snmpd/application_agentx.c

757

requestid, context, srl, nsr) == -1)

usr.sbin/snmpd/application_agentx.c

762

if (context != NULL)

usr.sbin/snmpd/application_agentx.c

763

free(context->aos_string);

usr.sbin/snmpd/application_agentx.c

771

struct ax_ostring *context, string;

usr.sbin/snmpd/application_agentx.c

798

if ((context = appl_agentx_string2ostring(ctx, &string)) == NULL) {

usr.sbin/snmpd/application_agentx.c

810

requestid, context, srl, nsr) == -1)

usr.sbin/snmpd/application_agentx.c

815

if (context != NULL)

usr.sbin/snmpd/application_agentx.c

816

free(context->aos_string);

usr.sbin/snmpd/ax.c

1128

struct ax_ostring *context)

usr.sbin/snmpd/ax.c

1139

if (context != NULL)

usr.sbin/snmpd/ax.c

1151

if (context != NULL) {

usr.sbin/snmpd/ax.c

1152

if (ax_pdu_add_str(ax, context) == -1)

usr.sbin/snmpd/ax.c

540

uint32_t packetid, struct ax_ostring *context, struct ax_searchrange *srl,

usr.sbin/snmpd/ax.c

546

packetid, context) == -1)

usr.sbin/snmpd/ax.c

559

uint32_t packetid, struct ax_ostring *context, struct ax_searchrange *srl,

usr.sbin/snmpd/ax.c

565

packetid, context) == -1)

usr.sbin/snmpd/ax.c

578

struct ax_ostring *context, struct ax_varbind *vblist, size_t nvb)

usr.sbin/snmpd/ax.c

586

sessionid, 0, 0, context) == -1)

usr.sbin/snmpd/ax.c

597

struct ax_ostring *context, struct ax_varbind *vblist, size_t nvb)

usr.sbin/snmpd/ax.c

600

sessionid, 0, 0, context) == -1)

usr.sbin/snmpd/ax.c

611

struct ax_ostring *context, struct ax_oid *id,

usr.sbin/snmpd/ax.c

615

sessionid, 0, 0, context) == -1)

usr.sbin/snmpd/ax.c

627

struct ax_ostring *context, struct ax_oid *id)

usr.sbin/snmpd/ax.c

630

sessionid, 0, 0, context) == -1)

usr.sbin/snmpd/ax.c

641

struct ax_ostring *context, uint8_t timeout, uint8_t priority,

usr.sbin/snmpd/ax.c

650

sessionid, 0, 0, context) == -1)

usr.sbin/snmpd/ax.c

671

struct ax_ostring *context, uint8_t priority, uint8_t range_subid,

usr.sbin/snmpd/ax.c

675

sessionid, 0, 0, context) == -1)

usr.sbin/vmd/vm_agentx.c

268

char *context = env->ax_context[0] == '\0' ? NULL : env->ax_context;

usr.sbin/vmd/vm_agentx.c

317

if ((ctx = agentx_context(sess, context)) == NULL)