include/time.h

114

clock_t clock(void);

lib/libc/hidden/time.h

29

PROTO_STD_DEPRECATED(clock);

lib/libc/include/thread_private.h

314

clockid_t clock;

lib/libc/include/thread_private.h

341

clockid_t clock;

lib/libc/softfloat/timesoftfloat.c

1002

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1060

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1069

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1071

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1078

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1092

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

110

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1101

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1103

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1110

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1124

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1133

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1135

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1142

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1156

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1165

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1167

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

117

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1174

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

119

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1190

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1199

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1201

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1208

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1224

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1233

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1235

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

124

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1242

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1257

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1270

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1273

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1284

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1299

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1312

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1315

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1326

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

137

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1378

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1387

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1389

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1396

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

144

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1455

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

146

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1464

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1466

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1473

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1487

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1496

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1498

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1505

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

151

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1519

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1528

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1530

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1537

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1551

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1560

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1562

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1569

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1585

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1594

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1596

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1603

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1619

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1628

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1630

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1637

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1652

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

166

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1665

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1668

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1679

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

1694

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1707

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1710

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1721

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

173

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

175

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1772

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1781

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

1783

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

1790

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

180

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

197

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

204

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

206

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

211

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

265

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

272

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

274

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

279

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

292

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

299

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

301

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

306

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

321

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

328

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

330

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

335

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

352

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

359

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

361

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

366

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

396

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

403

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

405

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

410

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

423

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

430

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

432

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

437

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

450

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

457

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

459

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

464

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

479

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

486

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

488

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

493

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

510

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

517

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

519

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

524

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

539

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

546

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

548

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

553

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

567

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

577

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

580

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

588

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

602

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

612

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

615

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

623

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

647

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

654

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

656

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

661

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

713

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

720

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

722

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

727

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

740

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

747

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

749

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

754

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

767

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

774

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

776

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

781

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

796

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

803

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

805

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

810

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

827

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

834

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

836

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

841

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

856

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

863

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

865

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

870

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

884

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

894

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

897

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

905

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

919

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

929

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

932

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

940

endClock = clock();

lib/libc/softfloat/timesoftfloat.c

988

startClock = clock();

lib/libc/softfloat/timesoftfloat.c

995

} while ( clock() - startClock < CLOCKS_PER_SEC );

lib/libc/softfloat/timesoftfloat.c

997

startClock = clock();

lib/libc/thread/rthread_cond.c

106

error = _twait(&cond->seq, seq, clock, abs);

lib/libc/thread/rthread_cond.c

40

cond->clock = CLOCK_REALTIME;

lib/libc/thread/rthread_cond.c

42

cond->clock = (*attr)->ca_clock;

lib/libc/thread/rthread_cond.c

78

clockid_t clock = cond->clock;

lib/libc/thread/rthread_sync.c

256

cond->clock = CLOCK_REALTIME;

lib/libc/thread/rthread_sync.c

258

cond->clock = (*attr)->ca_clock;

lib/libc/thread/rthread_sync.c

361

error = __thrsleep(self, cond->clock, abstime,

lib/libexpat/tests/benchmark/benchmark.c

141

tstart = clock();

lib/libexpat/tests/benchmark/benchmark.c

162

tend = clock();

lib/libfido2/src/tpm.c

327

expected.clock = actual->clock;

lib/libfido2/src/tpm.c

328

expected.clock.safe = 1;

lib/libfido2/src/tpm.c

78

tpm_clock_info_t clock;

regress/lib/libssl/ssl/ssltest.c

852

clock_t c_clock = clock();

regress/lib/libssl/ssl/ssltest.c

917

*c_time += (clock() - c_clock);

regress/lib/libssl/ssl/ssltest.c

925

clock_t s_clock = clock();

regress/lib/libssl/ssl/ssltest.c

979

*s_time += (clock() - s_clock);

sbin/unwind/libunbound/sldns/parseutil.c

147

sldns_gmtime64_r(int64_t clock, struct tm *result)

sbin/unwind/libunbound/sldns/parseutil.c

150

result->tm_sec = (int) LDNS_MOD(clock, 60);

sbin/unwind/libunbound/sldns/parseutil.c

151

clock = LDNS_DIV(clock, 60);

sbin/unwind/libunbound/sldns/parseutil.c

152

result->tm_min = (int) LDNS_MOD(clock, 60);

sbin/unwind/libunbound/sldns/parseutil.c

153

clock = LDNS_DIV(clock, 60);

sbin/unwind/libunbound/sldns/parseutil.c

154

result->tm_hour = (int) LDNS_MOD(clock, 24);

sbin/unwind/libunbound/sldns/parseutil.c

155

clock = LDNS_DIV(clock, 24);

sbin/unwind/libunbound/sldns/parseutil.c

157

sldns_year_and_yday_from_days_since_epoch(clock, result);

sys/arch/arm/cortex/agtimer.c

249

u_int32_t clock, oclock, delta, delaycnt;

sys/arch/arm/cortex/agtimer.c

270

clock = agtimer_readcnt64();

sys/arch/arm/cortex/agtimer.c

271

delta = clock - oclock;

sys/arch/arm/cortex/amptimer.c

310

u_int32_t clock, oclock, delta, delaycnt;

sys/arch/arm/cortex/amptimer.c

331

clock = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/arch/arm/cortex/amptimer.c

333

delta = clock - oclock;

sys/arch/armv7/omap/dmtimer.c

286

u_int32_t clock, oclock, delta, delaycnt;

sys/arch/armv7/omap/dmtimer.c

314

clock = bus_space_read_4(sc->sc_iot, sc->sc_ioh[1], DM_TCRR);

sys/arch/armv7/omap/dmtimer.c

315

delta = clock - oclock;

sys/arch/armv7/omap/gptimer.c

295

u_int32_t clock, oclock, delta, delaycnt;

sys/arch/armv7/omap/gptimer.c

323

clock = bus_space_read_4(gptimer_iot, gptimer_ioh1, GP_TCRR);

sys/arch/armv7/omap/gptimer.c

324

delta = clock - oclock;

sys/arch/armv7/omap/prcm.c

207

prcm_setclock(int clock, int speed)

sys/arch/armv7/omap/prcm.c

214

sc->sc_setclock(sc, clock, speed);

sys/arch/armv7/omap/prcm.c

218

prcm_am335x_setclock(struct prcm_softc *sc, int clock, int speed)

sys/arch/armv7/omap/prcm.c

223

if (clock == 1) {

sys/arch/armv7/omap/prcm.c

231

} else if (clock == 2) {

sys/arch/armv7/omap/prcm.c

239

} else if (clock == 3) { /* DISP M1 */

sys/arch/armv7/omap/prcm.c

257

} else if (clock == 4) { /* DISP N */

sys/arch/armv7/omap/prcm.c

275

} else if (clock == 5) { /* DISP M2 */

sys/arch/armv7/omap/prcm.c

284

prcm_v3_setclock(struct prcm_softc *sc, int clock, int speed)

sys/arch/armv7/omap/prcm.c

288

if (clock == 1) {

sys/arch/armv7/omap/prcm.c

293

} else if (clock >= 2 && clock <= 9) {

sys/arch/armv7/omap/prcm.c

294

int shift = (clock-2);

sys/arch/armv7/omap/prcm.c

300

panic("%s: invalid clock %d", __func__, clock);

sys/arch/armv7/omap/prcm.c

86

int clock, int speed);

sys/arch/armv7/omap/prcmvar.h

18

void prcm_setclock(int clock, int speed);

sys/arch/armv7/xilinx/zqclock.c

141

const struct zqclock_clock *clock;

sys/arch/armv7/xilinx/zqclock.c

146

clock = &zqclock_clocks[idx];

sys/arch/armv7/xilinx/zqclock.c

147

if (clock->clk_ctl_reg == 0)

sys/arch/armv7/xilinx/zqclock.c

150

return clock;

sys/arch/armv7/xilinx/zqclock.c

178

const struct zqclock_clock *clock;

sys/arch/armv7/xilinx/zqclock.c

183

clock = zqclock_get_clock(idx);

sys/arch/armv7/xilinx/zqclock.c

184

if (clock == NULL)

sys/arch/armv7/xilinx/zqclock.c

189

ctl = zynq_slcr_read(sc->sc_rm, clock->clk_ctl_reg);

sys/arch/armv7/xilinx/zqclock.c

192

if (clock->clk_has_div1)

sys/arch/armv7/xilinx/zqclock.c

211

const struct zqclock_clock *clock;

sys/arch/armv7/xilinx/zqclock.c

221

clock = zqclock_get_clock(idx);

sys/arch/armv7/xilinx/zqclock.c

222

if (clock == NULL)

sys/arch/armv7/xilinx/zqclock.c

231

if (clock->clk_has_div1)

sys/arch/armv7/xilinx/zqclock.c

275

ctl = zynq_slcr_read(sc->sc_rm, clock->clk_ctl_reg);

sys/arch/armv7/xilinx/zqclock.c

281

if (clock->clk_has_div1) {

sys/arch/armv7/xilinx/zqclock.c

286

zynq_slcr_write(sc->sc_rm, clock->clk_ctl_reg, ctl);

sys/arch/armv7/xilinx/zqclock.c

297

const struct zqclock_clock *clock;

sys/arch/armv7/xilinx/zqclock.c

302

clock = zqclock_get_clock(idx);

sys/arch/armv7/xilinx/zqclock.c

303

if (clock == NULL)

sys/arch/armv7/xilinx/zqclock.c

308

ctl = zynq_slcr_read(sc->sc_rm, clock->clk_ctl_reg);

sys/arch/armv7/xilinx/zqclock.c

310

ctl |= SLCR_CLK_CTRL_CLKACT(clock->clk_index);

sys/arch/armv7/xilinx/zqclock.c

312

ctl &= ~SLCR_CLK_CTRL_CLKACT(clock->clk_index);

sys/arch/armv7/xilinx/zqclock.c

313

zynq_slcr_write(sc->sc_rm, clock->clk_ctl_reg, ctl);

sys/arch/hppa/dev/mongoose.c

459

(sc->sc_regs->clock? 33 : 25));

sys/arch/hppa/dev/mongoosereg.h

35

u_int8_t clock;

sys/arch/loongson/loongson/loongson2_machdep.c

280

*freq = ((bootcpu_hwinfo.clock / 8) * step) / 1000000;

sys/arch/loongson/loongson/machdep.c

362

bootcpu_hwinfo.clock = cpuenv->speed;

sys/arch/loongson/loongson/machdep.c

429

bootcpu_hwinfo.clock = cpuspeed;

sys/arch/mips64/include/cpu.h

119

uint32_t clock; /* Hz */

sys/arch/mips64/mips64/clock.c

90

uint64_t cp0_freq = curcpu()->ci_hw.clock / CP0_CYCLE_DIVIDER;

sys/arch/mips64/mips64/cpu.c

195

printf(" %d MHz, ", ch->clock / 1000000);

sys/arch/mips64/mips64/mips64_machdep.c

241

delayconst = bootcpu_hwinfo.clock / CP0_CYCLE_DIVIDER;

sys/arch/mips64/mips64/mips64_machdep.c

301

ci->ci_hw.clock = cycles_per_sec * CP0_CYCLE_DIVIDER;

sys/arch/mips64/mips64/mips64_machdep.c

323

(uint64_t)ci->ci_hw.clock / CP0_CYCLE_DIVIDER;

sys/arch/octeon/dev/cn30xxpowvar.h

375

cpu_clock_hz = curcpu()->ci_hw.clock;

sys/arch/octeon/octeon/machdep.c

336

bootcpu_hwinfo.clock = boot_desc->eclock;

sys/arch/octeon/octeon/machdep.c

442

bootcpu_hwinfo.clock / 1000000);

sys/arch/riscv64/dev/smtclock.c

326

const struct smtclock *clock;

sys/arch/riscv64/dev/smtclock.c

330

for (clock = sc->sc_clocks; clock->idx != -1; clock++) {

sys/arch/riscv64/dev/smtclock.c

331

if (clock->idx == idx)

sys/arch/riscv64/dev/smtclock.c

335

if (clock->idx == -1)

sys/arch/riscv64/dev/smtclock.c

349

reg = HREAD4(sc, clock->reg);

sys/arch/riscv64/dev/smtclock.c

380

const struct smtclock *clock;

sys/arch/riscv64/dev/smtclock.c

383

for (clock = sc->sc_clocks; clock->idx != -1; clock++) {

sys/arch/riscv64/dev/smtclock.c

384

if (clock->idx == idx)

sys/arch/riscv64/dev/smtclock.c

388

if (clock->idx == -1) {

sys/arch/riscv64/dev/smtclock.c

407

HWRITE4(sc, clock->reg, 0);

sys/arch/riscv64/dev/smtclock.c

413

HSET4(sc, clock->reg, (1U << clock->bit));

sys/arch/riscv64/dev/smtclock.c

415

HCLR4(sc, clock->reg, (1U << clock->bit));

sys/arch/sparc64/dev/pcfiic_ebus.c

111

clock = PCF_CLOCK_3 | PCF_FREQ_90;

sys/arch/sparc64/dev/pcfiic_ebus.c

113

clock = PCF_CLOCK_4_43 | PCF_FREQ_90;

sys/arch/sparc64/dev/pcfiic_ebus.c

174

pcfiic_attach(sc, (i2c_addr_t)(addr >> 1), clock, swapregs,

sys/arch/sparc64/dev/pcfiic_ebus.c

93

u_int8_t clock = PCF_CLOCK_12 | PCF_FREQ_90;

sys/dev/fdt/amlmmc.c

506

uint32_t div, clock;

sys/dev/fdt/amlmmc.c

526

clock = SD_EMMC_CLOCK_CLK_SRC_24M | div;

sys/dev/fdt/amlmmc.c

529

clock = SD_EMMC_CLOCK_CLK_SRC_FCLK | div;

sys/dev/fdt/amlmmc.c

541

clock |= SD_EMMC_CLOCK_ALWAYS_ON;

sys/dev/fdt/amlmmc.c

542

clock |= SD_EMMC_CLOCK_CO_PHASE_180;

sys/dev/fdt/amlmmc.c

543

clock |= SD_EMMC_CLOCK_TX_PHASE_0;

sys/dev/fdt/amlmmc.c

544

clock |= SD_EMMC_CLOCK_RX_PHASE_0;

sys/dev/fdt/amlmmc.c

545

HWRITE4(sc, SD_EMMC_CLOCK, clock);

sys/dev/fdt/imxccm.c

372

imxccm_armclk_set_parent(struct imxccm_softc *sc, enum imxanatop_clocks clock)

sys/dev/fdt/imxccm.c

374

switch (clock)

sys/dev/fdt/rkdwhdmi.c

275

adjusted_mode->clock * 1000);

sys/dev/fdt/rkdwhdmi.c

278

dsc->sc_dev.dv_xname, adjusted_mode->clock * 1000,

sys/dev/fdt/rkdwhdmi.c

292

if (mode->clock == sc->sc_base.sc_mpll_config[i].pixel_clock)

sys/dev/fdt/rkvop.c

420

clock_set_frequency(sc->sc_node, "dclk_vop", adjusted_mode->clock * 1000);

sys/dev/fdt/simplepanel.c

35

.clock = 148500,

sys/dev/fdt/sxiccmu.c

1689

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

1734

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

1736

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

1739

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

1750

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

1794

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

1796

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

1799

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

1809

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

1816

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

1818

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

1821

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

1831

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

1879

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

1881

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

1884

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

1894

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

1901

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

1903

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

1906

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

1986

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

2045

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

2047

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

2050

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

2161

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

2169

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

2171

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

2174

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

2184

struct sxiccmu_clock clock;

sys/dev/fdt/sxiccmu.c

2191

clock.sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

2193

sc->sc_gates[idx].reg, 4, &clock.sc_ioh);

sys/dev/fdt/sxiccmu.c

2196

return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);

sys/dev/fdt/sxiccmu.c

583

struct sxiccmu_clock *clock;

sys/dev/fdt/sxiccmu.c

593

clock = malloc(sizeof(*clock), M_DEVBUF, M_WAITOK);

sys/dev/fdt/sxiccmu.c

594

clock->sc_node = node;

sys/dev/fdt/sxiccmu.c

596

clock->sc_iot = sc->sc_iot;

sys/dev/fdt/sxiccmu.c

598

error = bus_space_map(clock->sc_iot, reg[0], reg[1], 0,

sys/dev/fdt/sxiccmu.c

599

&clock->sc_ioh);

sys/dev/fdt/sxiccmu.c

601

error = bus_space_subregion(clock->sc_iot, sc->sc_ioh,

sys/dev/fdt/sxiccmu.c

602

sxiccmu_devices[i].offset, 4, &clock->sc_ioh);

sys/dev/fdt/sxiccmu.c

606

free(clock, M_DEVBUF, sizeof(*clock));

sys/dev/fdt/sxiccmu.c

610

clock->sc_cd.cd_node = node;

sys/dev/fdt/sxiccmu.c

611

clock->sc_cd.cd_cookie = clock;

sys/dev/fdt/sxiccmu.c

612

clock->sc_cd.cd_get_frequency = sxiccmu_devices[i].get_frequency;

sys/dev/fdt/sxiccmu.c

613

clock->sc_cd.cd_set_frequency = sxiccmu_devices[i].set_frequency;

sys/dev/fdt/sxiccmu.c

614

clock->sc_cd.cd_enable = sxiccmu_devices[i].enable;

sys/dev/fdt/sxiccmu.c

615

clock_register(&clock->sc_cd);

sys/dev/fdt/sxiccmu.c

618

clock->sc_rd.rd_node = node;

sys/dev/fdt/sxiccmu.c

619

clock->sc_rd.rd_cookie = clock;

sys/dev/fdt/sxiccmu.c

620

clock->sc_rd.rd_reset = sxiccmu_devices[i].reset;

sys/dev/fdt/sxiccmu.c

621

reset_register(&clock->sc_rd);

sys/dev/ic/ac97.c

1233

ac97_set_clock(struct ac97_codec_if *codec_if, unsigned int clock)

sys/dev/ic/ac97.c

1238

as->ac97_clock = clock;

sys/dev/ic/ac97.c

330

void ac97_set_clock(struct ac97_codec_if *codec_if, unsigned int clock);

sys/dev/ic/ac97.h

69

unsigned int clock);

sys/dev/ic/ar5211.c

272

u_int32_t turbo, mode, clock;

sys/dev/ic/ar5211.c

276

clock = 0;

sys/dev/ic/ar5211.c

284

clock |= AR5K_AR5211_PHY_PLL_44MHZ;

sys/dev/ic/ar5211.c

287

clock |= AR5K_AR5211_PHY_PLL_40MHZ;

sys/dev/ic/ar5211.c

329

AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock);

sys/dev/ic/ar5212.c

317

u_int32_t turbo, mode, clock;

sys/dev/ic/ar5212.c

321

clock = 0;

sys/dev/ic/ar5212.c

329

clock = AR5K_AR5212_PHY_PLL_AR5112;

sys/dev/ic/ar5212.c

332

clock = AR5K_AR5212_PHY_PLL_AR5111;

sys/dev/ic/ar5212.c

337

clock |= AR5K_AR5212_PHY_PLL_44MHZ;

sys/dev/ic/ar5212.c

340

clock |= AR5K_AR5212_PHY_PLL_40MHZ;

sys/dev/ic/ar5212.c

382

AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock);

sys/dev/ic/ar5212.c

646

ds_coef_man, clock;

sys/dev/ic/ar5212.c

648

clock = 40;

sys/dev/ic/ar5212.c

649

coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channel;

sys/dev/ic/ar5xxx.c

1188

u_int32_t data0, data1, clock;

sys/dev/ic/ar5xxx.c

1210

clock = 1;

sys/dev/ic/ar5xxx.c

1212

| (clock << 1) | (1 << 10) | 1;

sys/dev/ic/ar5xxx.c

1214

clock = 0;

sys/dev/ic/ar5xxx.c

1216

| (clock << 1) | (1 << 10) | 1;

sys/dev/ic/ar5xxx.c

630

ar5k_clocktoh(u_int clock)

sys/dev/ic/ar5xxx.c

632

return (clock / 40);

sys/dev/ic/dwhdmi.c

511

switch (sc->sc_curmode.clock) {

sys/dev/ic/dwhdmiphy.c

299

if (mode->clock <= mpll_conf->pixel_clock)

sys/dev/ic/dwhdmiphy.c

307

if (mode->clock <= phy_conf->pixel_clock)

sys/dev/ic/pcf8584.c

102

pcfiic_attach(struct pcfiic_softc *sc, i2c_addr_t addr, u_int8_t clock,

sys/dev/ic/pcf8584.c

116

sc->sc_clock = clock;

sys/dev/ic/siop_common.c

119

if (sc->clock_period != scf_period[i].clock)

sys/dev/ic/siop_common.c

129

if (sc->clock_period != dt_scf_period[i].clock)

sys/dev/ic/siop_common.c

448

if (sc->clock_period != dt_scf_period[i].clock)

sys/dev/ic/siop_common.c

540

if (sc->clock_period != scf_period[i].clock)

sys/dev/ic/siop_common.c

592

if (sc->clock_period != scf_period[i].clock)

sys/dev/ic/siopreg.h

74

int clock; /* clock period (ns * 10) */

sys/dev/ofw/ofw_clock.c

144

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

155

clock = clocks;

sys/dev/ofw/ofw_clock.c

156

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

158

freq = clock_get_frequency_cells(clock);

sys/dev/ofw/ofw_clock.c

161

clock = clock_next_clock(clock);

sys/dev/ofw/ofw_clock.c

185

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

196

clock = clocks;

sys/dev/ofw/ofw_clock.c

197

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

199

rv = clock_set_frequency_cells(clock, freq);

sys/dev/ofw/ofw_clock.c

202

clock = clock_next_clock(clock);

sys/dev/ofw/ofw_clock.c

226

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

236

clock = clocks;

sys/dev/ofw/ofw_clock.c

237

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

239

clock_enable_cells(clock, on);

sys/dev/ofw/ofw_clock.c

242

clock = clock_next_clock(clock);

sys/dev/ofw/ofw_clock.c

289

uint32_t *clock, *parent, *rate;

sys/dev/ofw/ofw_clock.c

299

clock = clocks = malloc(clen, M_TEMP, M_WAITOK);

sys/dev/ofw/ofw_clock.c

313

while (clock && clock < clocks + (clen / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

316

clock_set_parent_cells(clock, parent);

sys/dev/ofw/ofw_clock.c

320

clock_set_frequency_cells(clock, *rate);

sys/dev/ofw/ofw_clock.c

322

clock = clock_next_clock(clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1072

struct amdgpu_clock clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1691

u32 clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1704

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

100

amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

101

amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

102

amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

103

res.clock = clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

51

static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

58

cts = clock * 1000;

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

88

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

95

if (amdgpu_afmt_predefined_acr[i].clock == clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1017

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1038

args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1058

args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1080

args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1093

args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1115

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1134

args.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

589

struct amdgpu_pll *ppll = &adev->clock.ppll[0];

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

590

struct amdgpu_pll *spll = &adev->clock.spll;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

591

struct amdgpu_pll *mpll = &adev->clock.mpll;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

633

adev->clock.ppll[i] = *ppll;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

681

adev->clock.default_sclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

683

adev->clock.default_mclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

695

adev->clock.default_dispclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

698

if (adev->clock.default_dispclk < 53900) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

700

adev->clock.default_dispclk / 100);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

701

adev->clock.default_dispclk = 60000;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

702

} else if (adev->clock.default_dispclk <= 60000) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

704

adev->clock.default_dispclk / 100);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

705

adev->clock.default_dispclk = 62500;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

707

adev->clock.dp_extclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

710

adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

711

if (adev->clock.max_pixel_clock == 0)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

712

adev->clock.max_pixel_clock = 40000;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

721

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

722

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

901

int id, u32 clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

935

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

953

(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

975

(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

153

int id, u32 clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

157

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

163

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

205

u32 clock,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

717

struct amdgpu_pll *spll = &adev->clock.spll;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

718

struct amdgpu_pll *mpll = &adev->clock.mpll;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

731

adev->clock.default_sclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

733

adev->clock.default_mclk =

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

736

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

737

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1256

if (mode->clock > max_digital_pixel_clock_khz)

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1261

if ((mode->clock / 10) > adev->clock.max_pixel_clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1393

if ((adev->clock.default_dispclk >= 53900) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1544

if (mode->clock > 340000)

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1547

if (mode->clock > 165000)

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

351

amdgpu_encoder->native_mode.clock = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

365

native_mode->clock != 0) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

589

(amdgpu_encoder->native_mode.clock == 0))

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

618

if (!native_mode->clock) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

630

if (!native_mode->clock) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

846

if ((mode->clock / 10) > adev->clock.max_pixel_clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c

176

adjusted_mode->clock = native_mode->clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

132

static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

141

val |= clock ? 0 : rec->en_clk_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

930

adev->clock.default_sclk * 10;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

933

adev->clock.default_mclk * 10;

sys/dev/pci/drm/amd/amdgpu/amdgpu_pll.c

351

if ((crtc->mode.clock == test_crtc->mode.clock) &&

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

313

u32 adjusted_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

315

u32 dp_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

316

u32 clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

318

bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

349

adjusted_clock = mode->clock * 2;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

363

clock = (clock * 5) / 4;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

366

clock = (clock * 3) / 2;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

369

clock = clock * 2;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

390

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

402

args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

580

u32 clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

605

if (clock == ATOM_DISABLE)

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

607

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

617

args.v2.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

627

args.v3.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

644

args.v5.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

674

args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

706

args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

709

(clock > 165000))

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

771

amdgpu_connector->pixelclock_for_modeset = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

789

mode->clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

796

mode->clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

803

mode->clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

823

u32 pll_clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

824

u32 clock = mode->clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

832

clock = amdgpu_crtc->adjusted_clock;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

836

pll = &adev->clock.ppll[0];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

839

pll = &adev->clock.ppll[1];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

844

pll = &adev->clock.ppll[2];

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

860

encoder_mode, amdgpu_encoder->encoder_id, clock,

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.h

47

u32 clock,

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

422

mode->clock,

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

445

mode->clock, &dp_lanes, &dp_clock);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1063

if (is_dp && adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1988

lvds->native_mode.clock =

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

936

if (is_dp && adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

996

if (adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/cik.c

1451

static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/pci/drm/amd/amdgpu/cik.c

1460

clock, false, &dividers);

sys/dev/pci/drm/amd/amdgpu/cik.c

919

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1039

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1041

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1055

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1094

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1476

static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1480

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1531

static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1539

u32 dto_modulo = clock;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1592

dce_v10_0_audio_set_dto(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1675

dce_v10_0_afmt_update_ACR(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2246

if (adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2897

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3361

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1478

uint32_t clock, int bpc)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1482

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1558

static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1585

WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1588

WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1764

dce_v6_0_audio_set_dto(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1766

dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1768

dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2225

if (adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2843

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3252

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

897

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

899

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

917

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

944

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

985

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

997

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1008

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1047

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1457

static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1461

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1500

static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1508

u32 dto_modulo = clock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1559

dce_v8_0_audio_set_dto(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1629

dce_v8_0_afmt_update_ACR(encoder, mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2154

if (adev->clock.dp_extclk)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2814

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3269

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

992

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

994

(u32)mode->clock);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7691

uint64_t clock, clock_lo, clock_hi, hi_check;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7708

clock = clock_lo | (clock_hi << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7725

clock = clock_lo | (clock_hi << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7740

clock = clock_lo | (clock_hi << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7755

clock = clock_lo | (clock_hi << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7758

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5162

uint64_t clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5184

clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5186

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3824

uint64_t clock = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3828

clock = adev->smuio.funcs->get_gpu_clock_counter(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3832

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2923

uint64_t clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2927

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2930

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3951

uint64_t clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3955

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3958

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5106

uint64_t clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5110

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5113

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4271

uint64_t clock, clock_lo, clock_hi, hi_check;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4287

clock = clock_lo | (clock_hi << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4295

clock = gfx_v9_0_kiq_read_clock(adev);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4298

clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4305

return clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

511

uint64_t clock;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

519

return clock;

sys/dev/pci/drm/amd/amdgpu/nv.c

313

return adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/si.c

1484

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/si.c

1738

unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

41

u64 clock;

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

53

clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

55

return clock;

sys/dev/pci/drm/amd/amdgpu/soc15.c

347

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/soc21.c

228

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/soc24.c

98

return adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/vi.c

541

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/amdgpu/vi.c

980

static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/pci/drm/amd/amdgpu/vi.c

989

clock, false, &dividers);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11162

if (old_mode->clock == new_mode->clock &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11187

num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6698

timing_out->pix_clk_100hz = mode_in->clock * 10;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6799

native_mode->clock == drm_mode->clock &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6937

if (aconnector->freesync_vid_base.clock != 0)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

6992

if (high_mode->clock == 0 || high_mode->clock != mode->clock ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7939

drm_mode->clock,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8236

int clock, bpp = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8280

clock = adjusted_mode->clock;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8281

dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8424

amdgpu_encoder->native_mode.clock = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

8652

num = (unsigned long long)m->clock * 1000 * 1000;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

234

DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

235

dc_clks->clocks_in_khz[i] = pp_clks->clock[i];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

531

static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

536

amdgpu_dpm_set_min_deep_sleep_dcefclk(adev, clock);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

539

static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

544

amdgpu_dpm_set_hard_min_dcefclk_by_freq(adev, clock);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

540

int clock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

548

clock = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

552

ASSERT(clock);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

553

return clock;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

466

int clock = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

474

clock = clocks[i];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

478

ASSERT(clock);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

479

return clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

165

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

490

struct pp_display_clock_request *clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

496

int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

497

int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

498

int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1857

struct pp_display_clock_request *clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1867

clock);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1920

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1930

clock);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1937

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1946

clock);

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1951

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1960

clock);

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

55

if (amdgpu_crtc->hw_mode.clock) {

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

65

vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;

sys/dev/pci/drm/amd/pm/amdgpu_dpm_internal.c

93

cfg->display_clk = adev->clock.default_dispclk;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

584

struct pp_display_clock_request *clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

591

uint32_t clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

593

uint32_t clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

595

uint32_t clock);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3002

adev->pm.default_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3003

adev->pm.default_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3004

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3005

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3269

u32 i, clock = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3272

*max_clock = clock;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3277

if (clock < table->entries[i].clk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3278

clock = table->entries[i].clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3280

*max_clock = clock;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3284

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3292

if (clock <= table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5340

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5462

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7289

pl->mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7290

pl->sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7791

adev->pm.default_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7792

adev->pm.default_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7793

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7794

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1147

struct pp_display_clock_request *clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1151

if (!hwmgr || !hwmgr->pm_en || !clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1154

return phm_display_clock_voltage_request(hwmgr, clock);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1305

static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1317

hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1322

static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1334

hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1339

static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1351

hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

469

struct pp_display_clock_request *clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

476

return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

533

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

541

clock = 2700;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

543

clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

545

return clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

780

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

790

clock = 2700;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

796

clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

800

clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

804

return clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1155

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1157

if (clock >= MEM_FREQ_LOW_LATENCY &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1158

clock < MEM_FREQ_HIGH_LATENCY)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1160

else if (clock >= MEM_FREQ_HIGH_LATENCY)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

204

static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

208

if (clock && smu10_data->deep_sleep_dcefclk != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

209

smu10_data->deep_sleep_dcefclk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

218

static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

222

if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

223

smu10_data->dcf_actual_hard_min_freq = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

232

static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

236

if (clock && smu10_data->f_actual_hard_min_freq != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

237

smu10_data->f_actual_hard_min_freq = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

246

static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

250

if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

251

smu10_data->gfx_actual_soft_min_freq = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

254

clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

260

static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

264

if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

265

smu10_data->gfx_max_freq_limit = clock * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

268

clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1020

if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1028

if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4265

dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4272

dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4975

uint32_t i, now, clock, pcie_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4979

ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4983

if (clock > sclk_table->dpm_levels[i].value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4995

ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4999

if (clock > mclk_table->dpm_levels[i].value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5031

i, odn_sclk_table->entries[i].clock/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5040

i, odn_mclk_table->entries[i].clock/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5187

clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5192

clocks->clock[i] = sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5224

clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5232

clocks->clock[i] = mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5545

podn_dpm_table_in_backend->entries[input_level].clock = input_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5806

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5813

PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5815

temp = clock >> i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

954

entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

966

entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

385

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

100

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

110

if (clock <= table->entries[i].clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

118

if (clock >= table->entries[i].clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1188

unsigned long clock = 0, level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1199

clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1201

clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1203

data->sclk_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1204

data->sclk_dpm.hard_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

130

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

140

if (clock <= ptable->entries[i].vclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

148

if (clock >= ptable->entries[i].vclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1668

clocks->clock[i] = data->sys_info.display_clock[i] * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1673

clocks->clock[i] = table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1678

clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

559

unsigned long clock = 0, level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

570

clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

572

clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

574

data->sclk_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

575

data->sclk_dpm.hard_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

585

unsigned long clock = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

600

clock = table->entries[level].vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

602

clock = table->entries[table->count - 1].vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

604

data->uvd_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

605

data->uvd_dpm.hard_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

615

unsigned long clock = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

630

clock = table->entries[level].ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

632

clock = table->entries[table->count - 1].ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

634

data->vce_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

635

data->vce_dpm.hard_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

645

unsigned long clock = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

660

clock = table->entries[level].acpclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

662

clock = table->entries[table->count - 1].acpclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

664

data->acp_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

665

data->acp_dpm.hard_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

69

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

698

unsigned long clock = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

711

clock = hwmgr->display_config->min_core_set_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

712

if (clock == 0)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

715

if (data->sclk_dpm.hard_min_clk != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

716

data->sclk_dpm.hard_min_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

726

clock = data->sclk_dpm.soft_min_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

736

if (clock < stable_pstate_sclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

737

clock = stable_pstate_sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

740

if (data->sclk_dpm.soft_min_clk != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

741

data->sclk_dpm.soft_min_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

752

data->sclk_dpm.soft_max_clk != clock) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

753

data->sclk_dpm.soft_max_clk = clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

79

if (clock <= ptable->entries[i].ecclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

87

if (clock >= ptable->entries[i].ecclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1002

&(clock->ACMax)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1009

&(clock->ACMin)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1016

&(clock->DCMax)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1841

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1848

*clock = data->clk_range[clock_select].ACMax;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1850

*clock = data->clk_range[clock_select].ACMin;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1883

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

595

PPCLK_e clkID, uint32_t index, uint32_t *clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

60

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

603

clock) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

997

PPCLK_e clkid, struct vega12_clock_range *clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1588

PP_Clock *clock, PPCLK_e clock_select)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1595

clock)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1600

if (*clock == 0) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1604

clock)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2038

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2043

*clock = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2048

clock)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2055

clock)) == 0,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2838

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

373

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

384

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

457

struct pp_display_clock_request *clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

310

struct pp_display_clock_request *clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

326

int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

349

int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

350

int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

351

int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

352

int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

279

uint32_t clock, uint32_t *vol)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

287

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

298

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

313

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

343

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

361

sclk->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

388

static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

395

if (clock < min) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

400

temp = clock >> i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

409

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

415

result = ci_calculate_sclk_params(hwmgr, clock, level);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

419

hwmgr->dyn_state.vddc_dependency_on_sclk, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

426

level->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

432

clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

450

ci_get_sleep_divider_id_from_clock(clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1143

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1148

result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1154

mclk->MclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1156

mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1162

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1178

vdd_dep_table, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1203

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1209

result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

354

uint32_t clock, uint32_t *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

368

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

856

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

871

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

902

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

926

sclk->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

937

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

947

result = fiji_calculate_sclk_params(hwmgr, clock, level);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

956

vdd_dep_table, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

963

level->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

977

level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

508

uint32_t clock, uint32_t *vol)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

518

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1154

uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1171

vdd_dep_table, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1178

mem_level->MclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1192

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

355

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

369

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

891

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

902

sclk_setting->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

904

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

923

if (clock > smu_data->range_table[i].trans_lower_frequency

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

924

&& clock <= smu_data->range_table[i].trans_upper_frequency) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

930

sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

931

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

937

pcc_target_freq = clock - (clock * pcc_target_percent / 100);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

944

ss_target_freq = clock - (clock * ss_target_percent / 100);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

956

uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

967

result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

976

vdd_dep_table, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

996

level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

248

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

261

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1000

result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1017

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

602

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

616

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

720

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

731

sclk_setting->SclkFrequency = clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

733

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

752

if (clock > smu_data->range_table[i].trans_lower_frequency

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

753

&& clock <= smu_data->range_table[i].trans_upper_frequency) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

760

((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

762

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

768

pcc_target_freq = clock - (clock * pcc_target_percent / 100);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

777

ss_target_freq = clock - (clock * ss_target_percent / 100);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

790

static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

797

PP_ASSERT_WITH_CODE((clock >= min),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

801

temp = clock / (i + 1);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

810

uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

820

result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

824

table_info->vdd_dep_on_sclk, clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

842

level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

964

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

969

clock, &mpll_param),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

982

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

993

table_info->vdd_dep_on_mclk, clock,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

794

smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

811

clk_id << 16, clock);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

817

if (*clock != 0)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

822

clk_id << 16, clock);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

829

smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

846

clk_id << 16, clock);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

852

if (*clock != 0)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

857

clk_id << 16, clock);

sys/dev/pci/drm/apple/parser.c

422

u64 clock = mul_u32_u32(pixels, vert->precise_sync_rate);

sys/dev/pci/drm/apple/parser.c

424

return DIV_ROUND_CLOSEST_ULL(clock >> 16, 1000);

sys/dev/pci/drm/apple/parser.c

528

.clock = calculate_clock(&horiz, &vert),

sys/dev/pci/drm/apple/trace.h

531

u32 height, u32 clock, u32 color_mode),

sys/dev/pci/drm/apple/trace.h

532

TP_ARGS(dcp, id, score, width, height, clock, color_mode),

sys/dev/pci/drm/apple/trace.h

539

__field(u32, clock)

sys/dev/pci/drm/apple/trace.h

548

__entry->clock = clock;

sys/dev/pci/drm/apple/trace.h

557

__entry->clock >> 16,

sys/dev/pci/drm/apple/trace.h

558

((__entry->clock & 0xffff) * 1000) >> 16,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4796

int drm_dp_calc_pbn_mode(int clock, int bpp)

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4819

return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),

sys/dev/pci/drm/display/drm_hdmi_helper.c

215

unsigned long long clock = mode->clock * 1000ULL;

sys/dev/pci/drm/display/drm_hdmi_helper.c

252

clock = clock / 2;

sys/dev/pci/drm/display/drm_hdmi_helper.c

255

clock = clock * 2;

sys/dev/pci/drm/display/drm_hdmi_helper.c

257

return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

533

unsigned long long clock)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

538

if (info->max_tmds_clock && clock > info->max_tmds_clock * 1000)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

544

status = funcs->tmds_char_rate_valid(connector, mode, clock);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

559

unsigned long long clock;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

561

clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

562

if (!clock)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

565

status = hdmi_clock_valid(connector, mode, clock);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

569

conn_state->hdmi.tmds_char_rate = clock;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

884

unsigned long long clock;

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

886

clock = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

887

if (!clock)

sys/dev/pci/drm/display/drm_hdmi_state_helper.c

890

return hdmi_clock_valid(connector, mode, clock);

sys/dev/pci/drm/drm_edid.c

3352

return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);

sys/dev/pci/drm/drm_edid.c

3579

mode->clock = 1088 * 10;

sys/dev/pci/drm/drm_edid.c

3581

mode->clock = le16_to_cpu(timing->pixel_clock) * 10;

sys/dev/pci/drm/drm_edid.c

3703

if (mode->clock > max_clock)

sys/dev/pci/drm/drm_edid.c

4301

unsigned int clock = cea_mode->clock;

sys/dev/pci/drm/drm_edid.c

4304

return clock;

sys/dev/pci/drm/drm_edid.c

4312

clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);

sys/dev/pci/drm/drm_edid.c

4314

clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);

sys/dev/pci/drm/drm_edid.c

4316

return clock;

sys/dev/pci/drm/drm_edid.c

4362

if (!to_match->clock)

sys/dev/pci/drm/drm_edid.c

4375

clock1 = cea_mode.clock;

sys/dev/pci/drm/drm_edid.c

4378

if (abs(to_match->clock - clock1) > clock_tolerance &&

sys/dev/pci/drm/drm_edid.c

4379

abs(to_match->clock - clock2) > clock_tolerance)

sys/dev/pci/drm/drm_edid.c

4403

if (!to_match->clock)

sys/dev/pci/drm/drm_edid.c

4416

clock1 = cea_mode.clock;

sys/dev/pci/drm/drm_edid.c

4419

if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&

sys/dev/pci/drm/drm_edid.c

4420

KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))

sys/dev/pci/drm/drm_edid.c

4469

if (!to_match->clock)

sys/dev/pci/drm/drm_edid.c

4480

clock1 = hdmi_mode->clock;

sys/dev/pci/drm/drm_edid.c

4483

if (abs(to_match->clock - clock1) > clock_tolerance &&

sys/dev/pci/drm/drm_edid.c

4484

abs(to_match->clock - clock2) > clock_tolerance)

sys/dev/pci/drm/drm_edid.c

4507

if (!to_match->clock)

sys/dev/pci/drm/drm_edid.c

4518

clock1 = hdmi_mode->clock;

sys/dev/pci/drm/drm_edid.c

4521

if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||

sys/dev/pci/drm/drm_edid.c

4522

KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&

sys/dev/pci/drm/drm_edid.c

4570

clock1 = cea_mode->clock;

sys/dev/pci/drm/drm_edid.c

4575

if (mode->clock != clock1 && mode->clock != clock2)

sys/dev/pci/drm/drm_edid.c

4589

if (mode->clock != clock1)

sys/dev/pci/drm/drm_edid.c

4590

newmode->clock = clock1;

sys/dev/pci/drm/drm_edid.c

4592

newmode->clock = clock2;

sys/dev/pci/drm/drm_edid.c

5389

int clock1, clock2, clock;

sys/dev/pci/drm/drm_edid.c

5401

clock1 = cea_mode->clock;

sys/dev/pci/drm/drm_edid.c

5408

clock1 = cea_mode->clock;

sys/dev/pci/drm/drm_edid.c

5416

if (abs(mode->clock - clock1) < abs(mode->clock - clock2))

sys/dev/pci/drm/drm_edid.c

5417

clock = clock1;

sys/dev/pci/drm/drm_edid.c

5419

clock = clock2;

sys/dev/pci/drm/drm_edid.c

5421

if (mode->clock == clock)

sys/dev/pci/drm/drm_edid.c

5427

type, vic, mode->clock, clock);

sys/dev/pci/drm/drm_edid.c

5428

mode->clock = clock;

sys/dev/pci/drm/drm_edid.c

6853

mode->clock = type_7 ? pixel_clock : pixel_clock * 10;

sys/dev/pci/drm/drm_modes.c

1002

drm_mode->clock = pixel_freq;

sys/dev/pci/drm/drm_modes.c

1084

dmode->clock = vm->pixelclock / 1000;

sys/dev/pci/drm/drm_modes.c

1125

vm->pixelclock = dmode->clock * 1000;

sys/dev/pci/drm/drm_modes.c

1301

if (check_mul_overflow(mode->clock, num, &num))

sys/dev/pci/drm/drm_modes.c

1353

p->crtc_clock = p->clock;

sys/dev/pci/drm/drm_modes.c

1494

if (mode1->clock && mode2->clock)

sys/dev/pci/drm/drm_modes.c

1495

return KHZ2PICOS(mode1->clock) == KHZ2PICOS(mode2->clock);

sys/dev/pci/drm/drm_modes.c

1497

return mode1->clock == mode2->clock;

sys/dev/pci/drm/drm_modes.c

1640

if (mode->clock == 0)

sys/dev/pci/drm/drm_modes.c

1860

diff = b->clock - a->clock;

sys/dev/pci/drm/drm_modes.c

2597

out->clock = in->clock;

sys/dev/pci/drm/drm_modes.c

2653

if (in->clock > INT_MAX || in->vrefresh > INT_MAX)

sys/dev/pci/drm/drm_modes.c

2656

out->clock = in->clock;

sys/dev/pci/drm/drm_modes.c

455

mode->clock = pixel_clock_hz / 1000;

sys/dev/pci/drm/drm_modes.c

806

tmp -= drm_mode->clock % CVT_CLOCK_STEP;

sys/dev/pci/drm/drm_modes.c

807

drm_mode->clock = tmp;

sys/dev/pci/drm/i915/display/dvo_ch7017.c

254

if (mode->clock > 160000)

sys/dev/pci/drm/i915/display/dvo_ch7017.c

274

if (mode->clock < 100000) {

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

283

if (mode->clock > 165000)

sys/dev/pci/drm/i915/display/dvo_ch7xxx.c

295

if (mode->clock <= 65000) {

sys/dev/pci/drm/i915/display/dvo_ivch.c

321

if (mode->clock > 112000)

sys/dev/pci/drm/i915/display/dvo_ns2501.c

540

if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||

sys/dev/pci/drm/i915/display/dvo_ns2501.c

541

(mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||

sys/dev/pci/drm/i915/display/dvo_ns2501.c

542

(mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {

sys/dev/pci/drm/i915/display/intel_audio.c

207

if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)

sys/dev/pci/drm/i915/display/intel_audio.c

223

hdmi_audio_clock[i].clock,

sys/dev/pci/drm/i915/display/intel_audio.c

248

crtc_state->port_clock == hdmi_ncts_table[i].clock) {

sys/dev/pci/drm/i915/display/intel_audio.c

506

pixel_clk = crtc_state->hw.adjusted_mode.clock;

sys/dev/pci/drm/i915/display/intel_audio.c

82

int clock;

sys/dev/pci/drm/i915/display/intel_audio.c

88

int clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1087

u32 mul, clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1095

clock = MHz(135); /* LPT:H */

sys/dev/pci/drm/i915/display/intel_backlight.c

1097

clock = MHz(24); /* LPT:LP */

sys/dev/pci/drm/i915/display/intel_backlight.c

1099

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);

sys/dev/pci/drm/i915/display/intel_backlight.c

1125

int clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1128

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1130

clock = KHz(display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_backlight.c

1132

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);

sys/dev/pci/drm/i915/display/intel_backlight.c

1143

int clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1146

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1148

clock = KHz(display->cdclk.hw.cdclk);

sys/dev/pci/drm/i915/display/intel_backlight.c

1150

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);

sys/dev/pci/drm/i915/display/intel_backlight.c

1161

int mul, clock;

sys/dev/pci/drm/i915/display/intel_backlight.c

1165

clock = KHz(19200);

sys/dev/pci/drm/i915/display/intel_backlight.c

1167

clock = MHz(25);

sys/dev/pci/drm/i915/display/intel_backlight.c

1170

clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq);

sys/dev/pci/drm/i915/display/intel_backlight.c

1174

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);

sys/dev/pci/drm/i915/display/intel_bios.c

557

panel_fixed_mode->clock = dvo_timing->clock * 10;

sys/dev/pci/drm/i915/display/intel_bios.c

992

panel_fixed_mode->clock = dtd->pixel_clock;

sys/dev/pci/drm/i915/display/intel_crt.c

365

if (mode->clock < 25000)

sys/dev/pci/drm/i915/display/intel_crt.c

380

if (mode->clock > max_clock)

sys/dev/pci/drm/i915/display/intel_crt.c

383

if (mode->clock > max_dotclk)

sys/dev/pci/drm/i915/display/intel_crt.c

388

ilk_get_lanes_required(mode->clock, 270000, 24) > 2)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1001

.clock = 243000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1026

.clock = 324000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1051

.clock = 432000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1076

.clock = 675000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1114

.clock = 1350000, /* 13.5 Gbps */

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1169

.clock = 25200,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1195

.clock = 27000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1221

.clock = 74250,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1247

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1273

.clock = 594000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1300

.clock = 27027,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1310

.clock = 28320,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1320

.clock = 30240,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1330

.clock = 31500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1340

.clock = 36000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1350

.clock = 40000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1360

.clock = 49500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1370

.clock = 50000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1380

.clock = 57284,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1390

.clock = 58000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1400

.clock = 65000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1410

.clock = 71000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1420

.clock = 74176,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1430

.clock = 75000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1440

.clock = 78750,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1450

.clock = 85500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1460

.clock = 88750,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1470

.clock = 106500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1480

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1490

.clock = 115500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1500

.clock = 119000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1510

.clock = 135000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1520

.clock = 138500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1530

.clock = 147160,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1540

.clock = 148352,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1550

.clock = 154000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1560

.clock = 162000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1570

.clock = 167000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1580

.clock = 197802,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1590

.clock = 198000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1600

.clock = 209800,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1610

.clock = 241500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1620

.clock = 262750,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1630

.clock = 268500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1640

.clock = 296703,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1650

.clock = 297000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1660

.clock = 319750,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1670

.clock = 497750,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1680

.clock = 592000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1690

.clock = 593407,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1749

.clock = 25175,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1774

.clock = 27000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1799

.clock = 74250,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1824

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1849

.clock = 594000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1874

.clock = 3000000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1899

.clock = 6000000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1924

.clock = 8000000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1949

.clock = 10000000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

1974

.clock = 12000000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2065

if (port_clock == tables[i]->clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2286

pll_state->clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2362

if (crtc_state->port_clock == tables[i]->clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2496

pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2534

static u8 intel_c20_get_dp_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2536

switch (clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2564

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2569

static u8 intel_c20_get_hdmi_rate(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2571

if (clock >= 25175 && clock <= 600000)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2574

switch (clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2584

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2589

static bool is_dp2(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2592

if (clock == 1000000 || clock == 1350000 || clock == 2000000)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2598

static bool is_hdmi_frl(u32 clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2600

switch (clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2621

static int intel_get_c20_custom_width(u32 clock, bool dp)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2623

if (dp && is_dp2(clock))

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

2625

else if (is_hdmi_frl(clock))

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3112

u32 clock, val;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3116

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3122

switch (clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3136

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3142

int clock)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3144

switch (clock) {

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3166

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3410

u32 val, clock;

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3417

clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3419

if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3420

clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3542

int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3545

INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

3548

mpll_sw_state->clock, mpll_hw_state->clock);

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

531

.clock = 162000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

557

.clock = 216000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

583

.clock = 243000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

609

.clock = 270000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

635

.clock = 324000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

661

.clock = 432000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

687

.clock = 540000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

713

.clock = 675000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

739

.clock = 810000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

787

.clock = 162000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

812

.clock = 270000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

837

.clock = 540000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

862

.clock = 810000,

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

888

.clock = 1000000, /* 10 Gbps */

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

912

.clock = 1350000, /* 13.5 Gbps */

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

937

.clock = 2000000, /* 20 Gbps */

sys/dev/pci/drm/i915/display/intel_cx0_phy.c

976

.clock = 216000,

sys/dev/pci/drm/i915/display/intel_ddi.c

268

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_ddi.c

280

switch (clock) {

sys/dev/pci/drm/i915/display/intel_ddi.c

290

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_ddi.c

4480

mode1->clock == mode2->clock; /* we want an exact match */

sys/dev/pci/drm/i915/display/intel_display.c

2225

mode->clock = timings->crtc_clock;

sys/dev/pci/drm/i915/display/intel_display.c

7979

if (mode->clock > max_dotclock(display))

sys/dev/pci/drm/i915/display/intel_display.c

8237

struct dpll clock = {

sys/dev/pci/drm/i915/display/intel_display.c

8248

i9xx_calc_dpll_params(48000, &clock) != 25154);

sys/dev/pci/drm/i915/display/intel_display.c

8252

pipe_name(pipe), clock.vco, clock.dot);

sys/dev/pci/drm/i915/display/intel_display.c

8254

fp = i9xx_dpll_compute_fp(&clock);

sys/dev/pci/drm/i915/display/intel_display.c

8257

((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |

sys/dev/pci/drm/i915/display/intel_dp.c

1274

int clock, int bpc,

sys/dev/pci/drm/i915/display/intel_dp.c

1283

tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);

sys/dev/pci/drm/i915/display/intel_dp.c

1354

int hdisplay, int clock,

sys/dev/pci/drm/i915/display/intel_dp.c

1367

return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||

sys/dev/pci/drm/i915/display/intel_dp.c

1373

int hdisplay, int clock)

sys/dev/pci/drm/i915/display/intel_dp.c

1381

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))

sys/dev/pci/drm/i915/display/intel_dp.c

1385

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))

sys/dev/pci/drm/i915/display/intel_dp.c

1420

int target_clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_dp.c

1436

if (mode->clock < 10000)

sys/dev/pci/drm/i915/display/intel_dp.c

1445

target_clock = fixed_mode->clock;

sys/dev/pci/drm/i915/display/intel_dp.c

1677

int clock = crtc_state->hw.adjusted_mode.crtc_clock;

sys/dev/pci/drm/i915/display/intel_dp.c

1697

intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,

sys/dev/pci/drm/i915/display/intel_dp.c

1765

return intel_panel_highest_mode(connector, adjusted_mode)->clock;

sys/dev/pci/drm/i915/display/intel_dp.c

1777

int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);

sys/dev/pci/drm/i915/display/intel_dp.c

1785

mode_rate = intel_dp_link_required(clock, link_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

2015

lane_count, adjusted_mode->clock,

sys/dev/pci/drm/i915/display/intel_dp.c

2176

dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,

sys/dev/pci/drm/i915/display/intel_dp.c

3047

pixel_clock = downclock_mode->clock;

sys/dev/pci/drm/i915/display/intel_dp.c

4269

mode->clock *= n;

sys/dev/pci/drm/i915/display/intel_dp.h

156

int hdisplay, int clock);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

251

int try, clock = 0;

sys/dev/pci/drm/i915/display/intel_dp_aux.c

341

while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1197

mode_rate = intel_dp_link_required(fixed_mode->clock, 18);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1465

int target_clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1482

if (mode->clock < 10000) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1492

mode_rate = intel_dp_link_required(mode->clock, min_bpp);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1514

if (mode_rate > max_rate || mode->clock > max_dotclk ||

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1515

drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

243

adjusted_mode->clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1003

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1031

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1034

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

sys/dev/pci/drm/i915/display/intel_dpll.c

1035

WARN_ON(reduced_clock->p1 != clock->p1);

sys/dev/pci/drm/i915/display/intel_dpll.c

1037

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1038

WARN_ON(reduced_clock->p1 != clock->p1);

sys/dev/pci/drm/i915/display/intel_dpll.c

1041

switch (clock->p2) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1055

WARN_ON(reduced_clock->p2 != clock->p2);

sys/dev/pci/drm/i915/display/intel_dpll.c

1072

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1079

hw_state->fp0 = pnv_dpll_compute_fp(clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1082

hw_state->fp0 = i9xx_dpll_compute_fp(clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1086

hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1093

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1102

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1104

if (clock->p1 == 2)

sys/dev/pci/drm/i915/display/intel_dpll.c

1107

dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1108

if (clock->p2 == 4)

sys/dev/pci/drm/i915/display/intel_dpll.c

1111

WARN_ON(reduced_clock->p1 != clock->p1);

sys/dev/pci/drm/i915/display/intel_dpll.c

1112

WARN_ON(reduced_clock->p2 != clock->p2);

sys/dev/pci/drm/i915/display/intel_dpll.c

1140

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1145

hw_state->fp0 = i9xx_dpll_compute_fp(clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1148

hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1255

static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)

sys/dev/pci/drm/i915/display/intel_dpll.c

1259

fp = i9xx_dpll_compute_fp(clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1260

if (ilk_needs_fb_cb_tune(clock, factor))

sys/dev/pci/drm/i915/display/intel_dpll.c

1267

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1309

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

1313

switch (clock->p2) {

sys/dev/pci/drm/i915/display/intel_dpll.c

1327

WARN_ON(reduced_clock->p2 != clock->p2);

sys/dev/pci/drm/i915/display/intel_dpll.c

1339

const struct dpll *clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

1345

hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);

sys/dev/pci/drm/i915/display/intel_dpll.c

1348

hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

1905

const struct dpll *clock = &crtc_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

1931

tmp = DPIO_M1_DIV(clock->m1) |

sys/dev/pci/drm/i915/display/intel_dpll.c

1932

DPIO_M2_DIV(clock->m2) |

sys/dev/pci/drm/i915/display/intel_dpll.c

1933

DPIO_P1_DIV(clock->p1) |

sys/dev/pci/drm/i915/display/intel_dpll.c

1934

DPIO_P2_DIV(clock->p2) |

sys/dev/pci/drm/i915/display/intel_dpll.c

1935

DPIO_N_DIV(clock->n) |

sys/dev/pci/drm/i915/display/intel_dpll.c

2026

const struct dpll *clock = &crtc_state->dpll;

sys/dev/pci/drm/i915/display/intel_dpll.c

2032

m2_frac = clock->m2 & 0x3fffff;

sys/dev/pci/drm/i915/display/intel_dpll.c

2039

DPIO_CHV_P1_DIV(clock->p1) |

sys/dev/pci/drm/i915/display/intel_dpll.c

2040

DPIO_CHV_P2_DIV(clock->p2) |

sys/dev/pci/drm/i915/display/intel_dpll.c

2045

DPIO_CHV_M2_DIV(clock->m2 >> 22));

sys/dev/pci/drm/i915/display/intel_dpll.c

2074

if (clock->vco == 5400000) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2079

} else if (clock->vco <= 6200000) {

sys/dev/pci/drm/i915/display/intel_dpll.c

2084

} else if (clock->vco <= 6480000) {

sys/dev/pci/drm/i915/display/intel_dpll.c

318

static int pnv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

320

clock->m = clock->m2 + 2;

sys/dev/pci/drm/i915/display/intel_dpll.c

321

clock->p = clock->p1 * clock->p2;

sys/dev/pci/drm/i915/display/intel_dpll.c

323

clock->vco = clock->n == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

324

DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);

sys/dev/pci/drm/i915/display/intel_dpll.c

325

clock->dot = clock->p == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

326

DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/pci/drm/i915/display/intel_dpll.c

328

return clock->dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

336

int i9xx_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

338

clock->m = i9xx_dpll_compute_m(clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

339

clock->p = clock->p1 * clock->p2;

sys/dev/pci/drm/i915/display/intel_dpll.c

341

clock->vco = clock->n + 2 == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

342

DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);

sys/dev/pci/drm/i915/display/intel_dpll.c

343

clock->dot = clock->p == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

344

DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/pci/drm/i915/display/intel_dpll.c

346

return clock->dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

349

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

351

clock->m = clock->m1 * clock->m2;

sys/dev/pci/drm/i915/display/intel_dpll.c

352

clock->p = clock->p1 * clock->p2 * 5;

sys/dev/pci/drm/i915/display/intel_dpll.c

354

clock->vco = clock->n == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

355

DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);

sys/dev/pci/drm/i915/display/intel_dpll.c

356

clock->dot = clock->p == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

357

DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/pci/drm/i915/display/intel_dpll.c

359

return clock->dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

362

int chv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

364

clock->m = clock->m1 * clock->m2;

sys/dev/pci/drm/i915/display/intel_dpll.c

365

clock->p = clock->p1 * clock->p2 * 5;

sys/dev/pci/drm/i915/display/intel_dpll.c

367

clock->vco = clock->n == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

368

DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);

sys/dev/pci/drm/i915/display/intel_dpll.c

369

clock->dot = clock->p == 0 ? 0 :

sys/dev/pci/drm/i915/display/intel_dpll.c

370

DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/pci/drm/i915/display/intel_dpll.c

372

return clock->dot;

sys/dev/pci/drm/i915/display/intel_dpll.c

430

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

439

clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

441

clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;

sys/dev/pci/drm/i915/display/intel_dpll.c

442

clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

444

clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

445

clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;

sys/dev/pci/drm/i915/display/intel_dpll.c

450

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

453

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

458

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

sys/dev/pci/drm/i915/display/intel_dpll.c

462

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

sys/dev/pci/drm/i915/display/intel_dpll.c

473

port_clock = pnv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

475

port_clock = i9xx_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

484

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

488

clock.p2 = 7;

sys/dev/pci/drm/i915/display/intel_dpll.c

490

clock.p2 = 14;

sys/dev/pci/drm/i915/display/intel_dpll.c

493

clock.p1 = 2;

sys/dev/pci/drm/i915/display/intel_dpll.c

495

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

sys/dev/pci/drm/i915/display/intel_dpll.c

499

clock.p2 = 4;

sys/dev/pci/drm/i915/display/intel_dpll.c

501

clock.p2 = 2;

sys/dev/pci/drm/i915/display/intel_dpll.c

504

port_clock = i9xx_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

523

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

534

clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

535

clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

536

clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

537

clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

538

clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);

sys/dev/pci/drm/i915/display/intel_dpll.c

540

crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

550

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

566

clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

sys/dev/pci/drm/i915/display/intel_dpll.c

567

clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;

sys/dev/pci/drm/i915/display/intel_dpll.c

569

clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);

sys/dev/pci/drm/i915/display/intel_dpll.c

570

clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);

sys/dev/pci/drm/i915/display/intel_dpll.c

571

clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);

sys/dev/pci/drm/i915/display/intel_dpll.c

572

clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);

sys/dev/pci/drm/i915/display/intel_dpll.c

574

crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

583

const struct dpll *clock)

sys/dev/pci/drm/i915/display/intel_dpll.c

585

if (clock->n < limit->n.min || limit->n.max < clock->n)

sys/dev/pci/drm/i915/display/intel_dpll.c

587

if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)

sys/dev/pci/drm/i915/display/intel_dpll.c

589

if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)

sys/dev/pci/drm/i915/display/intel_dpll.c

591

if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)

sys/dev/pci/drm/i915/display/intel_dpll.c

597

if (clock->m1 <= clock->m2)

sys/dev/pci/drm/i915/display/intel_dpll.c

602

if (clock->p < limit->p.min || limit->p.max < clock->p)

sys/dev/pci/drm/i915/display/intel_dpll.c

604

if (clock->m < limit->m.min || limit->m.max < clock->m)

sys/dev/pci/drm/i915/display/intel_dpll.c

608

if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)

sys/dev/pci/drm/i915/display/intel_dpll.c

613

if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)

sys/dev/pci/drm/i915/display/intel_dpll.c

661

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

666

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/pci/drm/i915/display/intel_dpll.c

668

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

sys/dev/pci/drm/i915/display/intel_dpll.c

669

clock.m1++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

670

for (clock.m2 = limit->m2.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

671

clock.m2 <= limit->m2.max; clock.m2++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

672

if (clock.m2 >= clock.m1)

sys/dev/pci/drm/i915/display/intel_dpll.c

674

for (clock.n = limit->n.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

675

clock.n <= limit->n.max; clock.n++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

676

for (clock.p1 = limit->p1.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

677

clock.p1 <= limit->p1.max; clock.p1++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

680

i9xx_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

683

&clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

686

clock.p != match_clock->p)

sys/dev/pci/drm/i915/display/intel_dpll.c

689

this_err = abs(clock.dot - target);

sys/dev/pci/drm/i915/display/intel_dpll.c

691

*best_clock = clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

719

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

724

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/pci/drm/i915/display/intel_dpll.c

726

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

sys/dev/pci/drm/i915/display/intel_dpll.c

727

clock.m1++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

728

for (clock.m2 = limit->m2.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

729

clock.m2 <= limit->m2.max; clock.m2++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

730

for (clock.n = limit->n.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

731

clock.n <= limit->n.max; clock.n++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

732

for (clock.p1 = limit->p1.min;

sys/dev/pci/drm/i915/display/intel_dpll.c

733

clock.p1 <= limit->p1.max; clock.p1++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

736

pnv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

739

&clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

742

clock.p != match_clock->p)

sys/dev/pci/drm/i915/display/intel_dpll.c

745

this_err = abs(clock.dot - target);

sys/dev/pci/drm/i915/display/intel_dpll.c

747

*best_clock = clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

775

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

783

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/pci/drm/i915/display/intel_dpll.c

787

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

789

for (clock.m1 = limit->m1.max;

sys/dev/pci/drm/i915/display/intel_dpll.c

790

clock.m1 >= limit->m1.min; clock.m1--) {

sys/dev/pci/drm/i915/display/intel_dpll.c

791

for (clock.m2 = limit->m2.max;

sys/dev/pci/drm/i915/display/intel_dpll.c

792

clock.m2 >= limit->m2.min; clock.m2--) {

sys/dev/pci/drm/i915/display/intel_dpll.c

793

for (clock.p1 = limit->p1.max;

sys/dev/pci/drm/i915/display/intel_dpll.c

794

clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/pci/drm/i915/display/intel_dpll.c

797

i9xx_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

800

&clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

803

this_err = abs(clock.dot - target);

sys/dev/pci/drm/i915/display/intel_dpll.c

805

*best_clock = clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

807

max_n = clock.n;

sys/dev/pci/drm/i915/display/intel_dpll.c

869

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

878

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

879

for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/pci/drm/i915/display/intel_dpll.c

880

for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;

sys/dev/pci/drm/i915/display/intel_dpll.c

881

clock.p2 -= clock.p2 > 10 ? 2 : 1) {

sys/dev/pci/drm/i915/display/intel_dpll.c

882

clock.p = clock.p1 * clock.p2 * 5;

sys/dev/pci/drm/i915/display/intel_dpll.c

884

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {

sys/dev/pci/drm/i915/display/intel_dpll.c

887

clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,

sys/dev/pci/drm/i915/display/intel_dpll.c

888

refclk * clock.m1);

sys/dev/pci/drm/i915/display/intel_dpll.c

890

vlv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

894

&clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

898

&clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

903

*best_clock = clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

927

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll.c

939

clock.n = 1;

sys/dev/pci/drm/i915/display/intel_dpll.c

940

clock.m1 = 2;

sys/dev/pci/drm/i915/display/intel_dpll.c

942

for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/pci/drm/i915/display/intel_dpll.c

943

for (clock.p2 = limit->p2.p2_fast;

sys/dev/pci/drm/i915/display/intel_dpll.c

944

clock.p2 >= limit->p2.p2_slow;

sys/dev/pci/drm/i915/display/intel_dpll.c

945

clock.p2 -= clock.p2 > 10 ? 2 : 1) {

sys/dev/pci/drm/i915/display/intel_dpll.c

948

clock.p = clock.p1 * clock.p2 * 5;

sys/dev/pci/drm/i915/display/intel_dpll.c

950

m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,

sys/dev/pci/drm/i915/display/intel_dpll.c

951

refclk * clock.m1);

sys/dev/pci/drm/i915/display/intel_dpll.c

953

if (m2 > INT_MAX/clock.m1)

sys/dev/pci/drm/i915/display/intel_dpll.c

956

clock.m2 = m2;

sys/dev/pci/drm/i915/display/intel_dpll.c

958

chv_calc_dpll_params(refclk, &clock);

sys/dev/pci/drm/i915/display/intel_dpll.c

960

if (!intel_pll_is_valid(display, limit, &clock))

sys/dev/pci/drm/i915/display/intel_dpll.c

963

if (!vlv_PLL_is_optimal(display, target, &clock, best_clock,

sys/dev/pci/drm/i915/display/intel_dpll.c

967

*best_clock = clock;

sys/dev/pci/drm/i915/display/intel_dpll.h

24

int i9xx_calc_dpll_params(int refclk, struct dpll *clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1079

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1081

switch (clock / 2) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1088

clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1099

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1101

switch (clock / 2) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1112

MISSING_CASE(clock / 2);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1667

skl_ddi_calculate_wrpll(int clock,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

1692

u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2307

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2333

if (clock > 270000)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2335

else if (clock > 135000)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2337

else if (clock > 67000)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2339

else if (clock > 33000)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2375

struct dpll clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2377

clock.m1 = 2;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2378

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2380

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2382

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2383

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2384

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2386

return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2622

int clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2715

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2719

if (clock == params[i].clock) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

2725

MISSING_CASE(clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3011

int clock = crtc_state->port_clock;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

3023

ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

809

static unsigned hsw_wrpll_get_budget_for_freq(int clock)

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

811

switch (clock) {

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

934

hsw_ddi_calculate_wrpll(int clock /* in Hz */,

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

942

freq2k = clock / 100;

sys/dev/pci/drm/i915/display/intel_dpll_mgr.c

944

budget = hsw_wrpll_get_budget_for_freq(clock);

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

239

u32 clock; /* in KHz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

251

u32 clock; /* in KHz */

sys/dev/pci/drm/i915/display/intel_dpll_mgr.h

258

u32 clock; /* in kHz */

sys/dev/pci/drm/i915/display/intel_dsi.c

77

if (fixed_mode->clock > max_dotclk)

sys/dev/pci/drm/i915/display/intel_dsi_vbt.c

804

intel_dsi->pclk = mode->clock;

sys/dev/pci/drm/i915/display/intel_dvo.c

229

int target_clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_dvo.c

245

target_clock = fixed_mode->clock;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1875

int clock, bool respect_downstream_limits,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1881

if (clock < 25000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1883

if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1888

if (display->platform.geminilake && clock > 446666 && clock < 480000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1893

clock > 223333 && clock < 240000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1897

if (display->platform.cherryview && clock > 216000 && clock < 240000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1901

if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1905

if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)

sys/dev/pci/drm/i915/display/intel_hdmi.c

1911

int intel_hdmi_tmds_clock(int clock, int bpc,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1916

clock /= 2;

sys/dev/pci/drm/i915/display/intel_hdmi.c

1923

return DIV_ROUND_CLOSEST(clock * bpc, 8);

sys/dev/pci/drm/i915/display/intel_hdmi.c

1975

intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock,

sys/dev/pci/drm/i915/display/intel_hdmi.c

1991

int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2019

int clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2030

clock *= 2;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2032

if (clock > max_dotclk)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2038

clock *= 2;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2047

if (clock > 600000)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2061

status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);

sys/dev/pci/drm/i915/display/intel_hdmi.c

2069

status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2119

int clock, bool respect_downstream_limits)

sys/dev/pci/drm/i915/display/intel_hdmi.c

2139

int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2159

int bpc, clock = adjusted_mode->crtc_clock;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2162

clock *= 2;

sys/dev/pci/drm/i915/display/intel_hdmi.c

2164

bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,

sys/dev/pci/drm/i915/display/intel_hdmi.c

2170

intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);

sys/dev/pci/drm/i915/display/intel_hdmi.h

55

int intel_hdmi_tmds_clock(int clock, int bpc, enum intel_output_format sink_format);

sys/dev/pci/drm/i915/display/intel_lvds.c

411

if (fixed_mode->clock > max_pixclk)

sys/dev/pci/drm/i915/display/intel_lvds.c

808

if (fixed_mode->clock > 112999)

sys/dev/pci/drm/i915/display/intel_panel.c

110

mode->clock != preferred_mode->clock;

sys/dev/pci/drm/i915/display/intel_panel.c

154

if (fixed_mode->clock > best_mode->clock)

sys/dev/pci/drm/i915/display/intel_panel.c

242

DIV_ROUND_CLOSEST(adjusted_mode->clock * 1000,

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

151

static void lpt_compute_iclkip(struct iclkip_params *p, int clock)

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

163

clock << p->auxdiv);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

189

int clock = crtc_state->hw.adjusted_mode.crtc_clock;

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

195

lpt_compute_iclkip(&p, clock);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

196

drm_WARN_ON(display->drm, lpt_iclkip_freq(&p) != clock);

sys/dev/pci/drm/i915/display/intel_pch_refclk.c

206

clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1286

struct dpll *clock = &pipe_config->dpll;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1293

clock->p1 = 2;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1294

clock->p2 = 10;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1295

clock->n = 3;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1296

clock->m1 = 16;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1297

clock->m2 = 8;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1299

clock->p1 = 1;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1300

clock->p2 = 10;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1301

clock->n = 6;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1302

clock->m1 = 12;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1303

clock->m2 = 8;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1947

int clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1953

if (clock > max_dotclk)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1959

clock *= 2;

sys/dev/pci/drm/i915/display/intel_sdvo.c

1962

if (intel_sdvo->pixel_clock_min > clock)

sys/dev/pci/drm/i915/display/intel_sdvo.c

1965

if (intel_sdvo->pixel_clock_max < clock)

sys/dev/pci/drm/i915/display/intel_sdvo.c

793

args.clock = mode->clock / 10;

sys/dev/pci/drm/i915/display/intel_sdvo.c

851

mode_clock = mode->clock;

sys/dev/pci/drm/i915/display/intel_sdvo.c

853

dtd->part1.clock = mode_clock;

sys/dev/pci/drm/i915/display/intel_sdvo.c

909

mode.clock = dtd->part1.clock * 10;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

111

u16 clock;

sys/dev/pci/drm/i915/display/intel_sdvo_regs.h

78

u16 clock; /* pixel clock, in 10kHz units */

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

262

pll_state->clock = pixel_clock;

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1009

.clock = 85500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1039

.clock = 88750,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1069

.clock = 106500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1099

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1129

.clock = 115500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1159

.clock = 119000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1189

.clock = 135000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1219

.clock = 138500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

123

.clock = 270000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1249

.clock = 147160,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1279

.clock = 148352,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1309

.clock = 154000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1339

.clock = 162000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1369

.clock = 209800,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1399

.clock = 262750,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1429

.clock = 267300,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

145

.clock = 540000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1459

.clock = 268500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1489

.clock = 296703,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1519

.clock = 241500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1549

.clock = 319890,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1579

.clock = 497750,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1609

.clock = 592000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1639

.clock = 593407,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

166

.clock = 810000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1669

.clock = 297000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1699

.clock = 594000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

1802

if (crtc_state->port_clock == tables[i]->clock) {

sys/dev/pci/drm/i915/display/intel_snps_phy.c

186

.clock = 1000000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

221

.clock = 1350000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

269

.clock = 216000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

300

.clock = 243000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

331

.clock = 324000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

363

.clock = 432000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

410

.clock = 25175,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

439

.clock = 27000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

468

.clock = 74250,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

498

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

529

.clock = 25200,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

559

.clock = 27027,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

589

.clock = 28320,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

619

.clock = 30240,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

649

.clock = 31500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

679

.clock = 36000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

709

.clock = 40000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

739

.clock = 49500,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

769

.clock = 50000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

799

.clock = 57284,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

829

.clock = 58000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

859

.clock = 65000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

889

.clock = 71000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

919

.clock = 74176,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

949

.clock = 75000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

96

.clock = 162000,

sys/dev/pci/drm/i915/display/intel_snps_phy.c

979

.clock = 78750,

sys/dev/pci/drm/i915/display/intel_tv.c

1065

mode->clock = mode->clock * new_htotal / mode->htotal;

sys/dev/pci/drm/i915/display/intel_tv.c

1082

mode->clock = mode->clock * new_vtotal / mode->vtotal;

sys/dev/pci/drm/i915/display/intel_tv.c

1126

tv_mode.clock = pipe_config->port_clock;

sys/dev/pci/drm/i915/display/intel_tv.c

1163

adjusted_mode->crtc_clock = mode.clock;

sys/dev/pci/drm/i915/display/intel_tv.c

1219

pipe_config->port_clock = tv_mode->clock;

sys/dev/pci/drm/i915/display/intel_tv.c

1260

adjusted_mode->clock /= 2;

sys/dev/pci/drm/i915/display/intel_tv.c

1821

intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);

sys/dev/pci/drm/i915/display/intel_tv.c

319

u32 clock;

sys/dev/pci/drm/i915/display/intel_tv.c

390

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

433

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

475

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

518

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

562

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

607

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

649

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

673

.clock = 108000,

sys/dev/pci/drm/i915/display/intel_tv.c

697

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

721

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

745

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

771

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

798

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

824

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

850

.clock = 148500,

sys/dev/pci/drm/i915/display/intel_tv.c

971

if (mode->clock > max_dotclk)

sys/dev/pci/drm/i915/display/intel_tv.c

993

int clock)

sys/dev/pci/drm/i915/display/intel_tv.c

995

mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);

sys/dev/pci/drm/i915/display/intel_vblank.c

143

u32 clock = mode->crtc_clock;

sys/dev/pci/drm/i915/display/intel_vblank.c

172

clock), 1000 * htotal);

sys/dev/pci/drm/i915/display/intel_vbt_defs.h

56

u16 clock; /**< In 10khz */

sys/dev/pci/drm/i915/display/intel_vdsc.c

1079

int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);

sys/dev/pci/drm/i915/display/skl_watermark.c

2185

crtc_state->hw.adjusted_mode.clock);

sys/dev/pci/drm/i915/display/skl_watermark.c

2220

crtc_state->hw.adjusted_mode.clock);

sys/dev/pci/drm/i915/display/vlv_dsi.c

2003

intel_dsi->pclk, current_mode->clock);

sys/dev/pci/drm/i915/display/vlv_dsi.c

2005

current_mode->clock)) {

sys/dev/pci/drm/i915/display/vlv_dsi.c

2007

intel_dsi->pclk = current_mode->clock;

sys/dev/pci/drm/i915/gvt/handlers.c

555

struct dpll clock = {};

sys/dev/pci/drm/i915/gvt/handlers.c

584

clock.m1 = 2;

sys/dev/pci/drm/i915/gvt/handlers.c

585

clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

588

clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

590

clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

592

clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

594

clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,

sys/dev/pci/drm/i915/gvt/handlers.c

596

clock.m = clock.m1 * clock.m2;

sys/dev/pci/drm/i915/gvt/handlers.c

597

clock.p = clock.p1 * clock.p2 * 5;

sys/dev/pci/drm/i915/gvt/handlers.c

599

if (clock.n == 0 || clock.p == 0) {

sys/dev/pci/drm/i915/gvt/handlers.c

604

clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);

sys/dev/pci/drm/i915/gvt/handlers.c

605

clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);

sys/dev/pci/drm/i915/gvt/handlers.c

607

dp_br = clock.dot;

sys/dev/pci/drm/include/drm/display/drm_dp_mst_helper.h

879

int drm_dp_calc_pbn_mode(int clock, int bpp);

sys/dev/pci/drm/include/drm/drm_modes.h

135

.name = nm, .status = 0, .type = (t), .clock = (c), \

sys/dev/pci/drm/include/drm/drm_modes.h

150

.type = DRM_MODE_TYPE_DRIVER, .clock = (pix), \

sys/dev/pci/drm/include/drm/drm_modes.h

258

int clock; /* in kHz */

sys/dev/pci/drm/include/drm/drm_modes.h

432

(m)->name, drm_mode_vrefresh(m), (m)->clock, \

sys/dev/pci/drm/include/drm/gud.h

82

__le32 clock;

sys/dev/pci/drm/include/uapi/drm/drm_mode.h

243

__u32 clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1019

mode->clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

1032

mode->clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

1040

mode->clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

1060

u32 pll_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1061

u32 clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1070

clock = radeon_crtc->adjusted_clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

1074

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1077

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1082

pll = &rdev->clock.dcpll;

sys/dev/pci/drm/radeon/atombios_crtc.c

1106

encoder_mode, radeon_encoder->encoder_id, clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

1815

if ((crtc->mode.clock == test_crtc->mode.clock) &&

sys/dev/pci/drm/radeon/atombios_crtc.c

1874

if (rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_crtc.c

1922

if (rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_crtc.c

1948

if (rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_crtc.c

1971

if (rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_crtc.c

2024

atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

sys/dev/pci/drm/radeon/atombios_crtc.c

2029

rdev->clock.default_dispclk);

sys/dev/pci/drm/radeon/atombios_crtc.c

2033

atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

sys/dev/pci/drm/radeon/atombios_crtc.c

566

u32 adjusted_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

568

u32 dp_clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

569

u32 clock = mode->clock;

sys/dev/pci/drm/radeon/atombios_crtc.c

571

bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);

sys/dev/pci/drm/radeon/atombios_crtc.c

583

if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */

sys/dev/pci/drm/radeon/atombios_crtc.c

597

if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)

sys/dev/pci/drm/radeon/atombios_crtc.c

602

if (mode->clock > 200000) /* range limits??? */

sys/dev/pci/drm/radeon/atombios_crtc.c

636

adjusted_clock = mode->clock * 2;

sys/dev/pci/drm/radeon/atombios_crtc.c

655

clock = (clock * 5) / 4;

sys/dev/pci/drm/radeon/atombios_crtc.c

658

clock = (clock * 3) / 2;

sys/dev/pci/drm/radeon/atombios_crtc.c

661

clock = clock * 2;

sys/dev/pci/drm/radeon/atombios_crtc.c

687

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

699

args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

820

u32 clock,

sys/dev/pci/drm/radeon/atombios_crtc.c

845

if (clock == ATOM_DISABLE)

sys/dev/pci/drm/radeon/atombios_crtc.c

847

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

857

args.v2.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

867

args.v3.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

884

args.v5.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

913

args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

979

radeon_connector->pixelclock_for_modeset = mode->clock;

sys/dev/pci/drm/radeon/atombios_dp.c

459

mode->clock,

sys/dev/pci/drm/radeon/atombios_dp.c

477

if ((mode->clock > 340000) &&

sys/dev/pci/drm/radeon/atombios_dp.c

486

mode->clock,

sys/dev/pci/drm/radeon/atombios_encoders.c

1209

if (is_dp && rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_encoders.c

1269

if (rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_encoders.c

1336

if (is_dp && rdev->clock.dp_extclk)

sys/dev/pci/drm/radeon/atombios_encoders.c

2217

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/radeon/btc_dpm.c

1147

u32 i, clock = 0;

sys/dev/pci/drm/radeon/btc_dpm.c

1150

*max_clock = clock;

sys/dev/pci/drm/radeon/btc_dpm.c

1155

if (clock < table->entries[i].clk)

sys/dev/pci/drm/radeon/btc_dpm.c

1156

clock = table->entries[i].clk;

sys/dev/pci/drm/radeon/btc_dpm.c

1158

*max_clock = clock;

sys/dev/pci/drm/radeon/btc_dpm.c

1162

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/pci/drm/radeon/btc_dpm.c

1170

if (clock <= table->entries[i].clk) {

sys/dev/pci/drm/radeon/btc_dpm.c

2186

rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc);

sys/dev/pci/drm/radeon/btc_dpm.c

2195

rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc);

sys/dev/pci/drm/radeon/btc_dpm.c

2204

rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc);

sys/dev/pci/drm/radeon/btc_dpm.h

51

u32 clock, u16 max_voltage, u16 *voltage);

sys/dev/pci/drm/radeon/ci_dpm.c

1948

u32 ref_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

2389

u32 clock, u32 *voltage)

sys/dev/pci/drm/radeon/ci_dpm.c

2397

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/radeon/ci_dpm.c

2787

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

2966

table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

3125

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ci_dpm.c

3748

if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)

sys/dev/pci/drm/radeon/cik.c

1707

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/cik.c

9262

(u32)mode->clock);

sys/dev/pci/drm/radeon/cik.c

9264

(u32)mode->clock);

sys/dev/pci/drm/radeon/cik.c

9279

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/cik.c

9319

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/cik.c

9417

uint64_t clock;

sys/dev/pci/drm/radeon/cik.c

9421

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/radeon/cik.c

9424

return clock;

sys/dev/pci/drm/radeon/cik.c

9427

static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/pci/drm/radeon/cik.c

9435

clock, false, &dividers);

sys/dev/pci/drm/radeon/cypress_dpm.c

442

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/cypress_dpm.c

558

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

118

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce3_1_afmt.c

122

unsigned int max_ratio = clock / 24000;

sys/dev/pci/drm/radeon/dce3_1_afmt.c

159

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/pci/drm/radeon/dce3_1_afmt.c

166

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/pci/drm/radeon/dce6_afmt.c

271

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce6_afmt.c

286

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/pci/drm/radeon/dce6_afmt.c

290

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/dce6_afmt.c

312

clock = clock * 100 / div;

sys/dev/pci/drm/radeon/dce6_afmt.c

315

WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/pci/drm/radeon/dce6_afmt.c

318

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/pci/drm/radeon/dce6_afmt.h

48

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/dce6_afmt.h

50

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/evergreen.c

1142

static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/pci/drm/radeon/evergreen.c

1149

clock, false, &dividers);

sys/dev/pci/drm/radeon/evergreen.c

2174

(u32)mode->clock);

sys/dev/pci/drm/radeon/evergreen.c

2176

(u32)mode->clock);

sys/dev/pci/drm/radeon/evergreen.c

2193

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/evergreen.c

2220

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/evergreen.c

2259

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/evergreen.c

2271

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

230

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

232

unsigned int max_ratio = clock / 24000;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

269

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/pci/drm/radeon/evergreen_hdmi.c

273

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/evergreen_hdmi.c

301

clock = 100 * clock / div;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

305

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

60

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/evergreen_hdmi.h

62

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/ni_dpm.c

2012

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/ni_dpm.c

2242

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/ni_dpm.c

3970

pl->mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/ni_dpm.c

3971

pl->sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/ni_dpm.c

883

rdev->clock.current_dispclk,

sys/dev/pci/drm/radeon/r100.c

3292

pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */

sys/dev/pci/drm/radeon/r100.c

3299

pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */

sys/dev/pci/drm/radeon/r600.c

200

return rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/r600.c

227

if (rdev->clock.spll.reference_freq == 10000)

sys/dev/pci/drm/radeon/r600.c

4613

uint64_t clock;

sys/dev/pci/drm/radeon/r600.c

4617

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/radeon/r600.c

4620

return clock;

sys/dev/pci/drm/radeon/r600.h

47

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/r600_dpm.c

165

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/pci/drm/radeon/r600_dpm.c

172

vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;

sys/dev/pci/drm/radeon/r600_dpm.c

191

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/pci/drm/radeon/r600_hdmi.c

294

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/pci/drm/radeon/r600_hdmi.c

310

WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

sys/dev/pci/drm/radeon/r600_hdmi.c

314

WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);

sys/dev/pci/drm/radeon/radeon.h

2403

struct radeon_clock clock;

sys/dev/pci/drm/radeon/radeon.h

2947

u32 clock;

sys/dev/pci/drm/radeon/radeon.h

306

u32 clock,

sys/dev/pci/drm/radeon/radeon.h

310

u32 clock,

sys/dev/pci/drm/radeon/radeon_asic.h

400

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);

sys/dev/pci/drm/radeon/radeon_asic.h

403

void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);

sys/dev/pci/drm/radeon/radeon_atombios.c

1124

rdev->clock.vco_freq =

sys/dev/pci/drm/radeon/radeon_atombios.c

1136

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_atombios.c

1137

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_atombios.c

1138

struct radeon_pll *dcpll = &rdev->clock.dcpll;

sys/dev/pci/drm/radeon/radeon_atombios.c

1139

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_atombios.c

1140

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_atombios.c

1244

rdev->clock.default_sclk =

sys/dev/pci/drm/radeon/radeon_atombios.c

1246

rdev->clock.default_mclk =

sys/dev/pci/drm/radeon/radeon_atombios.c

1250

rdev->clock.default_dispclk =

sys/dev/pci/drm/radeon/radeon_atombios.c

1252

if (rdev->clock.default_dispclk == 0) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1254

rdev->clock.default_dispclk = 60000; /* 600 Mhz */

sys/dev/pci/drm/radeon/radeon_atombios.c

1256

rdev->clock.default_dispclk = 54000; /* 540 Mhz */

sys/dev/pci/drm/radeon/radeon_atombios.c

1258

rdev->clock.default_dispclk = 60000; /* 600 Mhz */

sys/dev/pci/drm/radeon/radeon_atombios.c

1261

if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1263

rdev->clock.default_dispclk / 100);

sys/dev/pci/drm/radeon/radeon_atombios.c

1264

rdev->clock.default_dispclk = 60000;

sys/dev/pci/drm/radeon/radeon_atombios.c

1266

rdev->clock.dp_extclk =

sys/dev/pci/drm/radeon/radeon_atombios.c

1268

rdev->clock.current_dispclk = rdev->clock.default_dispclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

1272

rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);

sys/dev/pci/drm/radeon/radeon_atombios.c

1273

if (rdev->clock.max_pixel_clock == 0)

sys/dev/pci/drm/radeon/radeon_atombios.c

1274

rdev->clock.max_pixel_clock = 40000;

sys/dev/pci/drm/radeon/radeon_atombios.c

1281

rdev->clock.vco_freq =

sys/dev/pci/drm/radeon/radeon_atombios.c

1284

rdev->clock.vco_freq = rdev->clock.current_dispclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

1288

rdev->clock.vco_freq = rdev->clock.current_dispclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

1290

if (rdev->clock.vco_freq == 0)

sys/dev/pci/drm/radeon/radeon_atombios.c

1291

rdev->clock.vco_freq = 360000; /* 3.6 GHz */

sys/dev/pci/drm/radeon/radeon_atombios.c

1511

int id, u32 clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

1545

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1563

(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1585

(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1644

lvds->native_mode.clock =

sys/dev/pci/drm/radeon/radeon_atombios.c

1839

mode->crtc_clock = mode->clock =

sys/dev/pci/drm/radeon/radeon_atombios.c

1883

mode->crtc_clock = mode->clock =

sys/dev/pci/drm/radeon/radeon_atombios.c

2469

rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2471

rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2641

rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2643

rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2737

rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2739

rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2809

rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2810

rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_atombios.c

2845

u32 clock,

sys/dev/pci/drm/radeon/radeon_atombios.c

2863

args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_atombios.c

2877

args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_atombios.c

2892

args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/pci/drm/radeon/radeon_atombios.c

2910

args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/pci/drm/radeon/radeon_atombios.c

2931

args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_atombios.c

2942

args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_atombios.c

2961

u32 clock,

sys/dev/pci/drm/radeon/radeon_atombios.c

2980

args.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_audio.c

440

static void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock)

sys/dev/pci/drm/radeon/radeon_audio.c

447

radeon_encoder->audio->set_dto(rdev, crtc, clock);

sys/dev/pci/drm/radeon/radeon_audio.c

494

static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq)

sys/dev/pci/drm/radeon/radeon_audio.c

501

cts = clock * 1000;

sys/dev/pci/drm/radeon/radeon_audio.c

531

static const struct radeon_hdmi_acr *radeon_audio_acr(unsigned int clock)

sys/dev/pci/drm/radeon/radeon_audio.c

553

if (hdmi_predefined_acr[i].clock == clock)

sys/dev/pci/drm/radeon/radeon_audio.c

557

radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);

sys/dev/pci/drm/radeon/radeon_audio.c

558

radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);

sys/dev/pci/drm/radeon/radeon_audio.c

559

radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);

sys/dev/pci/drm/radeon/radeon_audio.c

567

static void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock)

sys/dev/pci/drm/radeon/radeon_audio.c

569

const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock);

sys/dev/pci/drm/radeon/radeon_audio.c

656

radeon_audio_set_dto(encoder, mode->clock);

sys/dev/pci/drm/radeon/radeon_audio.c

659

radeon_audio_update_acr(encoder, mode->clock);

sys/dev/pci/drm/radeon/radeon_audio.c

694

radeon_audio_set_dto(encoder, rdev->clock.vco_freq * 10);

sys/dev/pci/drm/radeon/radeon_audio.h

55

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/radeon_audio.h

91

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/pci/drm/radeon/radeon_clocks.c

115

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

116

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

117

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_clocks.c

118

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_clocks.c

154

rdev->clock.max_pixel_clock = 35000;

sys/dev/pci/drm/radeon/radeon_clocks.c

163

rdev->clock.default_sclk = (*val) / 10;

sys/dev/pci/drm/radeon/radeon_clocks.c

165

rdev->clock.default_sclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

170

rdev->clock.default_mclk = (*val) / 10;

sys/dev/pci/drm/radeon/radeon_clocks.c

172

rdev->clock.default_mclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

198

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

199

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

200

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_clocks.c

201

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_clocks.c

232

rdev->clock.max_pixel_clock = 35000;

sys/dev/pci/drm/radeon/radeon_clocks.c

240

rdev->clock.default_sclk = (val) / 10;

sys/dev/pci/drm/radeon/radeon_clocks.c

242

rdev->clock.default_sclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

246

rdev->clock.default_mclk = (val) / 10;

sys/dev/pci/drm/radeon/radeon_clocks.c

248

rdev->clock.default_mclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

267

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

268

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_clocks.c

269

struct radeon_pll *dcpll = &rdev->clock.dcpll;

sys/dev/pci/drm/radeon/radeon_clocks.c

270

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_clocks.c

271

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_clocks.c

312

rdev->clock.max_pixel_clock = 35000;

sys/dev/pci/drm/radeon/radeon_clocks.c

355

rdev->clock.default_sclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

357

rdev->clock.default_mclk =

sys/dev/pci/drm/radeon/radeon_clocks.c

424

if (!rdev->clock.default_sclk)

sys/dev/pci/drm/radeon/radeon_clocks.c

425

rdev->clock.default_sclk = radeon_get_engine_clock(rdev);

sys/dev/pci/drm/radeon/radeon_clocks.c

426

if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)

sys/dev/pci/drm/radeon/radeon_clocks.c

427

rdev->clock.default_mclk = radeon_get_memory_clock(rdev);

sys/dev/pci/drm/radeon/radeon_clocks.c

429

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_clocks.c

430

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_clocks.c

439

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_clocks.c

46

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_clocks.c

76

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_combios.c

1270

lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;

sys/dev/pci/drm/radeon/radeon_combios.c

2808

rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_combios.c

2809

rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_combios.c

727

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_combios.c

728

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_combios.c

729

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/pci/drm/radeon/radeon_combios.c

730

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/pci/drm/radeon/radeon_combios.c

793

rdev->clock.default_sclk = sclk;

sys/dev/pci/drm/radeon/radeon_combios.c

794

rdev->clock.default_mclk = mclk;

sys/dev/pci/drm/radeon/radeon_combios.c

797

rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);

sys/dev/pci/drm/radeon/radeon_combios.c

799

rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */

sys/dev/pci/drm/radeon/radeon_connectors.c

1461

(mode->clock > 135000))

sys/dev/pci/drm/radeon/radeon_connectors.c

1464

if (radeon_connector->use_digital && (mode->clock > 165000)) {

sys/dev/pci/drm/radeon/radeon_connectors.c

1471

if (mode->clock > 340000)

sys/dev/pci/drm/radeon/radeon_connectors.c

1481

if ((mode->clock / 10) > rdev->clock.max_pixel_clock)

sys/dev/pci/drm/radeon/radeon_connectors.c

1614

(rdev->clock.default_dispclk >= 53900) &&

sys/dev/pci/drm/radeon/radeon_connectors.c

1767

if (mode->clock > 340000)

sys/dev/pci/drm/radeon/radeon_connectors.c

1770

if (mode->clock > 165000)

sys/dev/pci/drm/radeon/radeon_connectors.c

367

radeon_encoder->native_mode.clock = 0;

sys/dev/pci/drm/radeon/radeon_connectors.c

435

native_mode->clock != 0) {

sys/dev/pci/drm/radeon/radeon_connectors.c

698

(radeon_encoder->native_mode.clock == 0))

sys/dev/pci/drm/radeon/radeon_connectors.c

753

if (!native_mode->clock) {

sys/dev/pci/drm/radeon/radeon_connectors.c

765

if (!native_mode->clock) {

sys/dev/pci/drm/radeon/radeon_connectors.c

978

if ((mode->clock / 10) > rdev->clock.max_pixel_clock)

sys/dev/pci/drm/radeon/radeon_encoders.c

334

adjusted_mode->clock = native_mode->clock;

sys/dev/pci/drm/radeon/radeon_i2c.c

206

static void set_clock(void *i2c_priv, int clock)

sys/dev/pci/drm/radeon/radeon_i2c.c

215

val |= clock ? 0 : rec->en_clk_mask;

sys/dev/pci/drm/radeon/radeon_kms.c

353

*value = rdev->clock.spll.reference_freq * 10;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

774

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

776

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

780

if (mode->clock > 200000) /* range limits??? */

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

818

radeon_compute_pll_legacy(pll, mode->clock,

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

206

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

801

if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

952

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

248

pll = &rdev->clock.p2pll;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

250

pll = &rdev->clock.p1pll;

sys/dev/pci/drm/radeon/radeon_mode.h

770

int id, u32 clock);

sys/dev/pci/drm/radeon/radeon_pm.c

1379

rdev->pm.default_sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1380

rdev->pm.default_mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1381

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1382

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1442

rdev->pm.default_sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1443

rdev->pm.default_mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1444

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/radeon_pm.c

1445

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/radeon_uvd.c

958

unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rs690.c

100

else if (rdev->clock.default_mclk)

sys/dev/pci/drm/radeon/rs690.c

101

rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

sys/dev/pci/drm/radeon/rs690.c

327

a.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/rs690.c

86

else if (rdev->clock.default_mclk) {

sys/dev/pci/drm/radeon/rs690.c

87

rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

sys/dev/pci/drm/radeon/rs780_dpm.c

1013

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/pci/drm/radeon/rs780_dpm.c

782

ps->sclk_low = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/rs780_dpm.c

783

ps->sclk_high = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/rs780_dpm.c

991

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/pci/drm/radeon/rv515.c

975

a.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

139

u32 clock, struct rv6xx_sclk_stepping *step)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

145

clock, false, &dividers);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

154

step->vco_frequency = clock * step->post_divider;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

163

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1866

pl->mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1867

pl->sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

297

u32 clock, u32 index)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

301

rv6xx_convert_clock_to_stepping(rdev, clock, &step);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

428

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

549

u32 clock, enum r600_power_level level)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

551

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

559

if (clock && pi->sclk_ss) {

sys/dev/pci/drm/radeon/rv6xx_dpm.c

560

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {

sys/dev/pci/drm/radeon/rv6xx_dpm.c

598

u32 entry, u32 clock)

sys/dev/pci/drm/radeon/rv6xx_dpm.c

602

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))

sys/dev/pci/drm/radeon/rv6xx_dpm.c

655

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

840

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv730_dpm.c

169

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv730_dpm.c

49

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv740_dpm.c

130

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv740_dpm.c

250

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv770.c

788

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/rv770_dpm.c

2253

pl->mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/rv770_dpm.c

2254

pl->sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/rv770_dpm.c

405

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/rv770_dpm.c

502

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/si.c

1320

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/si.c

2292

(u32)mode->clock);

sys/dev/pci/drm/radeon/si.c

2294

(u32)mode->clock);

sys/dev/pci/drm/radeon/si.c

2315

wm_high.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/si.c

2342

wm_low.disp_clk = mode->clock;

sys/dev/pci/drm/radeon/si.c

2383

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/si.c

2395

b.full = dfixed_const(mode->clock);

sys/dev/pci/drm/radeon/si.c

6967

uint64_t clock;

sys/dev/pci/drm/radeon/si.c

6971

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/radeon/si.c

6974

return clock;

sys/dev/pci/drm/radeon/si_dpm.c

3108

rdev->clock.current_dispclk,

sys/dev/pci/drm/radeon/si_dpm.c

4740

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/pci/drm/radeon/si_dpm.c

4862

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/pci/drm/radeon/si_dpm.c

5105

if (rdev->clock.current_dispclk <=

sys/dev/pci/drm/radeon/si_dpm.c

6735

pl->mclk = rdev->clock.default_mclk;

sys/dev/pci/drm/radeon/si_dpm.c

6736

pl->sclk = rdev->clock.default_sclk;

sys/dev/pci/drm/radeon/trinity_dpm.c

1590

u64 disp_clk = rdev->clock.default_dispclk / 100;

sys/dev/pci/maestro.c

1590

u_int clock = 48000 << 2;

sys/dev/pci/maestro.c

1591

u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;

sys/dev/pci/pciide.c

6755

u_int8_t clock;

sys/dev/pci/pciide.c

6759

clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,

sys/dev/pci/pciide.c

6762

PDC262_U66, clock | PDC262_U66_EN(channel));

sys/dev/pci/pciide.c

6779

u_int8_t clock;

sys/dev/pci/pciide.c

6782

clock = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,

sys/dev/pci/pciide.c

6785

PDC262_U66, clock & ~PDC262_U66_EN(channel));

sys/dev/pci/tga.c

1599

bus_space_handle_t clock;

sys/dev/pci/tga.c

1649

TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */

sys/dev/pci/tga.c

1658

bus_space_write_4(dc->dc_memt, clock, 0, writeval);

sys/dev/pci/tga.c

1659

bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/pci/tga.c

1663

&clock); /* XXX */

sys/dev/pci/tga.c

1664

bus_space_write_4(dc->dc_memt, clock, 0, 0x0);

sys/dev/pci/tga.c

1665

bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);

sys/dev/sbus/magma.c

198

cd1400_compute_baud(speed_t speed, int clock, int *cor, int *bpr)

sys/dev/sbus/magma.c

206

br = ((clock * 1000000) + (co * speed) / 2) / (co * speed);

sys/dev/sbus/spif.c

964

stty_compute_baud(speed_t speed, int clock, u_int8_t *bprlp, u_int8_t *bprhp)

sys/dev/sbus/spif.c

968

rate = (2 * clock) / (16 * speed);

sys/dev/usb/dwc2/dwc2_hcd.c

380

int clock = 60; /* default value */

sys/dev/usb/dwc2/dwc2_hcd.c

387

clock = 60;

sys/dev/usb/dwc2/dwc2_hcd.c

390

clock = 48;

sys/dev/usb/dwc2/dwc2_hcd.c

393

clock = 30;

sys/dev/usb/dwc2/dwc2_hcd.c

396

clock = 60;

sys/dev/usb/dwc2/dwc2_hcd.c

399

clock = 48;

sys/dev/usb/dwc2/dwc2_hcd.c

402

clock = 48;

sys/dev/usb/dwc2/dwc2_hcd.c

405

clock = 48;

sys/dev/usb/dwc2/dwc2_hcd.c

409

return 125 * clock - 1;

sys/dev/usb/dwc2/dwc2_hcd.c

412

return 1000 * clock - 1;

sys/dev/usb/uaudio.c

1033

u = u->clock;

sys/dev/usb/uaudio.c

1064

u = u->clock;

sys/dev/usb/uaudio.c

1337

u->clock = NULL;

sys/dev/usb/uaudio.c

1382

clk, units, &u->clock))

sys/dev/usb/uaudio.c

1410

clk, units, &u->clock))

sys/dev/usb/uaudio.c

2297

u->clock = v;

sys/dev/usb/uaudio.c

2310

if (u->clock == NULL) {

sys/dev/usb/uaudio.c

2314

sc->pclock = u->clock;

sys/dev/usb/uaudio.c

2321

if (u->clock == NULL) {

sys/dev/usb/uaudio.c

2325

sc->rclock = u->clock;

sys/dev/usb/uaudio.c

239

struct uaudio_unit *clock;

sys/dev/usb/uaudio.c

2993

struct uaudio_unit *clock;

sys/dev/usb/uaudio.c

3162

clock = uaudio_clock(dir == AUMODE_PLAY ? sc->pclock : sc->rclock);

sys/dev/usb/uaudio.c

3163

if (clock == NULL) {

sys/dev/usb/uaudio.c

3167

if (!clock->cap_freqctl) {

sys/dev/usb/uaudio.c

3173

sc->ctl_ifnum, clock->id, req_buf, 4)) {

sys/dev/usb/udl.c

1267

uint16_t chip, uint32_t clock)

sys/dev/usb/udl.c

1277

(udl_modes[idx].clock == clock) &&

sys/dev/usb/udl.c

2056

mode.clock =

sys/dev/usb/udl.c

2063

sc->sc_chip, mode.clock);

sys/dev/usb/udl.c

2079

mode.clock =

sys/dev/usb/udl.c

2086

mode.freq, sc->sc_chip, mode.clock);

sys/dev/usb/udl.h

283

uint32_t clock;

sys/kern/tty_endrun.c

406

struct clock_ymdhms clock;

sys/kern/tty_endrun.c

423

clock.dt_year = n;

sys/kern/tty_endrun.c

437

clock.dt_mon = i;

sys/kern/tty_endrun.c

438

clock.dt_day = n;

sys/kern/tty_endrun.c

442

clock.dt_hour = clock.dt_min = clock.dt_sec = 0;

sys/kern/tty_endrun.c

444

secs = clock_ymdhms_to_secs(&clock);

sys/kern/tty_endrun.c

457

struct clock_ymdhms clock;

sys/kern/tty_endrun.c

469

clock.dt_hour = n;

sys/kern/tty_endrun.c

472

clock.dt_min = n;

sys/kern/tty_endrun.c

475

clock.dt_sec = n;

sys/kern/tty_endrun.c

477

DPRINTFN(1, ("hh:mm:ss %d:%d:%d\n", (int)clock.dt_hour,

sys/kern/tty_endrun.c

478

(int)clock.dt_min,

sys/kern/tty_endrun.c

479

(int)clock.dt_sec));

sys/kern/tty_endrun.c

480

secs = clock.dt_hour * 3600

sys/kern/tty_endrun.c

481

+ clock.dt_min * 60

sys/kern/tty_endrun.c

482

+ clock.dt_sec;

sys/lib/libsa/ctime.c

34

ctime(const time_t *clock)

sys/lib/libsa/ctime.c

48

time_t tt = *clock;

usr.bin/signify/zsig.c

248

time_t clock;

usr.bin/signify/zsig.c

267

clock = 0;

usr.bin/signify/zsig.c

269

time(&clock);

usr.bin/signify/zsig.c

271

strftime(date, sizeof date, "%Y-%m-%dT%H:%M:%SZ", gmtime(&clock));

usr.bin/ts/ts.c

108

clock_gettime(clock, &start);

usr.bin/ts/ts.c

114

clock_gettime(clock, &now);

usr.bin/ts/ts.c

53

clockid_t clock = CLOCK_REALTIME;

usr.bin/ts/ts.c

65

clock = CLOCK_MONOTONIC;

usr.bin/ts/ts.c

69

clock = CLOCK_MONOTONIC;

usr.bin/ts/ts.c

74

clock = CLOCK_MONOTONIC;

usr.sbin/inetd/inetd.c

1623

time_t clock;

usr.sbin/inetd/inetd.c

1625

clock = time(NULL);

usr.sbin/inetd/inetd.c

1627

(void) snprintf(buffer, sizeof buffer, "%.24s\r\n", ctime(&clock));

usr.sbin/inetd/inetd.c

1636

time_t clock;

usr.sbin/inetd/inetd.c

1640

clock = time(NULL);

usr.sbin/inetd/inetd.c

1648

(void) snprintf(buffer, sizeof buffer, "%.24s\r\n", ctime(&clock));

usr.sbin/mtree/create.c

76

time_t clock;

usr.sbin/mtree/create.c

80

(void)time(&clock);

usr.sbin/mtree/create.c

84

getlogin(), host, fullpath, ctime(&clock));

usr.sbin/nsd/tsig.c

400

time_t clock;

usr.sbin/nsd/tsig.c

402

clock = (time_t) current_time;

usr.sbin/nsd/tsig.c

403

ctime_r(&clock, current_time_text);

usr.sbin/nsd/tsig.c

406

clock = (time_t) signed_time;

usr.sbin/nsd/tsig.c

407

ctime_r(&clock, signed_time_text);

usr.sbin/unbound/sldns/parseutil.c

147

sldns_gmtime64_r(int64_t clock, struct tm *result)

usr.sbin/unbound/sldns/parseutil.c

150

result->tm_sec = (int) LDNS_MOD(clock, 60);

usr.sbin/unbound/sldns/parseutil.c

151

clock = LDNS_DIV(clock, 60);

usr.sbin/unbound/sldns/parseutil.c

152

result->tm_min = (int) LDNS_MOD(clock, 60);

usr.sbin/unbound/sldns/parseutil.c

153

clock = LDNS_DIV(clock, 60);

usr.sbin/unbound/sldns/parseutil.c

154

result->tm_hour = (int) LDNS_MOD(clock, 24);

usr.sbin/unbound/sldns/parseutil.c

155

clock = LDNS_DIV(clock, 24);

usr.sbin/unbound/sldns/parseutil.c

157

sldns_year_and_yday_from_days_since_epoch(clock, result);