sys/arch/arm64/dev/aplaudio.c

106

uint32_t fmt, pol, clk;

sys/arch/arm64/dev/aplaudio.c

157

clk = DAI_CLOCK_CFM | DAI_CLOCK_CBM;

sys/arch/arm64/dev/aplaudio.c

158

aplaudio_set_format(sc, fmt, pol, clk);

sys/arch/arm64/dev/aplaudio.c

169

uint32_t clk)

sys/arch/arm64/dev/aplaudio.c

176

fmt, pol, clk);

sys/arch/arm64/dev/aplaudio.c

182

dai->dd_set_format(dai->dd_cookie, fmt, pol, clk);

sys/arch/arm64/dev/aplmca.c

372

uint32_t clk)

sys/arch/arm64/dev/aplmca.c

399

if (!(clk & DAI_CLOCK_CBM) || !(clk & DAI_CLOCK_CFM))

sys/arch/arm64/dev/rpiclock.c

410

rpiclock_freq(struct rpiclock_softc *sc, const struct rpiclock *clk,

sys/arch/arm64/dev/rpiclock.c

414

uint32_t idx = clk->parents[mux];

sys/arch/arm64/dev/rpiclock.c

427

const struct rpiclock *clk;

sys/arch/arm64/dev/rpiclock.c

451

clk = rpiclock_lookup(idx);

sys/arch/arm64/dev/rpiclock.c

452

if (clk == NULL) {

sys/arch/arm64/dev/rpiclock.c

457

if (clk->sel_reg) {

sys/arch/arm64/dev/rpiclock.c

458

sel = HREAD4(sc, clk->sel_reg);

sys/arch/arm64/dev/rpiclock.c

461

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

465

if (parent >= nitems(clk->parents))

sys/arch/arm64/dev/rpiclock.c

467

parent = clk->parents[parent];

sys/arch/arm64/dev/rpiclock.c

472

div = HREAD4(sc, clk->div_int_reg);

sys/arch/arm64/dev/rpiclock.c

483

const struct rpiclock *clk;

sys/arch/arm64/dev/rpiclock.c

513

clk = rpiclock_lookup(idx);

sys/arch/arm64/dev/rpiclock.c

514

if (clk == NULL) {

sys/arch/arm64/dev/rpiclock.c

524

if (clk->sel_reg) {

sys/arch/arm64/dev/rpiclock.c

525

sel = HREAD4(sc, clk->sel_reg);

sys/arch/arm64/dev/rpiclock.c

528

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

537

for (i = 0; i < nitems(clk->parents); i++) {

sys/arch/arm64/dev/rpiclock.c

538

if (clk->parents[i] == 0)

sys/arch/arm64/dev/rpiclock.c

540

f = rpiclock_freq(sc, clk, i, freq);

sys/arch/arm64/dev/rpiclock.c

548

ctrl = HREAD4(sc, clk->ctrl_reg);

sys/arch/arm64/dev/rpiclock.c

549

if (clk->sel_reg) {

sys/arch/arm64/dev/rpiclock.c

558

HWRITE4(sc, clk->ctrl_reg, ctrl);

sys/arch/arm64/dev/rpiclock.c

560

parent = clk->parents[best_mux];

sys/arch/arm64/dev/rpiclock.c

563

HWRITE4(sc, clk->div_int_reg, div);

sys/arch/arm64/dev/rpiclock.c

572

const struct rpiclock *clk;

sys/arch/arm64/dev/rpiclock.c

575

clk = rpiclock_lookup(idx);

sys/arch/arm64/dev/rpiclock.c

576

if (clk == NULL) {

sys/arch/arm64/dev/rpiclock.c

582

HSET4(sc, clk->ctrl_reg, CLK_CTRL_ENABLE);

sys/arch/arm64/dev/rpiclock.c

584

HCLR4(sc, clk->ctrl_reg, CLK_CTRL_ENABLE);

sys/arch/armv7/omap/prcm.c

531

prcm_v4_hsusbhost_set_source(int clk, int clksrc)

sys/arch/armv7/omap/prcm.c

538

if (clk == PRCM_USBP1_PHY)

sys/arch/armv7/omap/prcm.c

540

else if (clk != PRCM_USBP2_PHY)

sys/arch/macppc/dev/zs.c

277

xcs->cs_clocks[0].clk = PCLK;

sys/arch/macppc/dev/zs.c

286

xcs->cs_clocks[1].clk = 0;

sys/arch/macppc/dev/zs.c

287

xcs->cs_clocks[2].clk = 0;

sys/arch/macppc/dev/zs.c

298

xcs->cs_clocks[1].clk = 0;

sys/arch/macppc/dev/zs.c

299

xcs->cs_clocks[2].clk = 0;

sys/arch/macppc/dev/zs.c

301

if (xcs->cs_clocks[1].clk)

sys/arch/macppc/dev/zs.c

303

if (xcs->cs_clocks[2].clk)

sys/arch/macppc/dev/zs.c

567

if (xcs->cs_clocks[i].clk <= 0)

sys/arch/macppc/dev/zs.c

571

tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps);

sys/arch/macppc/dev/zs.c

573

rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1);

sys/arch/macppc/dev/zs.c

590

int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps);

sys/arch/macppc/dev/zs.c

637

cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;

sys/arch/macppc/include/z8530var.h

52

long clk; /* clock rate, in MHz, present on signal line */

sys/arch/octeon/dev/octdwctwo.c

144

uint64_t clk;

sys/arch/octeon/dev/octdwctwo.c

168

clk = bus_space_read_8(sc->sc_bust, sc->sc_regh, USBN_CLK_CTL_OFFSET);

sys/arch/octeon/dev/octdwctwo.c

169

clk |= USBN_CLK_CTL_POR;

sys/arch/octeon/dev/octdwctwo.c

170

clk &= ~(USBN_CLK_CTL_HRST | USBN_CLK_CTL_PRST | USBN_CLK_CTL_HCLK_RST |

sys/arch/octeon/dev/octdwctwo.c

172

clk |= SET_USBN_CLK_CTL_DIVIDE(0x4ULL)

sys/arch/octeon/dev/octdwctwo.c

175

bus_space_write_8(sc->sc_bust, sc->sc_regh, USBN_CLK_CTL_OFFSET, clk);

sys/arch/octeon/dev/octdwctwo.c

234

uint64_t clk;

sys/arch/octeon/dev/octdwctwo.c

246

clk = bus_space_read_8(sc->sc_bust, sc->sc_regh,

sys/arch/octeon/dev/octdwctwo.c

248

clk |= USBN_CLK_CTL_POR;

sys/arch/octeon/dev/octdwctwo.c

249

clk |= USBN_CLK_CTL_HCLK_RST;

sys/arch/octeon/dev/octdwctwo.c

250

clk |= USBN_CLK_CTL_ENABLE;

sys/arch/octeon/dev/octdwctwo.c

251

clk &= ~USBN_CLK_CTL_HRST;

sys/arch/octeon/dev/octdwctwo.c

252

clk &= ~USBN_CLK_CTL_PRST;

sys/arch/octeon/dev/octdwctwo.c

254

USBN_CLK_CTL_OFFSET, clk);

sys/arch/sparc64/dev/pcfiic_ebus.c

108

int clk = getpropint(findroot(), "clock-frequency", 0);

sys/arch/sparc64/dev/pcfiic_ebus.c

110

if (clk < 105000000)

sys/arch/sparc64/dev/pcfiic_ebus.c

112

else if (clk < 160000000)

sys/arch/sparc64/sparc64/cpu.c

238

u_int clk;

sys/arch/sparc64/sparc64/cpu.c

264

clk = getpropint(node, "clock-frequency", 0);

sys/arch/sparc64/sparc64/cpu.c

265

if (clk == 0) {

sys/arch/sparc64/sparc64/cpu.c

269

clk = getpropint(findroot(), "clock-frequency", 0);

sys/arch/sparc64/sparc64/cpu.c

271

if (clk) {

sys/arch/sparc64/sparc64/cpu.c

272

cpu_clockrate[0] = clk; /* Tell OS what frequency we run on */

sys/arch/sparc64/sparc64/cpu.c

273

cpu_clockrate[1] = clk/1000000;

sys/arch/sparc64/sparc64/cpu.c

276

ma->ma_name, vers >> 4, vers & 0xf, clockfreq(clk));

sys/dev/fdt/es8316ac.c

261

uint32_t clk)

sys/dev/fdt/es8316ac.c

269

if (clk != (DAI_CLOCK_CBS|DAI_CLOCK_CFS))

sys/dev/fdt/graphaudio.c

117

uint32_t fmt, pol, clk;

sys/dev/fdt/graphaudio.c

175

clk = 0;

sys/dev/fdt/graphaudio.c

177

clk |= DAI_CLOCK_CFM;

sys/dev/fdt/graphaudio.c

179

clk |= DAI_CLOCK_CFS;

sys/dev/fdt/graphaudio.c

181

clk |= DAI_CLOCK_CBM;

sys/dev/fdt/graphaudio.c

183

clk |= DAI_CLOCK_CBS;

sys/dev/fdt/graphaudio.c

185

graphaudio_set_format(sc, fmt, pol, clk);

sys/dev/fdt/graphaudio.c

192

uint32_t clk)

sys/dev/fdt/graphaudio.c

196

fmt, pol, clk);

sys/dev/fdt/graphaudio.c

199

fmt, pol, clk);

sys/dev/fdt/if_dwqe_fdt.c

818

uint32_t iface, clk;

sys/dev/fdt/if_dwqe_fdt.c

836

clk = RK3588_RMII_MODE_GMACx_RGMII(fsc->sc_gmac_id);

sys/dev/fdt/if_dwqe_fdt.c

846

clk = RK3588_RMII_MODE_GMACx_RMII(fsc->sc_gmac_id);

sys/dev/fdt/if_dwqe_fdt.c

874

regmap_write_4(php_rm, RK3588_PHP_GRF_CLK_CON1, clk);

sys/dev/fdt/rkclock.c

1469

const struct rkclock *clk;

sys/dev/fdt/rkclock.c

1472

clk = rkclock_lookup(sc, RK3308_CLK_RTC32K);

sys/dev/fdt/rkclock.c

1473

vpll0_freq = rkclock_freq(sc, clk, 0, freq);

sys/dev/fdt/rkclock.c

1474

vpll1_freq = rkclock_freq(sc, clk, 1, freq);

sys/dev/fdt/rkclock.c

1484

div_con = rkclock_div_con(sc, clk, mux, freq);

sys/dev/fdt/rkclock.c

507

const struct rkclock *clk;

sys/dev/fdt/rkclock.c

509

for (clk = sc->sc_clocks; clk->idx; clk++) {

sys/dev/fdt/rkclock.c

510

if (clk->idx == idx)

sys/dev/fdt/rkclock.c

511

return clk;

sys/dev/fdt/rkclock.c

544

rkclock_div_con(struct rkclock_softc *sc, const struct rkclock *clk,

sys/dev/fdt/rkclock.c

548

uint32_t idx = clk->parents[mux];

sys/dev/fdt/rkclock.c

551

max_div_con = clk->div_mask >> (ffs(clk->div_mask) - 1);

sys/dev/fdt/rkclock.c

560

rkclock_freq(struct rkclock_softc *sc, const struct rkclock *clk,

sys/dev/fdt/rkclock.c

564

uint32_t idx = clk->parents[mux];

sys/dev/fdt/rkclock.c

567

div_con = rkclock_div_con(sc, clk, mux, freq);

sys/dev/fdt/rkclock.c

574

const struct rkclock *clk;

sys/dev/fdt/rkclock.c

578

clk = rkclock_lookup(sc, idx);

sys/dev/fdt/rkclock.c

579

if (clk == NULL) {

sys/dev/fdt/rkclock.c

584

reg = HREAD4(sc, clk->reg);

sys/dev/fdt/rkclock.c

585

shift = ffs(clk->sel_mask) - 1;

sys/dev/fdt/rkclock.c

589

mux = (reg & clk->sel_mask) >> shift;

sys/dev/fdt/rkclock.c

590

shift = ffs(clk->div_mask) - 1;

sys/dev/fdt/rkclock.c

594

div_con = (reg & clk->div_mask) >> shift;

sys/dev/fdt/rkclock.c

596

if (clk->parents[mux] == 0) {

sys/dev/fdt/rkclock.c

600

idx = clk->parents[mux];

sys/dev/fdt/rkclock.c

607

const struct rkclock *clk;

sys/dev/fdt/rkclock.c

613

clk = rkclock_lookup(sc, idx);

sys/dev/fdt/rkclock.c

614

if (clk == NULL) {

sys/dev/fdt/rkclock.c

620

reg = HREAD4(sc, clk->reg);

sys/dev/fdt/rkclock.c

621

sel_shift = ffs(clk->sel_mask) - 1;

sys/dev/fdt/rkclock.c

625

mux = (reg & clk->sel_mask) >> sel_shift;

sys/dev/fdt/rkclock.c

627

if (clk->parents[mux] == 0) {

sys/dev/fdt/rkclock.c

633

if (clk->flags & SET_PARENT) {

sys/dev/fdt/rkclock.c

634

parent = clk->parents[mux];

sys/dev/fdt/rkclock.c

636

if (clk->div_mask == 0)

sys/dev/fdt/rkclock.c

644

if (clk->div_mask == 0) {

sys/dev/fdt/rkclock.c

649

parent = clk->parents[mux];

sys/dev/fdt/rkclock.c

653

for (i = 0; i < nitems(clk->parents); i++) {

sys/dev/fdt/rkclock.c

654

if (clk->parents[i] == 0)

sys/dev/fdt/rkclock.c

656

parent = clk->parents[i];

sys/dev/fdt/rkclock.c

665

HWRITE4(sc, clk->reg,

sys/dev/fdt/rkclock.c

666

clk->sel_mask << 16 | best_mux << sel_shift);

sys/dev/fdt/rkclock.c

674

best_freq = rkclock_freq(sc, clk, mux, freq);

sys/dev/fdt/rkclock.c

681

if ((clk->flags & FIXED_PARENT) == 0) {

sys/dev/fdt/rkclock.c

682

for (i = 0; i < nitems(clk->parents); i++) {

sys/dev/fdt/rkclock.c

683

if (clk->parents[i] == 0)

sys/dev/fdt/rkclock.c

685

f = rkclock_freq(sc, clk, i, freq);

sys/dev/fdt/rkclock.c

694

div_con = rkclock_div_con(sc, clk, best_mux, freq);

sys/dev/fdt/rkclock.c

695

div_shift = ffs(clk->div_mask) - 1;

sys/dev/fdt/rkclock.c

696

HWRITE4(sc, clk->reg,

sys/dev/fdt/rkclock.c

697

clk->sel_mask << 16 | best_mux << sel_shift |

sys/dev/fdt/rkclock.c

698

clk->div_mask << 16 | div_con << div_shift);

sys/dev/fdt/rkclock.c

705

const struct rkclock *clk;

sys/dev/fdt/rkclock.c

709

clk = rkclock_lookup(sc, idx);

sys/dev/fdt/rkclock.c

710

if (clk == NULL || clk->sel_mask == 0) {

sys/dev/fdt/rkclock.c

715

for (mux = 0; mux < nitems(clk->parents); mux++) {

sys/dev/fdt/rkclock.c

716

if (clk->parents[mux] == parent)

sys/dev/fdt/rkclock.c

719

if (mux == nitems(clk->parents) || parent == 0) {

sys/dev/fdt/rkclock.c

724

shift = ffs(clk->sel_mask) - 1;

sys/dev/fdt/rkclock.c

725

HWRITE4(sc, clk->reg, clk->sel_mask << 16 | mux << shift);

sys/dev/fdt/rkiis.c

341

uint32_t clk)

sys/dev/fdt/rkiis.c

395

switch (clk) {

sys/dev/fdt/simpleaudio.c

121

uint32_t fmt, pol, clk;

sys/dev/fdt/simpleaudio.c

176

clk = 0;

sys/dev/fdt/simpleaudio.c

178

clk |= DAI_CLOCK_CFM;

sys/dev/fdt/simpleaudio.c

180

clk |= DAI_CLOCK_CFS;

sys/dev/fdt/simpleaudio.c

182

clk |= DAI_CLOCK_CBM;

sys/dev/fdt/simpleaudio.c

184

clk |= DAI_CLOCK_CBS;

sys/dev/fdt/simpleaudio.c

205

simpleaudio_set_format(sc, fmt, pol, clk);

sys/dev/fdt/simpleaudio.c

212

uint32_t clk)

sys/dev/fdt/simpleaudio.c

216

fmt, pol, clk);

sys/dev/fdt/simpleaudio.c

219

fmt, pol, clk);

sys/dev/fdt/sncodec.c

193

uint32_t clk)

sys/dev/fdt/sncodec.c

228

if (!(clk & DAI_CLOCK_CBM) || !(clk & DAI_CLOCK_CFM))

sys/dev/fdt/tascodec.c

180

uint32_t clk)

sys/dev/fdt/tascodec.c

215

if (!(clk & DAI_CLOCK_CBM) || !(clk & DAI_CLOCK_CFM))

sys/dev/ic/bcm2835_vcprop.h

211

struct vcprop_clock clk[VCPROP_MAXCLOCKS];

sys/dev/ic/cissreg.h

127

u_int8_t clk[4]; /* unaligned dumbness */

sys/dev/ic/pluartvar.h

60

struct clk *sc_clk;

sys/dev/ic/w83l518d_sdmmc.c

284

uint8_t clk;

sys/dev/ic/w83l518d_sdmmc.c

289

clk = WB_CLK_24M;

sys/dev/ic/w83l518d_sdmmc.c

291

clk = WB_CLK_16M;

sys/dev/ic/w83l518d_sdmmc.c

293

clk = WB_CLK_12M;

sys/dev/ic/w83l518d_sdmmc.c

295

clk = WB_CLK_375K;

sys/dev/ic/w83l518d_sdmmc.c

297

if (wb_idx_read(wb, WB_INDEX_CLK) != clk)

sys/dev/ic/w83l518d_sdmmc.c

298

wb_idx_write(wb, WB_INDEX_CLK, clk);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1329

dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1330

dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1332

dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

491

TP_PROTO(const struct dc_clocks *clk),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

492

TP_ARGS(clk),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

514

__entry->dispclk_khz = clk->dispclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

515

__entry->dppclk_khz = clk->dppclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

516

__entry->dcfclk_khz = clk->dcfclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

517

__entry->socclk_khz = clk->socclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

518

__entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

519

__entry->fclk_khz = clk->fclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

520

__entry->phyclk_khz = clk->phyclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

521

__entry->dramclk_khz = clk->dramclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

522

__entry->p_state_change_support = clk->p_state_change_support;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

523

__entry->prev_p_state_change_support = clk->prev_p_state_change_support;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

524

__entry->pwr_state = clk->pwr_state;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

525

__entry->prev_p_state_change_support = clk->prev_p_state_change_support;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

526

__entry->dtm_level = clk->dtm_level;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

527

__entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

528

__entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

529

__entry->bw_dppclk_khz = clk->bw_dppclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

530

__entry->bw_dispclk_khz = clk->bw_dispclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

560

TP_PROTO(const struct dce_bw_output *clk),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

561

TP_ARGS(clk),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

576

__entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

577

__entry->cpup_state_change_enable = clk->cpup_state_change_enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

578

__entry->stutter_mode_enable = clk->stutter_mode_enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

579

__entry->nbp_state_change_enable = clk->nbp_state_change_enable;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

580

__entry->all_displays_in_sync = clk->all_displays_in_sync;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

581

__entry->sclk_khz = clk->sclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

582

__entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

583

__entry->yclk_khz = clk->yclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

584

__entry->dispclk_khz = clk->dispclk_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

585

__entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1051

SET_PIXEL_CLOCK_PS_ALLOCATION_V5 clk;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1055

memset(&clk, 0, sizeof(clk));

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1060

clk.sPCLKInput.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1061

clk.sPCLKInput.ucPpll = (uint8_t)pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1062

clk.sPCLKInput.ucRefDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1064

clk.sPCLKInput.usFbDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1066

clk.sPCLKInput.ulFbDivDecFrac =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1068

clk.sPCLKInput.ucPostDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1070

clk.sPCLKInput.ucTransmitterID =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1074

clk.sPCLKInput.ucEncoderMode =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1079

clk.sPCLKInput.usPixelClock =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1083

clk.sPCLKInput.ucMiscInfo |=

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1087

clk.sPCLKInput.ucMiscInfo |=

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1099

clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1103

clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1109

if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1121

SET_PIXEL_CLOCK_PS_ALLOCATION_V6 clk;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1125

memset(&clk, 0, sizeof(clk));

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1149

clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1150

clk.sPCLKInput.ucPpll = (uint8_t) pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1151

clk.sPCLKInput.ucRefDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1153

clk.sPCLKInput.usFbDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1155

clk.sPCLKInput.ulFbDivDecFrac =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1157

clk.sPCLKInput.ucPostDiv =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1159

clk.sPCLKInput.ucTransmitterID =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1163

clk.sPCLKInput.ucEncoderMode =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1168

clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1172

clk.sPCLKInput.ucMiscInfo |=

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1177

clk.sPCLKInput.ucMiscInfo |=

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1189

clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1192

clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1195

clk.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1201

if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1213

PIXEL_CLOCK_PARAMETERS_V7 clk;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1217

memset(&clk, 0, sizeof(clk));

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1240

clk.ucCRTC = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1241

clk.ucPpll = (uint8_t) pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1242

clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1243

clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1245

clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1247

clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1250

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1253

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1256

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1259

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1262

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1265

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1268

clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1270

if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

463

struct set_pixel_clock_parameter_v1_7 *clk)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

474

cmd.set_pixel_clock.pixel_clock.clk = *clk;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

484

struct set_pixel_clock_parameter_v1_7 clk;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

488

memset(&clk, 0, sizeof(clk));

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

512

clk.crtc_id = controller_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

513

clk.pll_id = (uint8_t) pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

514

clk.encoderobjid =

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

519

clk.encoder_mode = (uint8_t) bp->

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

523

clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

525

clk.deep_color_ratio =

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

536

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

539

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

542

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

545

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

548

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

551

clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

555

set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

559

if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

194

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

221

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

349

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

456

clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

459

clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

462

clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

465

clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

89

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

136

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

198

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

81

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

85

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

97

*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

212

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

217

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

219

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

230

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

235

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

237

smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

261

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

266

uint32_t param = (clk << 16) | dpm_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

268

smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

279

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

284

uint32_t param = clk << 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

286

smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

41

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

42

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

43

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

44

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

100

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

140

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

243

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

279

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

392

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

131

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

230

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

141

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

238

if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

132

static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

138

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

150

*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

626

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

729

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

227

uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

237

if (clk == PPCLK_DISPCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

239

if (clk == PPCLK_DPPCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

241

if (clk == PPCLK_DCFCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

243

if (clk == PPCLK_DTBCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

245

if (clk == PPCLK_UCLK)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

281

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

287

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

289

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

295

hard_min_done = dcn32_smu_wait_get_hard_min_status(clk_mgr, clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

43

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1234

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

344

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

383

struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

120

static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1229

&context->bw_ctx.bw.dcn.clk,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1238

&context->bw_ctx.bw.dcn.clk,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

124

switch (clk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1245

dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1342

new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1343

new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1344

new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1364

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1371

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

159

static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

165

uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

177

*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

590

static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

592

if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

605

int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

608

actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

75

static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

79

switch (clk) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

301

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

307

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

309

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

315

hard_min_done = dcn401_smu_wait_hard_min_status(clk_mgr, clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

439

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

444

uint32_t param = (clk << 16) | dpm_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

446

smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

457

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

462

uint32_t param = clk << 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

464

smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

23

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

38

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

39

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2297

TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2559

TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);

sys/dev/pci/drm/amd/display/dc/core/dc.c

3052

if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))

sys/dev/pci/drm/amd/display/dc/core/dc.c

3055

} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {

sys/dev/pci/drm/amd/display/dc/core/dc.c

5795

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6281

profile.power_level = !context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

191

context->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

192

context->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

193

context->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

194

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

195

context->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

196

context->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

199

context->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

200

context->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

201

context->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

202

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

203

context->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/core/dc_debug.c

204

context->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

649

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

478

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

479

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

480

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

481

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

482

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

483

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1157

context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1160

context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1162

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1163

context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1165

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1167

context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1169

if (context->bw_ctx.bw.dcn.clk.dispclk_khz <

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1171

context->bw_ctx.bw.dcn.clk.dispclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1175

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1177

context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1180

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1184

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1188

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1192

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1153

context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1154

context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1155

context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1156

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1158

if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1159

context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1161

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1162

context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1163

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1170

context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1172

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1174

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1176

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1177

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1198

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1199

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1213

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1216

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1217

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1218

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1219

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1241

context->bw_ctx.bw.dcn.clk.p_state_change_support,

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1249

context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2102

full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2106

context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2115

dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2118

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

295

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

318

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

329

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

332

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

423

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

498

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&

sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

518

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

502

context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

561

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

565

context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

566

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

567

context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

568

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

569

context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

570

context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

571

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1659

context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1660

context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1661

context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1662

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1663

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1664

context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1665

context->bw_ctx.bw.dcn.clk.p_state_change_support =

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1672

context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1674

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1675

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1676

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1678

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1680

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1685

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1686

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1724

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1725

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1768

context->bw_ctx.bw.dcn.clk.socclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1769

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1770

context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1771

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1772

context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1773

context->bw_ctx.bw.dcn.clk.fclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1774

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1775

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1778

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1779

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1780

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1782

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1785

context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2355

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2372

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2375

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2407

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2504

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2523

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3603

if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3610

context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;

sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

619

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

638

context->bw_ctx.bw.dcn.clk.zstate_support = support;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

807

context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

808

context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

809

context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

810

context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.active.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

811

context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

812

context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.idle.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

813

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.deepsleep_dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

814

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming->fclk_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

815

context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

816

context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz > 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

817

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

818

context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

819

context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

820

context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

821

context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

822

context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

231

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

232

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

510

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

151

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

152

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

154

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

157

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

161

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

164

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

169

context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

171

context->bw_ctx.bw.dcn.clk.num_ways = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

98

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

184

context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

185

context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

186

context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

187

context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

188

context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

189

context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

190

context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

191

context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

285

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

286

context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

289

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

291

context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

293

if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

294

context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

336

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

337

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

361

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

362

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

364

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

366

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

370

context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

371

context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

419

context->bw_ctx.bw.dcn.clk.dtbclk_en = false;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

477

context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1776

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1777

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3021

if (context->bw_ctx.bw.dcn.clk.dispclk_khz <

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3026

context->bw_ctx.bw.dcn.clk.dppclk_khz <=

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3343

context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3381

context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4058

struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

741

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

742

dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

743

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

744

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

745

dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

746

dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

747

dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2450

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2457

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2460

context->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2470

if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1169

dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1190

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1192

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1197

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1791

bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1795

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1797

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1802

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1807

if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1810

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1814

context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

751

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1374

bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1380

context->bw_ctx.bw.dcn.clk.p_state_change_support = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1385

context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1421

if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1424

context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1454

context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1465

if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1650

dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

56

struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

561

struct dc_clocks clk;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

927

unsigned int clk;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

939

clk = 300000;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

942

eng_clks.data[i].clocks_in_khz = clk;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

943

clk += 100000;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

972

clk = 250000;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

976

mem_clks.data[i].clocks_in_khz = clk;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

978

clk += 500000;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1977

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1814

return !context->bw_ctx.bw.dcn.clk.p_state_change_support;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1760

context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2019

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

533

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

778

if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

779

context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1758

int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2538

struct set_pixel_clock_parameter_v1_7 clk; /**< payload */

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

117

u32 clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1043

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1047

(u8)kv_get_clk_bypass(adev, table->entries[i].clk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1050

table->entries[i].clk, false, &dividers);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1105

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1109

table->entries[i].clk, false, &dividers);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1159

if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1161

else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1163

else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1165

else if (kv_get_clock_difference(table->entries[i].clk, 20000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1167

else if (kv_get_clock_difference(table->entries[i].clk, 10000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1774

if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1782

if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1788

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

1789

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2227

if (stable_p_state_sclk >= table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2228

stable_p_state_sclk = table->entries[i].clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2234

stable_p_state_sclk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2257

ps->levels[i].sclk = table->entries[limit].clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2423

kv_set_divider_value(adev, i, table->entries[i].clk);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

797

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

866

static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

872

if (kv_get_clock_difference(clk, 40000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

874

else if (kv_get_clock_difference(clk, 30000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

876

else if (kv_get_clock_difference(clk, 20000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

878

else if (kv_get_clock_difference(clk, 15000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

880

else if (kv_get_clock_difference(clk, 10000) < 200)

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

173

amdgpu_table->entries[i].clk = le16_to_cpu(entry->usClockLow) |

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

492

adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

546

adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3277

if (clock < table->entries[i].clk)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3278

clock = table->entries[i].clk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

3292

if (clock <= table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

5698

adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7453

adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7455

adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7457

adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7459

adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

162

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_smc.c

164

if (!(rst & RST_REG) && !(clk & CK_DISABLE))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

32

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

759

cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

335

table->values[i] = (uint32_t)dep_record->clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

392

mclk_table_record->clk = le32_to_cpu(mclk_dep_record->ulMclk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

434

sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

463

sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

393

dep_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

419

clock_table->values[i] = (unsigned long)table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1011

mclk_table->entries[low].clk/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1016

mclk_table->entries[high].clk/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1069

mclk_table->entries[i].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1070

((mclk_table->entries[i].clk / 100)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1122

level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1126

data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1209

if (pclk_vol_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1211

pclk_vol_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1214

pclk_vol_table->entries[i].clk) :

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1263

if (pclk_vol_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1264

clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

145

table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

147

table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

149

table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

151

table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

153

table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

155

table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

157

table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

159

table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

483

ptable->entries[i].clk = pclk_dependency_table->Freq * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

786

(data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) :

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

792

data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

805

data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

809

data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

862

return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

865

data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

188

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1525

if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1526

hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1531

hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1534

vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1542

if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1543

hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1548

hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1551

vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2074

if (sclk_table->entries[j].clk == sclk &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2108

if (sclk_table->entries[j].clk == sclk &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2471

allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2473

allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2867

allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2869

allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3197

if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3212

if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3367

table_info->vdd_dep_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3369

table_info->vdd_dep_on_sclk->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3375

stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3712

if (dep_mclk_table->entries[0].clk !=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3860

if (dep_mclk_table->entries[0].clk !=

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5187

clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5192

clocks->clock[i] = sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5199

static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5203

if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5205

else if (clk >= MEM_FREQ_HIGH_LATENCY)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5224

clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5226

dep_mclk_table->entries[i].clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5232

clocks->clock[i] = mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5266

if (dep_sclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5268

dep_sclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5289

if (dep_mclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5291

dep_mclk_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5293

dep_mclk_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5296

smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5352

if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5353

dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5354

dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5355

dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5456

uint32_t clk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5469

if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5470

hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5477

if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5478

hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5546

podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

808

allowed_vdd_sclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

810

allowed_vdd_sclk_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

822

allowed_vdd_mclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

824

allowed_vdd_mclk_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

901

dep_sclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

904

dep_sclk_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

912

hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

918

dep_mclk_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

920

dep_mclk_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

928

hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1033

hwmgr->pstate_sclk = table->entries[0].clk / 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1036

hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

110

if (clock <= table->entries[i].clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

118

if (clock >= table->entries[i].clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1193

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1194

data->sclk_dpm.hard_min_clk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1199

clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1201

clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1402

smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1539

info->level = table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1586

i, sclk_table->entries[i].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1673

clocks->clock[i] = table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1701

clocks->engine_max_clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1703

clocks->engine_max_clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1758

sclk = table->entries[sclk_index].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

265

table->sclk = dep_table->entries[dep_table->count-1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

288

table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

290

table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

292

table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

294

table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

296

table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

298

table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

300

table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

302

table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

482

(i < vddc_table->count) ? vddc_table->entries[i].clk : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

564

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

565

data->sclk_dpm.hard_min_clk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

570

clock = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

572

clock = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

703

data->sclk_dpm.soft_min_clk = table->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

707

data->sclk_dpm.soft_max_clk = table->entries[level].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

709

data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

483

*sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

507

table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

513

table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

519

table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

525

table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

561

if (dal_power_level == table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

700

dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1250

dep_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1252

dep_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1640

if (dep_on_sclk->entries[i].clk == gfx_clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1695

if (dep_on_soc->entries[i].clk >= soc_clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1701

if (dep_on_soc->entries[i].clk == soc_clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1844

if (dep_on_mclk->entries[i].clk == mem_clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1930

uint16_t clk = 0, vddc = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1955

clk = (uint16_t)(dep_table->entries[i].clk / 100);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1960

cpu_to_le16(clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1967

cpu_to_le16(clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3033

hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3034

hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3036

hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3037

hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3040

hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3041

hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3347

table_info->vdd_dep_on_sclk->entries[count].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3349

table_info->vdd_dep_on_sclk->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3355

stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

347

od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

349

od_table[2]->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3496

dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3502

dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4089

if(mclk_table->entries[i].clk >= frequency)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4415

if (dep_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4417

dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4436

if (dep_table->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4439

dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4441

dep_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4460

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4476

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4536

clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4792

i, podn_vdd_dep->entries[i].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4803

i, podn_vdd_dep->entries[i].clk/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4934

i, podn_vdd_dep->entries[i].clk / 100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4944

i, podn_vdd_dep->entries[i].clk/100,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5420

uint32_t clk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5434

if (golden_table->dpm_levels[0].value > clk ||

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5435

hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5443

if (golden_table->dpm_levels[0].value > clk ||

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5444

hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

548

*socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5558

dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5561

(dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5562

podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5563

dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5567

dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5570

podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5573

if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5574

podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5576

podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5577

podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5579

podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5647

podn_vdd_dep_table->entries[input_level].clk = input_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

580

if (socclk_table->entries[j].clk == sclk &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

795

allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

797

allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

586

clk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

620

mclk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

654

clk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

669

clk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

715

clk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

768

clk_table->entries[i].clk =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

774

clk_table->entries[i].clk = 90000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

864

table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

614

uint32_t i, num_of_levels, clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

624

ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

628

dpm_table->dpm_levels[i].value = clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

553

PPCLK_e clk_id, uint32_t index, uint32_t *clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

560

clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

572

uint32_t i, num_of_levels, clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

582

ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

586

dpm_table->dpm_levels[i].value = clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

98

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1360

if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1863

if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1873

if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

287

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1282

if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1641

if (table_info->vdd_dep_on_sclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1650

if (table_info->vdd_dep_on_mclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1704

(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1705

(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1707

(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1708

(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

368

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1405

if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1829

if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1839

if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

518

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1263

if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1628

if (table_info->vdd_dep_on_sclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1637

if (table_info->vdd_dep_on_mclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1675

volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1676

(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1677

volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1678

(2522480 - sclk_table->entries[i].clk/100 * 115764/100));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1680

volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1681

(2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1682

volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1683

(3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

369

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1154

if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1625

(sclk_table->entries[i].clk/100) / 10000) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1626

(8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1628

(sclk_table->entries[i].clk/100) / 100000) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1629

(6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1632

(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1633

(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1635

(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1636

(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

261

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1096

if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1412

if (table_info->vdd_dep_on_sclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1421

if (table_info->vdd_dep_on_mclk->entries[level].clk >=

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1512

volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1514

(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1515

volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1517

(2522480 - sclk_table->entries[i].clk/100 * 115764/100));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

616

if (dep_table->entries[i].clk >= clock) {

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3416

static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3423

return smu_set_min_dcef_deep_sleep(smu, clk);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

462

static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

467

if (clk == SMU_MCLK) {

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

470

} else if (clk == SMU_FCLK) {

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

477

} else if (clk == SMU_SOCCLK) {

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1165

int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1599

#define CLK_MAP(clk, index) \

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1600

[SMU_##clk] = {1, (index)}

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

202

int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2034

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2049

&clk);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2055

single_dpm_table->dpm_levels[i].value = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2059

single_dpm_table->min = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2061

single_dpm_table->max = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

675

int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

680

SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1916

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1941

&clk);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1947

single_dpm_table->dpm_levels[i].value = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1951

single_dpm_table->min = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1953

single_dpm_table->max = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1529

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1552

&clk);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1558

single_dpm_table->dpm_levels[i].value = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1562

single_dpm_table->min = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1564

single_dpm_table->max = clk;

sys/dev/pci/drm/amd/pm/swsmu/smu_internal.h

44

#define smu_set_min_dcef_deep_sleep(smu, clk) smu_ppt_funcs(set_min_dcef_deep_sleep, 0, smu, clk)

sys/dev/pci/drm/apple/dcp-internal.h

132

struct clk *clk;

sys/dev/pci/drm/apple/dcp.c

869

dcp->clk = devm_clk_get(dev, NULL);

sys/dev/pci/drm/apple/dcp.c

870

if (IS_ERR(dcp->clk))

sys/dev/pci/drm/apple/dcp.c

871

return dev_err_probe(dev, PTR_ERR(dcp->clk),

sys/dev/pci/drm/apple/dcp.c

924

devm_clk_put(dev, dcp->clk);

sys/dev/pci/drm/apple/dcp.c

925

dcp->clk = NULL;

sys/dev/pci/drm/apple/iomfb_template.c

453

return clk_get_rate(dcp->clk);

sys/dev/pci/drm/display/drm_dp_helper.c

1669

int clk;

sys/dev/pci/drm/display/drm_dp_helper.c

1723

clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);

sys/dev/pci/drm/display/drm_dp_helper.c

1724

if (clk > 0)

sys/dev/pci/drm/display/drm_dp_helper.c

1725

seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);

sys/dev/pci/drm/display/drm_dp_helper.c

1727

clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);

sys/dev/pci/drm/display/drm_dp_helper.c

1728

if (clk > 0)

sys/dev/pci/drm/display/drm_dp_helper.c

1729

seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);

sys/dev/pci/drm/display/drm_dp_helper.c

1731

clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);

sys/dev/pci/drm/display/drm_dp_helper.c

1732

if (clk > 0)

sys/dev/pci/drm/display/drm_dp_helper.c

1733

seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);

sys/dev/pci/drm/drm_linux.c

3688

struct clk *

sys/dev/pci/drm/drm_linux.c

3692

struct clk *clk;

sys/dev/pci/drm/drm_linux.c

3694

clk = malloc(sizeof(*clk), M_DEVBUF, M_WAITOK);

sys/dev/pci/drm/drm_linux.c

3695

clk->freq = clock_get_frequency(pdev->node, name);

sys/dev/pci/drm/drm_linux.c

3696

return clk;

sys/dev/pci/drm/drm_linux.c

3700

clk_get_rate(struct clk *clk)

sys/dev/pci/drm/drm_linux.c

3702

return clk->freq;

sys/dev/pci/drm/i915/display/intel_bw.c

158

points[i].clk = val & 0xff;

sys/dev/pci/drm/i915/display/intel_bw.c

363

i, qi->psf_points[i].clk);

sys/dev/pci/drm/i915/display/intel_bw.c

369

static int adl_calc_psf_bw(int clk)

sys/dev/pci/drm/i915/display/intel_bw.c

376

return DIV_ROUND_CLOSEST(64 * clk * 100, 6);

sys/dev/pci/drm/i915/display/intel_bw.c

631

bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);

sys/dev/pci/drm/i915/display/intel_bw.c

67

u8 clk; /* clock in multiples of 16.6666 MHz */

sys/dev/pci/drm/i915/display/intel_display_regs.h

2554

#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1373

u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1375

total += intel_gt_clock_interval_to_ns(gt, clk);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1458

u64 clk = guc->timestamp.gt_stamp - stats->start_gt_clk;

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

1460

stats->total_gt_clks += clk;

sys/dev/pci/drm/include/linux/clk.h

10

unsigned long clk_get_rate(struct clk *);

sys/dev/pci/drm/include/linux/clk.h

11

struct clk *devm_clk_get(struct device *, const char *);

sys/dev/pci/drm/radeon/btc_dpm.c

1155

if (clock < table->entries[i].clk)

sys/dev/pci/drm/radeon/btc_dpm.c

1156

clock = table->entries[i].clk;

sys/dev/pci/drm/radeon/btc_dpm.c

1170

if (clock <= table->entries[i].clk) {

sys/dev/pci/drm/radeon/btc_dpm.c

2563

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;

sys/dev/pci/drm/radeon/btc_dpm.c

2565

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;

sys/dev/pci/drm/radeon/btc_dpm.c

2567

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;

sys/dev/pci/drm/radeon/btc_dpm.c

2569

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;

sys/dev/pci/drm/radeon/ci_dpm.c

2271

if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {

sys/dev/pci/drm/radeon/ci_dpm.c

2397

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/pci/drm/radeon/ci_dpm.c

2550

if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=

sys/dev/pci/drm/radeon/ci_dpm.c

2558

if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=

sys/dev/pci/drm/radeon/ci_dpm.c

2692

rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

2724

rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

3437

allowed_sclk_vddc_table->entries[i].clk)) {

sys/dev/pci/drm/radeon/ci_dpm.c

3439

allowed_sclk_vddc_table->entries[i].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

3450

allowed_mclk_table->entries[i].clk)) {

sys/dev/pci/drm/radeon/ci_dpm.c

3452

allowed_mclk_table->entries[i].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

3748

if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)

sys/dev/pci/drm/radeon/ci_dpm.c

4893

allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

4895

allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;

sys/dev/pci/drm/radeon/ci_dpm.c

5752

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;

sys/dev/pci/drm/radeon/ci_dpm.c

5754

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;

sys/dev/pci/drm/radeon/ci_dpm.c

5756

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;

sys/dev/pci/drm/radeon/ci_dpm.c

5758

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;

sys/dev/pci/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/ci_smc.c

160

if (!(clk & CK_DISABLE) && (0x20100 <= pc_c))

sys/dev/pci/drm/radeon/kv_dpm.c

1374

if (table->entries[i].clk >= 0) /* XXX */

sys/dev/pci/drm/radeon/kv_dpm.c

1536

if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||

sys/dev/pci/drm/radeon/kv_dpm.c

1544

if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)

sys/dev/pci/drm/radeon/kv_dpm.c

1550

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/pci/drm/radeon/kv_dpm.c

1551

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/pci/drm/radeon/kv_dpm.c

1965

if (stable_p_state_sclk >= table->entries[i].clk) {

sys/dev/pci/drm/radeon/kv_dpm.c

1966

stable_p_state_sclk = table->entries[i].clk;

sys/dev/pci/drm/radeon/kv_dpm.c

1972

stable_p_state_sclk = table->entries[0].clk;

sys/dev/pci/drm/radeon/kv_dpm.c

1995

ps->levels[i].sclk = table->entries[limit].clk;

sys/dev/pci/drm/radeon/kv_dpm.c

2161

kv_set_divider_value(rdev, i, table->entries[i].clk);

sys/dev/pci/drm/radeon/kv_dpm.c

565

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/pci/drm/radeon/kv_dpm.c

634

static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)

sys/dev/pci/drm/radeon/kv_dpm.c

640

if (kv_get_clock_difference(clk, 40000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

642

else if (kv_get_clock_difference(clk, 30000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

644

else if (kv_get_clock_difference(clk, 20000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

646

else if (kv_get_clock_difference(clk, 15000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

648

else if (kv_get_clock_difference(clk, 10000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

811

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/pci/drm/radeon/kv_dpm.c

815

(u8)kv_get_clk_bypass(rdev, table->entries[i].clk);

sys/dev/pci/drm/radeon/kv_dpm.c

818

table->entries[i].clk, false, &dividers);

sys/dev/pci/drm/radeon/kv_dpm.c

873

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/pci/drm/radeon/kv_dpm.c

877

table->entries[i].clk, false, &dividers);

sys/dev/pci/drm/radeon/kv_dpm.c

927

if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

929

else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

931

else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

933

else if (kv_get_clock_difference(table->entries[i].clk, 20000) < 200)

sys/dev/pci/drm/radeon/kv_dpm.c

935

else if (kv_get_clock_difference(table->entries[i].clk, 10000) < 200)

sys/dev/pci/drm/radeon/ni_dpm.c

4089

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;

sys/dev/pci/drm/radeon/ni_dpm.c

4091

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;

sys/dev/pci/drm/radeon/ni_dpm.c

4093

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;

sys/dev/pci/drm/radeon/ni_dpm.c

4095

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;

sys/dev/pci/drm/radeon/r600_dpm.c

1187

rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =

sys/dev/pci/drm/radeon/r600_dpm.c

1245

rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =

sys/dev/pci/drm/radeon/r600_dpm.c

832

radeon_table->entries[i].clk = le16_to_cpu(entry->usClockLow) |

sys/dev/pci/drm/radeon/radeon.h

1394

u32 clk;

sys/dev/pci/drm/radeon/radeon_atombios.c

3338

cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);

sys/dev/pci/drm/radeon/radeon_combios.c

641

u8 id, blocks, clk, data;

sys/dev/pci/drm/radeon/radeon_combios.c

652

clk = RBIOS8(offset + 3 + (i * 5) + 3);

sys/dev/pci/drm/radeon/radeon_combios.c

656

(1 << clk), (1 << data));

sys/dev/pci/drm/radeon/si_dpm.c

5106

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {

sys/dev/pci/drm/radeon/si_dpm.c

6912

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;

sys/dev/pci/drm/radeon/si_dpm.c

6914

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;

sys/dev/pci/drm/radeon/si_dpm.c

6916

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;

sys/dev/pci/drm/radeon/si_dpm.c

6918

rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;

sys/dev/pci/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/pci/drm/radeon/si_smc.c

166

if (!(rst & RST_REG) && !(clk & CK_DISABLE))

sys/dev/pci/envy.c

372

int clk, dout, csmask, cs;

sys/dev/pci/envy.c

378

clk = 0x20;

sys/dev/pci/envy.c

383

clk = 0x2;

sys/dev/pci/envy.c

397

reg &= ~(clk | dout);

sys/dev/pci/envy.c

402

reg |= clk;

sys/dev/pci/eso.c

646

int mode, r[2], rd[2], ar[2], clk;

sys/dev/pci/eso.c

692

clk = ABS(ar[0]) > ABS(ar[1]) ? 1 : 0;

sys/dev/pci/eso.c

693

srg = rd[clk] | (clk == 1 ? ESO_CLK1_SELECT : 0x00);

sys/dev/pci/eso.c

696

fltdiv = 256 - 200279L / r[clk];

sys/dev/pci/eso.c

699

p->sample_rate = r[clk];

sys/dev/pci/if_alc.c

220

uint32_t clk, v;

sys/dev/pci/if_alc.c

224

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

226

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

228

MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));

sys/dev/pci/if_alc.c

285

uint32_t clk, v;

sys/dev/pci/if_alc.c

289

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

291

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

294

MDIO_SUP_PREAMBLE | clk);

sys/dev/pci/if_alc.c

372

uint32_t clk, v;

sys/dev/pci/if_alc.c

378

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

380

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

382

MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);

sys/dev/pci/if_alc.c

402

uint32_t clk, v;

sys/dev/pci/if_alc.c

408

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

410

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

413

MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);

sys/dev/sdmmc/if_bwfm_sdio.c

352

uint32_t clk, reg;

sys/dev/sdmmc/if_bwfm_sdio.c

437

clk = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_CHIPCLKCSR);

sys/dev/sdmmc/if_bwfm_sdio.c

439

clk | BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HT);

sys/dev/sdmmc/if_bwfm_sdio.c

463

bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_CHIPCLKCSR, clk);

sys/dev/usb/uaudio.c

1317

unsigned int i, j, size, ctl, type, subtype, assoc, clk;

sys/dev/usb/uaudio.c

1379

if (!uaudio_getnum(&p, 1, &clk))

sys/dev/usb/uaudio.c

1382

clk, units, &u->clock))

sys/dev/usb/uaudio.c

1407

if (!uaudio_getnum(&p, 1, &clk))

sys/dev/usb/uaudio.c

1410

clk, units, &u->clock))

sys/dev/usb/uchcom.c

641

uint32_t clk = 12000000;

sys/dev/usb/uchcom.c

646

clk /= 2;

sys/dev/usb/uchcom.c

649

clk /= 16;

sys/dev/usb/uchcom.c

652

clk /= 128;

sys/dev/usb/uchcom.c

655

clk = 11719;

sys/dev/usb/uchcom.c

662

*factor = 256 - clk / rate;

sys/dev/usb/umcs.c

402

uint8_t clk, data;

sys/dev/usb/umcs.c

405

if (umcs_calc_baudrate(rate, &div, &clk))

sys/dev/usb/umcs.c

409

rate, clk, div);

sys/dev/usb/umcs.c

415

if (umcs_set_reg(sc, spreg, data | clk))

sys/dev/usb/umcs.c

443

umcs_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk)

sys/dev/usb/umcs.c

456

*clk = i << UMCS_SPx_CLK_SHIFT;

sys/dev/videomode/videomode.c

23

#define M(nm,hr,vr,clk,hs,he,ht,vs,ve,vt,f) \

sys/dev/videomode/videomode.c

24

{ clk, hr, hs, he, ht, vr, vs, ve, vt, f, nm }