banks
struct banks *b;
struct banks bank[NBANKS];
struct aca_banks *banks, struct ras_query_context *qctx)
ret = aca_banks_add_bank(banks, &bank);
static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,
if (!mgr || !banks)
if (list_empty(&mgr->list) || list_empty(&banks->list))
list_for_each_entry(node, &banks->list, node) {
static void aca_banks_init(struct aca_banks *banks)
if (!banks)
struct aca_banks *banks,
if (!banks || !count) {
list_for_each_entry(node, &banks->list, node) {
memset(banks, 0, sizeof(*banks));
INIT_LIST_HEAD(&banks->list);
if (amdgpu_cper_generate_ce_records(adev, banks, count))
struct aca_banks banks;
static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank)
aca_banks_init(&banks);
ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks, qctx);
if (list_empty(&banks.list)) {
ret = aca_dispatch_banks(&aca->mgr, &banks, type,
aca_banks_generate_cper(adev, type, &banks, count);
aca_banks_release(&banks);
list_add_tail(&node->node, &banks->list);
banks->nr_banks++;
static void aca_banks_release(struct aca_banks *banks)
if (list_empty(&banks->list))
list_for_each_entry_safe(node, tmp, &banks->list, node) {
banks->nr_banks--;
struct aca_banks *banks,
list_for_each_entry(node, &banks->list, node) {
list_for_each_entry(node, &banks->list, node) {
struct aca_banks *banks,
struct ice_bank_info *banks = &hw->flash.banks;
offset = banks->nvm_ptr;
size = banks->nvm_size;
active_bank = banks->nvm_bank;
offset = banks->orom_ptr;
size = banks->orom_size;
active_bank = banks->orom_bank;
offset = banks->netlist_ptr;
size = banks->netlist_size;
active_bank = banks->netlist_bank;
struct ice_bank_info *banks = &hw->flash.banks;
banks->nvm_bank = ICE_1ST_FLASH_BANK;
banks->nvm_bank = ICE_2ND_FLASH_BANK;
banks->orom_bank = ICE_1ST_FLASH_BANK;
banks->orom_bank = ICE_2ND_FLASH_BANK;
banks->netlist_bank = ICE_1ST_FLASH_BANK;
banks->netlist_bank = ICE_2ND_FLASH_BANK;
status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
&banks->netlist_size);
uint32_t orom_size_word = hw->flash.banks.orom_size / 2;
hw->flash.banks.orom_size);
orom_data = (uint8_t *)ice_calloc(hw, hw->flash.banks.orom_size,
orom_data, hw->flash.banks.orom_size);
for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size;
struct ice_bank_info banks; /* Flash Bank information */
struct ixgbe_bank_info *banks = &hw->flash.banks;
offset = banks->nvm_ptr;
size = banks->nvm_size;
active_bank = banks->nvm_bank;
offset = banks->orom_ptr;
size = banks->orom_size;
active_bank = banks->orom_bank;
offset = banks->netlist_ptr;
size = banks->netlist_size;
active_bank = banks->netlist_bank;
struct ixgbe_bank_info *banks = &hw->flash.banks;
banks->nvm_bank = IXGBE_1ST_FLASH_BANK;
banks->nvm_bank = IXGBE_2ND_FLASH_BANK;
banks->orom_bank = IXGBE_1ST_FLASH_BANK;
banks->orom_bank = IXGBE_2ND_FLASH_BANK;
banks->netlist_bank = IXGBE_1ST_FLASH_BANK;
banks->netlist_bank = IXGBE_2ND_FLASH_BANK;
&banks->nvm_ptr);
&banks->nvm_size);
&banks->orom_ptr);
&banks->orom_size);
&banks->netlist_ptr);
&banks->netlist_size);
struct ixgbe_bank_info banks; /* Flash Bank information */