sys/dev/pci/drm/i915/display/intel_dpio_phy.c

362

if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

420

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);

sys/dev/pci/drm/i915/display/intel_dpio_phy.c

485

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);

sys/dev/pci/drm/i915/display/vlv_dsi.c

755

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);

sys/dev/pci/drm/i915/display/vlv_dsi.c

913

intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);

sys/dev/pci/drm/i915/gvt/display.c

246

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

sys/dev/pci/drm/i915/gvt/display.c

280

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);

sys/dev/pci/drm/i915/gvt/display.c

310

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

sys/dev/pci/drm/i915/gvt/display.c

341

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

sys/dev/pci/drm/i915/gvt/handlers.c

2780

MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);

sys/dev/pci/drm/i915/gvt/mmio.c

265

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

1138

MMIO_D(BXT_P_CR_GT_DISP_PWRON);