_reg_write_4
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
_reg_write_4(SH4_BCR4, BSC_BCR4_VAL);
_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
_reg_write_4(SH4_MCR, BSC_MCR_VAL);
_reg_write_4(TCOR, 0xffffffff);
_reg_write_4(TCNT, 0xffffffff);
_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
_reg_write_4(SH4_PCICR, PCICR_BASE);
_reg_write_4(SH4_PCICONF2,
_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR0, 0xac000000);
_reg_write_4(SH4_PCICONF5, 0xac000000);
_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR1, 0xac000000);
_reg_write_4(SH4_PCICONF6, 0x8c000000);
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
_reg_write_4(SH4_PCIPAR, tag | reg);
_reg_write_4(SH4_PCIPAR, 0);
_reg_write_4(SH4_PCIPAR, tag | reg);
_reg_write_4(SH4_PCIPDR, data);
_reg_write_4(SH4_PCIPAR, 0);
_reg_write_4(cca, va & CCA_TAGADDR_MASK);
_reg_write_4(SH4_CCR, SH4_CCR_ICI|SH4_CCR_OCI);
_reg_write_4(SH4_CCR, r);
_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
_reg_write_4(SH_(TCNT ## x), 0xffffffff); \
_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
_reg_write_4(SH_(TCOR1), 0xffffffff);
_reg_write_4(SH_(TCOR2), 0xffffffff);
_reg_write_4(SH_(BARA), 0); /* break address */
_reg_write_4(SH3_CCR,
_reg_write_4(SH4_CCR,
_reg_write_4(SH4_CCR,
_reg_write_4(iprreg, r);
_reg_write_4(iprreg, bit);
_reg_write_4(iprreg, bit);
_reg_write_4(SH_(TCNT1), 0);
_reg_write_4(SH4_INTPRI00, 0);
_reg_write_4(SH4_INTMSK00, INTMSK00_MASK_ALL);
_reg_write_4(SH_(BARB), nproc->p_md.md_regs->tf_spc);
_reg_write_4(SH_(PTEH), asid);
_reg_write_4(SH3_MMUAA | a, 0);
_reg_write_4(SH3_MMUDA | a, 0);
_reg_write_4(SH3_PTEH, (va & ~PGOFSET) | asid);
_reg_write_4(SH3_PTEL, pte & PG_HW_BITS);
_reg_write_4(SH3_PTEH, oasid);
_reg_write_4(SH3_MMUCR, SH3_MMUCR_AT | SH3_MMUCR_TF);
_reg_write_4(SH3_MMUAA | a, 0);
_reg_write_4(SH3_MMUAA | a, 0);
_reg_write_4(a, 0);
_reg_write_4(a, 0);
_reg_write_4(a, 0);
_reg_write_4(SH4_ITLB_DA1, 0);
_reg_write_4(SH4_ITLB_DA1 | (1 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_DA1 | (2 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_DA1 | (3 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_PTEH, asid);
_reg_write_4(SH4_PTEH, (va & ~PGOFSET) | asid);
_reg_write_4(SH4_PTEA,
_reg_write_4(SH4_PTEA, 0);
_reg_write_4(SH4_PTEL, ptel);
_reg_write_4(SH4_PTEH, oasid);
_reg_write_4(SH4_ITLB_AA, 0);
_reg_write_4(SH4_ITLB_AA | (1 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_AA | (2 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_AA | (3 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_MMUCR, 0); /* zero wired entry */
_reg_write_4(SH4_MMUCR, SH4_MMUCR_AT | SH4_MMUCR_TI | SH4_MMUCR_SQMD |
_reg_write_4(SH4_PTEH, asid);
_reg_write_4(SH4_UTLB_AA | SH4_UTLB_A, va); /* Clear D, V */
_reg_write_4(SH4_PTEH, pteh);
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);