sys/arch/landisk/landisk/intr.c

78

evtcode = _reg_read_4(SH4_INTEVT);

sys/arch/landisk/stand/boot/delay.c

116

return ~(_reg_read_4(TCNT));

sys/arch/sh/dev/shpcic.c

164

_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);

sys/arch/sh/dev/shpcic.c

180

_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);

sys/arch/sh/dev/shpcic.c

199

_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));

sys/arch/sh/dev/shpcic.c

204

_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));

sys/arch/sh/dev/shpcic.c

209

_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));

sys/arch/sh/dev/shpcic.c

214

_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));

sys/arch/sh/dev/shpcic.c

328

data = _reg_read_4(SH4_PCIPDR);

sys/arch/sh/dev/shpcic.c

90

id = _reg_read_4(SH4_PCICONF0);

sys/arch/sh/sh/cache_sh3.c

80

r = _reg_read_4(SH3_CCR);

sys/arch/sh/sh/cache_sh4.c

125

r = _reg_read_4(SH4_CCR);

sys/arch/sh/sh/clock.c

109

(0xffffffff - _reg_read_4(SH_(TCNT ## x)))

sys/arch/sh/sh/clock.c

211

return 0xffffffff - _reg_read_4(SH_(TCNT2));

sys/arch/sh/sh/db_interface.c

229

r = _reg_read_4(SH3_MMUCR);

sys/arch/sh/sh/db_interface.c

234

i = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;

sys/arch/sh/sh/db_interface.c

246

r = _reg_read_4(SH3_MMUAA | a);

sys/arch/sh/sh/db_interface.c

259

r = _reg_read_4(SH3_MMUDA | a);

sys/arch/sh/sh/db_interface.c

278

r = _reg_read_4(SH4_MMUCR);

sys/arch/sh/sh/db_interface.c

285

i = _reg_read_4(SH4_PTEH) & SH4_PTEH_ASID_MASK;

sys/arch/sh/sh/db_interface.c

293

r = _reg_read_4(SH4_ITLB_AA | e);

sys/arch/sh/sh/db_interface.c

298

r = _reg_read_4(SH4_ITLB_DA1 | e);

sys/arch/sh/sh/db_interface.c

309

r = _reg_read_4(SH4_ITLB_DA2 | e);

sys/arch/sh/sh/db_interface.c

323

r = _reg_read_4(SH4_UTLB_AA | e);

sys/arch/sh/sh/db_interface.c

328

r = _reg_read_4(SH4_UTLB_DA1 | e);

sys/arch/sh/sh/db_interface.c

342

r = _reg_read_4(SH4_UTLB_DA2 | e);

sys/arch/sh/sh/db_interface.c

425

_reg_read_4(SH3_CCR) & ~SH3_CCR_CE);

sys/arch/sh/sh/db_interface.c

444

r = _reg_read_4(cca | (way << sh_cache_way_shift));

sys/arch/sh/sh/db_interface.c

470

_reg_read_4(SH4_CCR) & ~(SH4_CCR_ICE | SH4_CCR_OCE));

sys/arch/sh/sh/db_interface.c

485

r = _reg_read_4(SH4_CCIA | (i << CCIA_ENTRY_SHIFT));

sys/arch/sh/sh/db_interface.c

495

r = _reg_read_4(SH4_CCDA | e);

sys/arch/sh/sh/db_interface.c

503

_reg_read_4(SH4_CCR) | SH4_CCR_ICE | SH4_CCR_OCE);

sys/arch/sh/sh/interrupt.c

400

printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));

sys/arch/sh/sh/interrupt.c

402

printf(" INTEVT2=0x%x", _reg_read_4(SH7709_INTEVT2));

sys/arch/sh/sh/interrupt.c

465

r = _reg_read_4(iprreg);

sys/arch/sh/sh/mmu.c

81

r = _reg_read_4(SH3_MMUCR);

sys/arch/sh/sh/mmu.c

91

r = _reg_read_4(SH4_MMUCR);

sys/arch/sh/sh/mmu_sh3.c

116

oasid = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;

sys/arch/sh/sh/mmu_sh3.c

64

if ((_reg_read_4(SH3_MMUAA | a) &

sys/arch/sh/sh/mmu_sh3.c

83

if ((_reg_read_4(SH3_MMUAA | a) &

sys/arch/sh/sh/mmu_sh4.c

108

if ((_reg_read_4(a) & SH4_UTLB_AA_ASID_MASK) == asid)

sys/arch/sh/sh/mmu_sh4.c

125

a = _reg_read_4(SH4_MMUCR) & SH4_MMUCR_URB_MASK;

sys/arch/sh/sh/mmu_sh4.c

155

oasid = _reg_read_4(SH4_PTEH) & SH4_PTEH_ASID_MASK;

sys/arch/sh/sh/mmu_sh4.c

83

pteh = _reg_read_4(SH4_PTEH);

sys/arch/sh/sh/trap.c

158

int tra = _reg_read_4(SH_(TRA));