sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2460

[I915_EXEC_BSD] = VCS0,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

175

case VCS0:

sys/dev/pci/drm/i915/gt/intel_engine.h

99

ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

134

[VCS0] = {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1709

[VCS0] = MSG_IDLE_VCS0,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

412

[VCS0] = GEN11_GRDOM_MEDIA,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

437

[VCS0] = GEN6_GRDOM_MEDIA,

sys/dev/pci/drm/i915/gt/intel_engine_user.c

213

[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3504

[VCS0] = GEN8_VCS0_IRQ_SHIFT,

sys/dev/pci/drm/i915/gt/intel_mocs.c

570

[VCS0] = __GEN9_VCS0_MOCS0,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

101

case VCS0:

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

290

return __ENGINE_INSTANCES_MASK(mask, VCS0, I915_MAX_VCS);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1165

[VCS0] = {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

429

#define R_VCS1 BIT(VCS0)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

611

[VCS0] = {

sys/dev/pci/drm/i915/gvt/execlist.c

51

[VCS0] = VCS_AS_CONTEXT_SWITCH,

sys/dev/pci/drm/i915/gvt/handlers.c

2107

id = VCS0;

sys/dev/pci/drm/i915/gvt/handlers.c

344

engine_mask |= BIT(VCS0);

sys/dev/pci/drm/i915/gvt/mmio_context.c

170

[VCS0] = 0xc900,

sys/dev/pci/drm/i915/gvt/mmio_context.c

357

[VCS0] = 0x4264,

sys/dev/pci/drm/i915/gvt/mmio_context.c

414

[VCS0] = 0xc900,

sys/dev/pci/drm/i915/i915_gpu_error.c

1423

case VCS0:

sys/dev/pci/drm/i915/i915_irq.c

1096

intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],

sys/dev/pci/drm/i915/i915_pci.c

225

.platform_engine_mask = BIT(RCS0) | BIT(VCS0),

sys/dev/pci/drm/i915/i915_pci.c

233

.platform_engine_mask = BIT(RCS0) | BIT(VCS0),

sys/dev/pci/drm/i915/i915_pci.c

239

.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \

sys/dev/pci/drm/i915/i915_pci.c

265

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

sys/dev/pci/drm/i915/i915_pci.c

313

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

sys/dev/pci/drm/i915/i915_pci.c

380

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),

sys/dev/pci/drm/i915/i915_pci.c

388

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

447

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

453

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

498

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)

sys/dev/pci/drm/i915/i915_pci.c

513

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

560

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

581

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

614

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

620

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

627

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

643

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

650

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),

sys/dev/pci/drm/i915/i915_pci.c

668

BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

677

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

685

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

736

BIT(VCS0) | BIT(VCS2) | \

sys/dev/pci/drm/i915/i915_pci.c

755

.engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),