TRANSCONF_ENABLE
TRANSCONF_ENABLE);
TRANSCONF_ENABLE, 0);
ret = tmp & TRANSCONF_ENABLE;
val |= TRANSCONF_ENABLE;
if (!(tmp & TRANSCONF_ENABLE))
val |= TRANSCONF_ENABLE;
val |= TRANSCONF_ENABLE;
if (!(tmp & TRANSCONF_ENABLE))
return tmp & TRANSCONF_ENABLE;
cur_state = !!(val & TRANSCONF_ENABLE);
if (val & TRANSCONF_ENABLE) {
val | TRANSCONF_ENABLE);
if ((val & TRANSCONF_ENABLE) == 0)
val &= ~TRANSCONF_ENABLE;
if ((val & TRANSCONF_ENABLE) == 0)
intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)
return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
if (data & TRANSCONF_ENABLE) {