TRANSCONF
intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
intel_de_rmw(display, TRANSCONF(display, dsi_trans),
if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
TRANSCONF(display, pipe_config->cpu_transcoder));
TRANSCONF(display, pipe_config->cpu_transcoder));
if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder),
TRANSCONF(display, cpu_transcoder));
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
intel_de_posting_read(display, TRANSCONF(display, pipe));
intel_de_write(display, TRANSCONF(display, pipe), 0);
intel_de_posting_read(display, TRANSCONF(display, pipe));
if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)
if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)
return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&
intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
intel_de_rmw(display, TRANSCONF(display, cpu_transcoder),
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;
pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
TRANSCONF(display, cpu_transcoder));
TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;
vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,
MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,
MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,
MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,
MMIO_D(TRANSCONF(display, TRANSCODER_A));
MMIO_D(TRANSCONF(display, TRANSCODER_B));
MMIO_D(TRANSCONF(display, TRANSCODER_C));
MMIO_D(TRANSCONF(display, TRANSCODER_EDP));