sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2459

[I915_EXEC_BLT] = BCS0,

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

173

case BCS0:

sys/dev/pci/drm/i915/gt/intel_engine.h

97

ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1469

if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

1708

[BCS0] = MSG_IDLE_BCS,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

403

[BCS0] = GEN11_GRDOM_BLT,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

436

[BCS0] = GEN6_GRDOM_BLT,

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

71

[BCS0] = {

sys/dev/pci/drm/i915/gt/intel_engine_user.c

212

[COPY_ENGINE_CLASS] = { BCS0, 1 },

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3503

[BCS0] = GEN8_BCS_IRQ_SHIFT,

sys/dev/pci/drm/i915/gt/intel_ggtt.c

345

ce = gt->engine[BCS0]->bind_context;

sys/dev/pci/drm/i915/gt/intel_gt.c

1128

struct intel_engine_cs *engine = gt->engine[BCS0];

sys/dev/pci/drm/i915/gt/intel_gt.c

1167

struct intel_engine_cs *engine = gt->engine[BCS0];

sys/dev/pci/drm/i915/gt/intel_mocs.c

573

[BCS0] = __GEN9_BCS0_MOCS0,

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

98

case BCS0:

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1055

if (s->engine->id == BCS0 &&

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1160

[BCS0] = {

sys/dev/pci/drm/i915/gvt/cmd_parser.c

432

#define R_BCS BIT(BCS0)

sys/dev/pci/drm/i915/gvt/cmd_parser.c

622

[BCS0] = {

sys/dev/pci/drm/i915/gvt/execlist.c

50

[BCS0] = BCS_AS_CONTEXT_SWITCH,

sys/dev/pci/drm/i915/gvt/handlers.c

2113

id = BCS0;

sys/dev/pci/drm/i915/gvt/handlers.c

348

engine_mask |= BIT(BCS0);

sys/dev/pci/drm/i915/gvt/mmio_context.c

137

{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

sys/dev/pci/drm/i915/gvt/mmio_context.c

138

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

sys/dev/pci/drm/i915/gvt/mmio_context.c

139

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

140

{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

141

{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

172

[BCS0] = 0xcc00,

sys/dev/pci/drm/i915/gvt/mmio_context.c

359

[BCS0] = 0x426c,

sys/dev/pci/drm/i915/gvt/mmio_context.c

416

[BCS0] = 0xcc00,

sys/dev/pci/drm/i915/gvt/mmio_context.c

83

{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */

sys/dev/pci/drm/i915/gvt/mmio_context.c

84

{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */

sys/dev/pci/drm/i915/gvt/mmio_context.c

85

{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

86

{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */

sys/dev/pci/drm/i915/gvt/mmio_context.c

87

{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */

sys/dev/pci/drm/i915/gvt/scheduler.c

169

} else if (workload->engine->id == BCS0)

sys/dev/pci/drm/i915/i915_gpu_error.c

1420

case BCS0:

sys/dev/pci/drm/i915/i915_pci.c

265

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

sys/dev/pci/drm/i915/i915_pci.c

313

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

sys/dev/pci/drm/i915/i915_pci.c

380

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),

sys/dev/pci/drm/i915/i915_pci.c

388

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

447

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

453

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

498

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)

sys/dev/pci/drm/i915/i915_pci.c

513

.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

sys/dev/pci/drm/i915/i915_pci.c

560

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

581

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

sys/dev/pci/drm/i915/i915_pci.c

614

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

620

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

627

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),

sys/dev/pci/drm/i915/i915_pci.c

643

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

650

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),

sys/dev/pci/drm/i915/i915_pci.c

667

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |

sys/dev/pci/drm/i915/i915_pci.c

677

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

685

BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

sys/dev/pci/drm/i915/i915_pci.c

734

BIT(RCS0) | BIT(BCS0) | \

sys/dev/pci/drm/i915/i915_pci.c

781

.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),