sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
155
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
159
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
101
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
105
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
109
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
328
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
331
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
358
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
384
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
81
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
85
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
89
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
93
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
97
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
242
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
246
while (!(RREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
256
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
260
reg = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
266
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
268
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
270
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
272
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
274
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
299
hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
300
hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
48
SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
493
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
498
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1021
*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1044
*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1056
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1058
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1065
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1067
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
110
pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
111
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
116
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
123
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
130
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
165
SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
173
SOC15_REG_OFFSET(SDMA1, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
189
uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
224
hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
227
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
361
for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
362
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
670
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
738
uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
744
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
750
RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
770
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
771
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
772
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
781
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
798
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
837
wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
841
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
849
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
852
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
874
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
937
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
945
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
950
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
953
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
957
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
960
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
969
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
977
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
991
WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
995
WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
104
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
143
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
147
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
151
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
155
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
210
hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
213
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
264
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
347
for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
348
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
598
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
618
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
641
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
643
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
650
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
652
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
100
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
134
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
138
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
187
value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
190
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
195
hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
198
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
205
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
234
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
236
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
238
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
240
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
244
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_PQ_WPTR_POLL_CNTL1),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
249
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_EOP_RPTR),
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
254
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
332
for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
333
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
457
act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
462
if (low == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE)) &&
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
463
high == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE_HI)))
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
515
WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_DEQUEUE_REQUEST), type);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
519
temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
582
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
583
WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
592
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
772
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
776
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
86
WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
87
WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
124
for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
125
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
171
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
172
WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
181
WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
347
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
351
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
85
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
89
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1100
*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
120
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
123
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
129
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
134
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
137
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
140
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
146
WREG32(SOC15_REG_OFFSET(ATHUB, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
151
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
194
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
198
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
238
hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
241
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
372
for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
373
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
620
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
676
uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
685
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
691
RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
709
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
732
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
771
wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
775
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
783
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
786
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
808
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
854
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
858
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
862
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
872
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
886
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
965
reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4036
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4338
ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4364
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4365
reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4366
reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4367
reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4368
reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4369
reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4373
SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4377
SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5190
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5191
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5193
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5194
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5385
return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5387
return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5406
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5408
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5410
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5412
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6407
SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7348
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7350
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7356
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7358
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7364
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7366
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7372
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7374
(SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7380
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7382
(SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7388
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7390
(SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7396
data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7398
(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7403
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7405
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7411
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7413
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7419
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7421
(SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7427
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7429
(SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7435
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7437
(SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7443
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7445
(SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7451
data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7453
(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7771
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7776
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7781
SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
7786
SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8303
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8504
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8509
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8514
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8523
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8528
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8533
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8802
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9061
cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9064
cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9108
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9111
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9114
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9117
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9421
target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9423
target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9545
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9550
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9748
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2172
return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2174
return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2193
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2195
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2197
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2199
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2301
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2304
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3646
SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5199
SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5204
SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5209
SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5214
SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5576
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
561
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6023
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6318
cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6321
cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6369
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6372
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6375
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6378
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6700
target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6807
r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6972
r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7118
RREG32(SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
866
ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
892
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
893
reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
894
reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
895
reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
896
reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
897
reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
898
reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
44
rlc_status0 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_0));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c
45
rlc_status1 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_1));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1843
return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1862
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1864
return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1966
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1969
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3963
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3981
uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
453
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4543
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4703
cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4751
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4754
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5280
r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
735
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
736
reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
737
reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
738
reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
739
reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
740
reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
741
reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1197
uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1825
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1826
reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1827
reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1828
reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1829
reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1830
reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1831
reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2577
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2578
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2580
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2581
WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2772
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2774
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2776
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2847
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2849
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2852
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2855
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2859
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2864
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2892
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2894
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2897
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2900
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2906
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2910
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2931
default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2936
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2942
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2947
WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2959
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2962
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2970
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2972
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2975
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2977
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2980
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2982
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2987
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2999
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3004
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3013
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3018
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3027
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3032
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3040
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3045
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3053
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3058
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3062
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3070
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3075
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3083
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3088
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3379
(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4318
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4323
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4328
SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4333
SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4698
ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4726
ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4754
ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5159
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5308
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5313
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5322
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5327
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5333
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5659
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5752
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5964
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5967
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5970
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5973
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6015
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6017
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6019
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6021
return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7114
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7117
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7120
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7123
wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7146
SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7324
RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
390
ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_PGM_LO)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
397
ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_USER_DATA_0)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
779
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
785
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA0), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
786
WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA1), 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1443
reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1444
reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1445
reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1446
reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1447
reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1448
reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1449
reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1674
reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1783
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1785
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2496
SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2501
SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2506
SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2511
SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2796
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2801
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2810
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2815
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2986
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3080
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3083
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3086
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3089
mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3131
return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3133
return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3135
return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3137
return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3424
wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3427
wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3430
wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3433
wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3455
SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
425
xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
426
scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4689
RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
471
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
474
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
477
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
479
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
481
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
483
SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
485
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
487
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
476
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
479
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
482
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
484
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
486
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
488
SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
490
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
492
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
420
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
423
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
426
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
428
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
430
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
432
SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
434
SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
436
SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
553
SOC15_REG_OFFSET(GC, GET_INST(GC, i),
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
556
SOC15_REG_OFFSET(GC, GET_INST(GC, i),
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
559
SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
561
SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
563
SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
565
SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
567
SOC15_REG_OFFSET(GC, GET_INST(GC, i),
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
570
SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
440
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
443
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
446
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
448
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
450
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
452
SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
454
SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
456
SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
471
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
474
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
477
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
479
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
481
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
483
SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
485
SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
487
SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
468
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
471
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
474
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
476
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
478
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
480
SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
482
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
484
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
456
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
459
SOC15_REG_OFFSET(GC, 0,
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
462
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
464
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
466
SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
468
SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
470
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
472
SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
226
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
429
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
431
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
220
*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
421
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
423
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
213
*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
457
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
459
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1044
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1046
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
816
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
100
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
102
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
116
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
132
data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
51
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c
92
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c
37
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
54
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
55
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
56
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
57
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
58
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
59
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
60
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
61
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
67
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
68
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
69
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
70
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
71
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
72
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
54
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
55
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
56
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
57
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
58
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
59
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
60
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
61
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
67
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
68
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
69
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
70
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
71
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
72
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
54
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
55
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
56
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
57
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
58
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
59
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
60
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
61
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
67
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
68
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
69
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
70
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
71
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
72
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
308
if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
310
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
312
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
314
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
316
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
318
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
320
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
322
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
324
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
326
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
328
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
330
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
332
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
334
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
336
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
356
if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
101
ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
103
ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
121
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
127
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
187
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
206
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
231
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
235
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
239
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
243
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
247
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
251
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
255
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
259
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
263
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
267
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
275
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
306
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
313
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
317
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
321
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
325
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
329
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
333
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
341
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
345
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
349
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
361
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
365
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
369
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
405
PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
45
ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
504
SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
64
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
70
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
82
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
88
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
94
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
99
ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
114
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
236
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
249
data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
250
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
261
data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
264
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
267
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
354
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
358
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
389
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
159
adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
345
WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
358
WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
362
WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
403
WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
410
WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
129
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
294
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
307
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
311
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
320
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
329
WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
374
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
378
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
409
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
136
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
331
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
344
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
348
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
357
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
366
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
410
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
414
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
474
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
477
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
480
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
569
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
291
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
293
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
295
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
555
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
568
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
579
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
639
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
646
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
170
adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
377
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
384
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
388
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
397
WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
402
WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
433
WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
540
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
544
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
585
WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
117
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
279
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
288
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
293
WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
451
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
455
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
494
WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
371
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
375
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
383
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
391
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
396
WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
409
reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
489
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
491
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
493
tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC_RB_SIZE);
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
34
return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS),
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
34
return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS),
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
455
reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
459
reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
480
reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
484
reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
472
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
475
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
478
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
480
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
482
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
484
SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
486
SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
488
SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
456
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
459
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
462
SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
464
SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
466
SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
468
SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
470
SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
591
hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
593
hub->ctx0_ptb_addr_hi32 = SOC15_REG_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
596
SOC15_REG_OFFSET(MMHUB, i, regVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
598
SOC15_REG_OFFSET(MMHUB, i, regVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
600
SOC15_REG_OFFSET(MMHUB, i, regVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
601
hub->vm_l2_pro_fault_status = SOC15_REG_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
603
hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(MMHUB, i,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
529
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
532
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
535
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
537
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
539
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
541
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
543
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
545
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
454
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
457
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
460
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
463
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
465
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
467
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
469
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
471
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
483
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
486
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
489
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
491
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
493
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
495
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
497
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
499
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
518
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
521
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
472
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
475
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
478
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
480
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
482
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
484
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
486
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
488
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
475
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
478
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
481
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
483
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
485
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
487
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
489
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
491
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
510
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
614
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
617
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
620
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
622
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
624
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
626
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
628
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
630
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
477
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
480
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
483
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
485
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
487
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
489
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
491
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
493
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
512
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
515
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
547
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
551
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
555
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
559
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
563
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
567
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
571
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
575
SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
140
reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
144
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
146
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
148
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
150
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
182
RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
243
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
247
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
331
u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
335
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
58
return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
68
reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.h
72
(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.h
74
(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1)
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
55
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
56
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
57
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
58
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
59
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
60
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
61
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
62
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
68
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
69
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
70
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
71
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
72
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
73
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
79
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
80
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
81
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
82
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
83
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
84
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
262
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
267
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
272
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
277
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
446
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
112
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
113
instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
114
instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
115
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
137
u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
138
SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
298
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
303
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
308
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
313
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
559
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
305
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
310
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
315
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
320
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
482
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
229
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
234
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
239
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
244
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
401
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
91
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
92
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
240
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
245
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
250
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
255
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
297
SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
70
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
71
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
87
u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
117
SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE):
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
118
SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
221
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
226
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
231
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
236
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
241
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_INDEX);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
246
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_DATA);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
372
SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
68
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
92
SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
93
SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
111
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
133
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
191
u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
206
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
238
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
256
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
268
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
275
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
277
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
287
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
291
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
302
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
313
data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
318
data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
325
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
330
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
335
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
340
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
345
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
350
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
375
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
382
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
385
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
392
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
415
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
145
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
160
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
164
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
187
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
189
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
191
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
308
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
313
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
318
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
323
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
799
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
193
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
198
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
203
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
208
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
213
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
218
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
341
SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
68
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
90
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
342
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
347
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
352
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
357
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
362
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
476
SOC15_REG_OFFSET(
sys/dev/pci/drm/amd/amdgpu/nv.c
283
address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/nv.c
284
data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/nv.c
297
address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/nv.c
298
data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/nv.c
381
if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
117
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
96
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
180
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
276
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
303
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
307
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
345
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
351
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
377
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
409
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
442
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
621
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
658
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
125
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
45
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
55
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
93
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
99
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
120
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
135
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
165
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
188
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
192
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
222
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
237
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
84
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
99
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
163
(SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
184
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
215
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
364
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
388
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
398
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
436
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
442
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
468
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
533
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
685
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
722
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
745
ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
749
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
773
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
808
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
937
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
185
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
206
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
216
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
254
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
260
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
286
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
80
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
115
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
232
SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
253
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
263
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
301
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
307
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
333
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
398
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
551
SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
589
SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
611
ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
615
psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
619
SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
644
SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
111
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
132
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
149
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
170
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
182
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
221
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
244
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
270
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
274
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
313
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
327
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
93
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1258
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1262
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1265
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1268
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1277
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1280
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1283
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1286
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1289
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1296
WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2343
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2348
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2040
data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2045
data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c
30
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c
35
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c
30
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c
35
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
32
return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c
37
return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_6.c
30
return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_6.c
35
return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c
31
return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c
36
return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c
30
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c
35
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1377
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1399
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1406
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1414
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
sys/dev/pci/drm/amd/amdgpu/soc15.c
1488
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/pci/drm/amd/amdgpu/soc15.c
1493
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/pci/drm/amd/amdgpu/soc15.c
245
address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc15.c
246
data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
sys/dev/pci/drm/amd/amdgpu/soc15.c
259
address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc15.c
260
data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
sys/dev/pci/drm/amd/amdgpu/soc15.c
273
address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc15.c
274
data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/soc15.c
287
address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc15.c
288
data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/soc15.c
428
if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
sys/dev/pci/drm/amd/amdgpu/soc15.c
430
else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
sys/dev/pci/drm/amd/amdgpu/soc15.c
493
if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
494
reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
495
reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
496
reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
sys/dev/pci/drm/amd/amdgpu/soc21.c
198
address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc21.c
199
data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/soc21.c
212
address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
sys/dev/pci/drm/amd/amdgpu/soc21.c
213
data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
sys/dev/pci/drm/amd/amdgpu/soc21.c
302
if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
sys/dev/pci/drm/amd/amdgpu/soc24.c
161
if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
127
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
339
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
357
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
401
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
403
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c
58
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
103
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
106
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
111
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
114
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
181
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
183
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
185
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
189
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
191
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
193
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
236
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
240
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
308
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
310
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
314
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
316
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
400
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
402
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
406
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
408
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
48
rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
63
rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c
78
rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
274
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
276
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
278
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
316
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
345
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
371
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
374
SOC15_REG_OFFSET(UMC, 0,
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
452
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
454
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
498
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccCtrl);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
74
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
81
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0);
sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c
88
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
112
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
130
mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
256
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
273
mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
304
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
306
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c
88
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
129
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
131
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
46
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
69
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c
84
SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
187
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
189
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
245
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
247
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
249
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
288
mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
336
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
338
SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
397
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel);
sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c
399
SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt);
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
413
umsch->rb_wptr = SOC15_REG_OFFSET(VCN, 0, regVCN_UMSCH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
414
umsch->rb_rptr = SOC15_REG_OFFSET(VCN, 0, regVCN_UMSCH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1040
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1061
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1065
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1076
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1081
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1114
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1152
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1166
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1189
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1192
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1195
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1198
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1202
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1205
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1208
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1265
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1330
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1334
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1337
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1340
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1374
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1377
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1380
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1390
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1393
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1396
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1399
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1426
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
549
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
554
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
559
tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
565
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
569
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
824
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
828
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
831
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
834
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
837
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
839
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
842
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
847
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
849
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
851
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
853
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
854
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
856
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
858
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
860
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
861
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
864
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
868
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
872
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
876
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
881
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
892
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
901
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
905
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
909
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
914
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
921
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
925
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
926
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
927
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
930
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
933
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
936
MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
966
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
981
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
985
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
989
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
115
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
118
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
121
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
132
RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
140
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
144
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
164
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
165
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
168
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
171
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
174
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
177
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
185
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
187
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
191
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
234
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
236
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
238
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
242
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
243
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
244
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
245
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
246
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
254
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
256
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
259
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
261
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
264
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
267
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
271
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
274
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
277
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
280
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
285
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
289
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
291
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
295
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
297
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
299
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
300
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
305
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
307
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
309
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
312
MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
317
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
343
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
344
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
345
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
346
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
347
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
351
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
352
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
353
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
354
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
355
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
359
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
360
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
361
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
362
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
363
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
366
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
369
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
371
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
378
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
392
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
395
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
400
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
635
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
636
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
637
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
638
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
640
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
641
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
642
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
643
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
644
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
651
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
653
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
655
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
657
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
659
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
661
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
665
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
667
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
668
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
67
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
671
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
672
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
674
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
675
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
678
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
679
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
681
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
682
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
69
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
71
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
782
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
89
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
91
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
93
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1163
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1205
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1214
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1218
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1222
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1227
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1272
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1519
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1522
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1538
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1560
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1563
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1566
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1569
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1573
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1576
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1579
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1602
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1606
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1609
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1612
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1623
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1626
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1629
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1632
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1657
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1660
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1663
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
177
SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
179
SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
181
SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
183
SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1843
amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
185
SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
866
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
915
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
919
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
941
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
945
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
956
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
960
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
999
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1026
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1030
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1070
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1074
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1104
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1108
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1120
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1125
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1205
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1254
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1258
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1263
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1268
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1322
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1351
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
188
adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
190
adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
192
adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
194
adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
196
adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1987
SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1993
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1997
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2003
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2007
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2014
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2017
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2021
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2025
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2029
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2032
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2036
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2041
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2046
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2049
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2056
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2059
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2062
SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2069
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2073
SOC15_REG_OFFSET(UVD, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2084
SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
961
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
990
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1015
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1122
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1151
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1182
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1196
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1200
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1247
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1251
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1254
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1274
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1278
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1291
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1296
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1435
SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1442
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1446
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1451
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1454
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1458
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1463
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1468
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1471
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1475
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1479
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1482
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1485
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1490
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1495
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1498
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1505
SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1508
SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1511
SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1517
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1521
SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1533
SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1572
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1623
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1628
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1633
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1642
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1690
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1716
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
331
adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
333
adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
335
adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
337
adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
339
adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1038
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1147
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1182
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1222
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1226
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1230
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1279
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1283
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1300
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1304
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1317
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1322
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1431
MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1438
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1441
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1445
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1449
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1452
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1456
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1461
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1466
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1469
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1472
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1475
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1481
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1484
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1487
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1490
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1498
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1501
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1504
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1512
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1515
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1525
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1621
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1671
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1676
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1681
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1745
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1779
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
217
adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
219
adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
221
adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
223
adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
225
adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1006
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1167
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1171
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1175
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1224
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1228
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1255
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1259
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1273
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1278
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1386
MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1393
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1396
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1400
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1404
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1407
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1411
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1416
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1421
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1424
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1427
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1430
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1436
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1439
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1442
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1445
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1481
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1484
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1487
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1589
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1648
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1653
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1658
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1038
MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1044
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1048
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1053
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1056
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1059
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1063
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1068
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1073
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1075
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1077
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1079
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1085
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1088
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1091
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1094
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1110
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1113
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1116
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1208
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1213
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1217
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1268
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1272
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1291
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1296
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1310
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1315
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1378
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1441
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1446
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1451
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
856
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1079
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1083
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1087
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1136
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1140
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1168
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1172
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1186
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1191
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1251
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1311
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1316
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1321
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
921
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1042
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1047
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1052
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
705
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
833
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
837
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
841
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
864
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
868
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
896
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
900
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
914
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
919
WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
980
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1003
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1007
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1030
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1034
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1062
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1066
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1080
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1085
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1154
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1212
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1217
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1222
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
681
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
830
MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
836
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
840
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
845
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
848
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
851
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
855
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
860
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
865
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
867
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
869
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
871
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
877
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
880
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
883
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
886
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
902
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
905
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
908
MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
999
WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
53
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
54
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
55
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
56
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
57
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
58
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
59
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
60
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
66
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
67
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
68
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
69
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
70
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
71
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
77
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
78
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
79
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
80
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
81
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
82
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
61
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
62
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
63
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
64
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
65
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
66
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
67
ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
68
ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
74
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
75
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
76
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
77
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
78
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
79
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
85
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
86
ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
87
ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
88
ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
89
ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
90
ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
54
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
66
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
76
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
75
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2184
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2185
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
2186
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2252
tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1502
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1503
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c
1504
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2366
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2367
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2368
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2973
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2974
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2975
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2977
smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2978
smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
2979
smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
1127
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
1128
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
1129
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1136
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1137
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
1138
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1707
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1708
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
1709
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2186
smu->param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2187
smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2188
smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2190
smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2191
smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
2192
smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
