SM
ds->ds_ctl0 = SM(AR_TXC0_FRAME_LEN, totlen);
ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, AR_MAX_RATE_POWER);
ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, AR_FRAME_TYPE_BEACON);
ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, AR_ENCR_TYPE_CLEAR);
ds->ds_ctl2 = SM(AR_TXC2_XMIT_DATA_TRIES0, 1);
ds->ds_ctl3 = SM(AR_TXC3_XMIT_RATE0, hwrate);
ds->ds_ctl7 = SM(AR_TXC7_CHAIN_SEL0, sc->txchainmask);
ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, txpower);
ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, type);
ds->ds_ctl1 |= SM(AR_TXC1_DEST_IDX, entry);
ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, encrtype);
SM(AR_TXC2_XMIT_DATA_TRIES0, 2) |
SM(AR_TXC2_XMIT_DATA_TRIES1, 2) |
SM(AR_TXC2_XMIT_DATA_TRIES2, 2) |
SM(AR_TXC2_XMIT_DATA_TRIES3, 4);
SM(AR_TXC3_XMIT_RATE0, series[0].hwrate) |
SM(AR_TXC3_XMIT_RATE1, series[1].hwrate) |
SM(AR_TXC3_XMIT_RATE2, series[2].hwrate) |
SM(AR_TXC3_XMIT_RATE3, series[3].hwrate);
SM(AR_TXC4_PACKET_DUR0, series[0].dur) |
SM(AR_TXC4_PACKET_DUR1, series[1].dur);
SM(AR_TXC5_PACKET_DUR2, series[2].dur) |
SM(AR_TXC5_PACKET_DUR3, series[3].dur);
SM(AR_TXC7_CHAIN_SEL0, sc->txchainmask) |
SM(AR_TXC7_CHAIN_SEL1, sc->txchainmask) |
SM(AR_TXC7_CHAIN_SEL2, sc->txchainmask) |
SM(AR_TXC7_CHAIN_SEL3, sc->txchainmask);
ds->ds_ctl9 = SM(AR_TXC9_XMIT_POWER1, txpower);
ds->ds_ctl10 = SM(AR_TXC10_XMIT_POWER2, txpower);
ds->ds_ctl11 = SM(AR_TXC11_XMIT_POWER3, txpower);
ds->ds_ctl2 |= SM(AR_TXC2_BURST_DUR, dur);
ds->ds_ctl7 |= SM(AR_TXC7_RTSCTS_RATE, hwrate);
ds->ds_ctl0 |= SM(AR_TXC0_FRAME_LEN, totlen);
ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
ds->ds_ctl1 = SM(AR_RXC1_BUF_LEN, ATHN_RXBUFSZ);
phy |= SM(AR5416_AMODE_REFSEL, 2);
phy |= SM(AR5416_AMODE_REFSEL, 1);
phy |= SM(AR5416_AMODE_REFSEL, 2);
phy |= SM(AR5416_AMODE_REFSEL, 2);
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
(SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) {
SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
SM(AR_TXI_DESC_NDWORDS, 23) |
SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) |
ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen);
ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER);
ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON);
ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR);
ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1);
ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate);
ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->txchainmask);
ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN,
ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum);
SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
SM(AR_TXI_DESC_NDWORDS, 23) |
SM(AR_TXI_QCU_NUM, qid) |
ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower);
ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type);
ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry);
ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype);
ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK,
SM(AR_TXC13_XMIT_DATA_TRIES0, 2) |
SM(AR_TXC13_XMIT_DATA_TRIES1, 2) |
SM(AR_TXC13_XMIT_DATA_TRIES2, 2) |
SM(AR_TXC13_XMIT_DATA_TRIES3, 4);
SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) |
SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) |
SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) |
SM(AR_TXC14_XMIT_RATE3, series[3].hwrate);
SM(AR_TXC15_PACKET_DUR0, series[0].dur) |
SM(AR_TXC15_PACKET_DUR1, series[1].dur);
SM(AR_TXC16_PACKET_DUR2, series[2].dur) |
SM(AR_TXC16_PACKET_DUR3, series[3].dur);
SM(AR_TXC18_CHAIN_SEL0,
SM(AR_TXC18_CHAIN_SEL1,
SM(AR_TXC18_CHAIN_SEL2,
SM(AR_TXC18_CHAIN_SEL3,
SM(AR_TXC18_CHAIN_SEL0, sc->txchainmask) |
SM(AR_TXC18_CHAIN_SEL1, sc->txchainmask) |
SM(AR_TXC18_CHAIN_SEL2, sc->txchainmask) |
SM(AR_TXC18_CHAIN_SEL3, sc->txchainmask);
ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur);
ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate);
ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen);
ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN,
ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum);
AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
SM(AR_PHY_PAPRD_PA_IN, sc->pa_in[chain][i]) |
SM(AR_PHY_PAPRD_ANGLE, sc->angle[chain][i]));
AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS))
phy |= SM(AR9280_AMODE_REFSEL, 3);
phy |= SM(AR9280_AMODE_REFSEL, 2);
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]);
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |
SM(AR_BT_PRIORITY_TIME, 2) |
SM(AR_BT_FIRST_SLOT_TIME, 5) |
SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |
SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |
SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT));
SM(AR_BT_BCN_MISS_THRESH, 50) |
SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET);
SM(AR_QUIET2_QUIET_DUR, 10));
SM(AR_D_RETRY_LIMIT_STA_SH, 32) |
SM(AR_D_RETRY_LIMIT_STA_LG, 32) |
SM(AR_D_RETRY_LIMIT_FR_SH, 10));
SM(AR_D_MISC_BKOFF_THRESH, 2) |
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
SM(AR_D_LCL_IFS_CWMIN, 0) |
SM(AR_D_LCL_IFS_CWMAX, 0) |
SM(AR_D_LCL_IFS_AIFS, 1));
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |
SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL));
SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)));
SM(AR_QOS_NO_ACK_TWO_BIT, 2) |
SM(AR_QOS_NO_ACK_BIT_OFF, 5) |
SM(AR_QOS_NO_ACK_BYTE_OFF, 0));
AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
AR_WRITE(sc, AR_TIMT, SM(AR_TIMT_FIRST, 2000) | SM(AR_TIMT_LAST, 500));
AR_WRITE(sc, AR_MIRT, SM(AR_MIRT_RATE_THRES, 2000));
SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |
SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |
SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn));
SM(AR_D_CHNTIME_DUR,
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);
pll |= SM(AR_RTC_PLL_DIV, 0x0a);
pll |= SM(AR_RTC_PLL_DIV, 0x0b);
(((var) & ~field##_M) | SM(field, val))
(((var) & ~field##_M) | SM(field, val))
SM(R92C_EDCA_PARAM_TXOP, ac->ac_txoplimit) |
SM(R92C_EDCA_PARAM_ECWMIN, ac->ac_ecwmin) |
SM(R92C_EDCA_PARAM_ECWMAX, ac->ac_ecwmax) |
SM(R92C_EDCA_PARAM_AIFS, aifs));
SM(R92C_CAM_ALGO, algo) |
SM(R92C_CAM_KEYID, k->k_id) |
SM(R92C_CAM_MACLO, LE_READ_2(&macaddr[0])) |
SM(R92C_TXAGC_RATE06, power[RTWN_POWER_OFDM6]) |
SM(R92C_TXAGC_RATE09, power[RTWN_POWER_OFDM9]) |
SM(R92C_TXAGC_RATE12, power[RTWN_POWER_OFDM12]) |
SM(R92C_TXAGC_RATE18, power[RTWN_POWER_OFDM18]));
SM(R92C_TXAGC_RATE24, power[RTWN_POWER_OFDM24]) |
SM(R92C_TXAGC_RATE36, power[RTWN_POWER_OFDM36]) |
SM(R92C_TXAGC_RATE48, power[RTWN_POWER_OFDM48]) |
SM(R92C_TXAGC_RATE54, power[RTWN_POWER_OFDM54]));
SM(R92C_TXAGC_MCS00, power[RTWN_POWER_MCS( 0)]) |
SM(R92C_TXAGC_MCS01, power[RTWN_POWER_MCS( 1)]) |
SM(R92C_TXAGC_MCS02, power[RTWN_POWER_MCS( 2)]) |
SM(R92C_TXAGC_MCS03, power[RTWN_POWER_MCS( 3)]));
SM(R92C_TXAGC_MCS04, power[RTWN_POWER_MCS( 4)]) |
SM(R92C_TXAGC_MCS05, power[RTWN_POWER_MCS( 5)]) |
SM(R92C_TXAGC_MCS06, power[RTWN_POWER_MCS( 6)]) |
SM(R92C_TXAGC_MCS07, power[RTWN_POWER_MCS( 7)]));
SM(R92C_TXAGC_MCS08, power[RTWN_POWER_MCS( 8)]) |
SM(R92C_TXAGC_MCS09, power[RTWN_POWER_MCS( 9)]) |
SM(R92C_TXAGC_MCS10, power[RTWN_POWER_MCS(10)]) |
SM(R92C_TXAGC_MCS11, power[RTWN_POWER_MCS(11)]));
SM(R92C_TXAGC_MCS12, power[RTWN_POWER_MCS(12)]) |
SM(R92C_TXAGC_MCS13, power[RTWN_POWER_MCS(13)]) |
SM(R92C_TXAGC_MCS14, power[RTWN_POWER_MCS(14)]) |
SM(R92C_TXAGC_MCS15, power[RTWN_POWER_MCS(15)]));
SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07));
param_addr = SM(R88E_LSSI_PARAM_ADDR, addr);
param_addr = SM(R92C_LSSI_PARAM_ADDR, addr);
param_addr | SM(R92C_LSSI_PARAM_DATA, val));
SM(R92C_CAMCMD_ADDR, addr));
SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) |
SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher));
SM(R88E_TXDW1_MACID, R92C_MACID_BSS) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
SM(R92C_TXDW1_RAID, raid));
SM(R92C_TXDW1_MACID, R92C_MACID_BSS) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
SM(R92C_TXDW1_RAID, raid) |
txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 0));
txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f));
SM(R92C_TXDW1_MACID, 0) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
SM(R92C_TXDW1_RAID, R92C_RAID_11B));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
SM(R92C_LLT_INIT_ADDR, addr) |
SM(R92C_LLT_INIT_DATA, data));
SM(R92C_RQPN_PUBQ, pagecnt) |
SM(R92C_RQPN_HPQ, hqpages) |
SM(R92C_RQPN_LPQ, lqpages) |
SM(R92C_PBP_PSRX, R92C_PBP_128) |
SM(R92C_PBP_PSTX, R92C_PBP_128));
desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) |
SM(R92S_TXDW0_PKTLEN, m->m_pkthdr.len) |
SM(R92S_TXDW0_OFFSET, sizeof(*txd)) |
SM(R92S_TXDW1_MACID, R92S_MACID_BSS) |
SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_BE));
SM(R92S_TXDW1_CIPHER, cipher) |
SM(R92S_TXDW1_KEYIDX, k->k_id));
txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, tid));
txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen));
SM(R92S_IOCMD_CLASS, 0xf4) |
SM(R92S_IOCMD_INDEX, 0x00) |
SM(R92S_IOCMD_VALUE, 0x0007));
SM(R92S_TXDW0_OFFSET, sizeof(*txd)) |
SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) |
txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C));
R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG));
(((var) & ~field##_M) | SM(field, val))
txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,
SM(R92C_TXDW0_PKTLEN, pktlen) |
SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
SM(R88E_TXDW1_MACID, R92C_MACID_BSS) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
SM(R92C_TXDW1_RAID, raid));
SM(R92C_TXDW1_MACID, R92C_MACID_BSS) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK);
txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,
txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
SM(R92C_TXDW1_MACID, 0) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
SM(R92C_TXDW1_RAID, R92C_RAID_11B));
txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,
SM(R92C_TXDW0_PKTLEN, pktlen) |
SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
SM(R92E_TXDW1_MACID, R92C_MACID_BSS) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
SM(R92C_TXDW1_RAID, raid));
txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, 8));
txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate));
SM(R92E_TXDW1_MACID, 0) |
SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
SM(R92C_TXDW1_RAID, R92E_RAID_11B));
txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0));
txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f));
txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq));
SM(R92C_RQPN_PUBQ, pagecnt) |
SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) |
SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) |
SM(R92C_PBP_PSRX, R92C_PBP_256) |
SM(R92C_PBP_PSTX, R92C_PBP_256));
SM(R92C_PBP_PSRX, R92C_PBP_128) |
SM(R92C_PBP_PSTX, R92C_PBP_128));
SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
SM(R92C_LLT_INIT_ADDR, addr) |
SM(R92C_LLT_INIT_DATA, data));