Symbol: SF
bin/pax/options.c
459
flg |= SF;
distrib/special/more/curses.h
61
*KR, *KS, *KU, *LL, *MA, *ND, *NL, *RC, *SC, *SE, *SF,
games/sail/sync.c
119
(void) snprintf(buf, sizeof buf, SF, game);
games/sail/sync.c
145
(void) snprintf(sync_file, sizeof sync_file, SF, game);
games/sail/sync.c
52
static const char SF[] = _PATH_SYNC;
games/sail/sync.c
56
static char sync_lock[sizeof SF];
sys/arch/sh/sh/db_interface.c
524
SF(sr);
sys/arch/sh/sh/db_interface.c
525
SF(r15);
sys/arch/sh/sh/db_interface.c
526
SF(r14);
sys/arch/sh/sh/db_interface.c
527
SF(r13);
sys/arch/sh/sh/db_interface.c
528
SF(r12);
sys/arch/sh/sh/db_interface.c
529
SF(r11);
sys/arch/sh/sh/db_interface.c
530
SF(r10);
sys/arch/sh/sh/db_interface.c
531
SF(r9);
sys/arch/sh/sh/db_interface.c
532
SF(r8);
sys/arch/sh/sh/db_interface.c
533
SF(pr);
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
49
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
50
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
51
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
52
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
53
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
54
SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
55
SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
56
SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
57
SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
58
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
59
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
60
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
64
SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
65
SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
69
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
70
SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
71
SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
72
SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
73
SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
74
SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
75
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
76
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
77
SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
78
SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
79
SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
247
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
248
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
275
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
276
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
322
SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
323
SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
324
SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
325
SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
326
SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h
330
SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
100
SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
101
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
102
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
103
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
104
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
105
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
106
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
107
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
108
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
109
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
110
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
111
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
112
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
113
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
114
SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
115
SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
116
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
117
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
118
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
119
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
120
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
121
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
122
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
123
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
124
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
125
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
126
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
127
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
128
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
129
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
130
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
131
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
132
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
133
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
134
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
135
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
136
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
137
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
138
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
139
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
140
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
141
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
142
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
143
SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
144
SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
145
SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
146
SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
85
SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
86
SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
87
SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
88
SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
89
SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
90
SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
91
SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
92
SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
93
SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
94
SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
95
SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
96
SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
97
SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
98
SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
99
SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
41
SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
42
SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
43
SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
44
SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
45
SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
46
SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
47
SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h
48
SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h
44
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h
45
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h
46
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h
47
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h
48
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
136
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
137
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
138
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
139
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
140
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
141
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
142
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
143
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
144
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
145
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
146
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
147
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
148
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
149
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
150
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
151
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
152
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
153
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
154
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
155
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
156
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
157
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
158
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
159
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
160
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
161
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
162
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
163
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
164
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
165
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
166
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
167
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
168
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
169
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
170
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
171
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
172
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
173
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
174
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
175
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
176
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
177
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
178
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
179
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
180
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
181
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
182
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
183
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
184
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
185
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
186
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
187
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
188
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
189
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
190
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
191
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
192
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
193
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
194
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
195
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
196
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
197
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
198
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
199
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
200
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
201
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
202
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
203
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
204
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
205
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
206
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
207
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
208
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
209
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
210
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
211
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
212
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
213
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
214
SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
215
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
216
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
217
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
218
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
219
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
220
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
221
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
222
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
223
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
224
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
225
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
226
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
227
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
228
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
229
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
230
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
231
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
232
SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
233
SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
234
SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
235
SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
236
SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
237
SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
238
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
239
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
240
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
241
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
242
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
243
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
244
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
245
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
246
SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
247
SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
248
SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
249
SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
250
SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
251
SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
252
SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
253
SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
254
SF(MMHUBBUB_MEM_PWR_CNTL, WBIF_WHOLE_BUF_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
255
SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
256
SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
257
SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
258
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
259
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
260
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
261
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
262
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
263
SF(MMHUBBUB_WARMUP_P_VMID, MMHUBBUB_WARMUP_P_VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
264
SF(MCIF_WB0_MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, mask_sh)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
268
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
269
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
270
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
271
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
272
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
273
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
274
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
275
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
276
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
277
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
278
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
279
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
280
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
281
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
282
SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
283
SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
284
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
285
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
286
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
287
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
288
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
289
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
290
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
291
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
292
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
293
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
294
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
295
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
296
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
297
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
298
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
299
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
300
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
301
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
302
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
303
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
304
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
305
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
306
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
307
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
308
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
309
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
310
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
311
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
312
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
313
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
314
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
315
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
316
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
317
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
318
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
319
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
320
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
321
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
322
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
323
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
324
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
325
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
326
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
327
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
328
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
329
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
330
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
331
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
332
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
333
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
334
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
335
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
336
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
337
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
338
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
339
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
340
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
341
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
342
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
343
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
344
SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
345
SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
346
SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
347
SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
348
SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
349
SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
350
SF(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
351
SF(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
352
SF(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
353
SF(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
354
SF(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
355
SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
356
SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
357
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
358
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
359
SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
360
SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
361
SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
362
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
363
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
364
SF(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
365
SF(MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
366
SF(MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
367
SF(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
368
SF(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
369
SF(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
370
SF(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
371
SF(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
372
SF(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
373
SF(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
374
SF(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
375
SF(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
376
SF(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
377
SF(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
378
SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
379
SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
380
SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
381
SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
382
SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
383
SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
384
SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
385
SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
386
SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
387
SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
388
SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
389
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
390
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
391
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
392
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
393
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
394
SF(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI, mask_sh)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
714
SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
756
SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
764
SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
765
SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
766
SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
767
SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h
768
SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
100
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
101
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
102
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
103
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
104
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
105
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
106
SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
107
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
108
SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
109
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
110
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
111
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
112
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
113
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
114
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
115
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
116
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
117
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
118
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
119
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
120
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
121
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
122
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
123
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
124
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
125
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
126
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
127
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
128
SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
129
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
130
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
131
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
132
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
133
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
134
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
135
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
136
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
137
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
138
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
139
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
140
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
141
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
142
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
143
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
144
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
145
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
146
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
147
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
148
SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
149
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
150
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
151
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
152
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
153
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
154
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
155
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
156
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
157
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
158
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
159
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
160
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
161
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
162
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
163
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
164
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
165
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
166
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
167
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
168
SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
169
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
170
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
171
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
172
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
173
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
174
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
175
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
176
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
177
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
178
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
179
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
180
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
181
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
182
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
183
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
184
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
185
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
186
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
187
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
188
SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
189
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
190
SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
191
SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
192
SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
193
SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
194
SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
195
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
196
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
197
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
198
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
199
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
200
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
201
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
202
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
203
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
204
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
205
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
206
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
207
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
208
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
209
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
210
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
211
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
212
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
213
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
214
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
215
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
216
SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
217
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
218
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
219
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
220
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
221
SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
222
SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
223
SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
224
SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
225
SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
226
SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
227
SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
228
SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
229
SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
230
SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
231
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
232
SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
233
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
234
SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
235
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
236
SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
237
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
238
SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
239
SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
240
SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
241
SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
242
SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
243
SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
244
SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
245
SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
246
SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
247
SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
248
SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
249
SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
250
SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh)
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
91
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
92
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
93
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
94
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
95
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
96
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
97
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
98
SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h
99
SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
100
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
101
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
102
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
103
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
104
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
105
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
106
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
107
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
108
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
109
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
110
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
111
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
112
SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
113
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
114
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
115
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
116
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
117
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
118
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
119
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
120
SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
121
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
122
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
123
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
124
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
125
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
126
SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
127
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
128
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
129
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
130
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
131
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
132
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
133
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
134
SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
135
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
136
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
137
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
138
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
139
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
140
SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
141
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
142
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
143
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
144
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
145
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
146
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
147
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
148
SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
149
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
150
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
151
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
152
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
153
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
154
SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
155
SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
156
SF(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
157
SF(MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
158
SF(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
159
SF(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
160
SF(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
161
SF(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
162
SF(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
163
SF(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
164
SF(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
165
SF(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
166
SF(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
167
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
168
SF(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
169
SF(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
170
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
171
SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
172
SF(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
173
SF(MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
174
SF(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
175
SF(MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
176
SF(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
177
SF(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
178
SF(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
179
SF(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
180
SF(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
181
SF(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
182
SF(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
183
SF(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
184
SF(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
185
SF(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
186
SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
187
SF(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
188
SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
189
SF(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
190
SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
191
SF(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
192
SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
193
SF(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
194
SF(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB_WARMUP_ADDR_REGION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
195
SF(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
196
SF(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB_WARMUP_BASE_ADDR_LOW, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
197
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
198
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
199
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
200
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
201
SF(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_INC_ADDR, mask_sh)
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
84
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
85
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
86
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
87
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
88
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
89
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
90
SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
91
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
92
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
93
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
94
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
95
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
96
SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
97
SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
98
SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h
99
SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
39
SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
40
SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
41
SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
42
SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h
43
SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
64
SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
65
SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
66
SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
67
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
68
SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
69
SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
70
SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
71
SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
72
SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
73
SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
74
SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
75
SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
76
SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
77
SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
78
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
79
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
80
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
81
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
82
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
83
SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
84
SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h
85
SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
138
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
139
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
140
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
141
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
142
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
143
SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
144
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
145
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
146
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
147
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
148
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
149
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
150
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
151
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
152
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
153
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
154
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
155
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
156
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
157
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
158
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
159
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
160
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
161
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
162
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
163
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
164
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
165
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
166
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
167
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
168
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
169
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
170
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
171
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
172
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
173
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
174
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
175
SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
176
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
177
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
178
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
179
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
180
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
181
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
182
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h
183
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
429
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
430
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
431
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
432
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
433
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
434
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
435
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
436
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
437
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
438
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
439
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
440
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
441
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
442
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
443
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
444
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
445
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
446
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
447
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
448
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
449
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
450
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
451
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
452
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
453
SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
454
SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
455
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
456
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
457
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
458
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
459
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
460
SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
461
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
462
SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
463
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
464
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
465
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
466
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
467
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
468
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
469
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
470
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
471
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
472
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
473
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
474
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
475
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
476
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
477
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
478
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
479
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
480
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
481
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
482
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
483
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
484
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
485
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
486
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
487
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
488
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
489
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
490
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
491
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
492
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
493
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
494
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
495
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
496
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
497
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
498
SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
499
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
500
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
501
SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
502
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
503
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
504
SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
505
SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
506
SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
507
SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
508
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
509
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
510
SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
511
SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
512
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
513
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
514
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
515
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
516
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
517
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
518
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
519
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
520
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
521
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
522
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
523
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
524
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
525
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
526
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
527
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
528
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
529
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
530
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
531
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
536
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
537
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
538
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
539
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
540
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
541
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
542
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
543
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
544
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
545
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
546
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
547
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
548
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
549
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
550
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
551
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
552
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
553
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
554
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
555
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
556
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
557
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
558
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
559
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
560
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
561
SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
562
SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
563
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
564
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
565
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
566
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
567
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
568
SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
569
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
570
SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
571
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
572
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
573
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
574
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
575
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
576
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
577
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
578
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
579
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
580
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
581
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
582
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
583
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
584
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
585
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
586
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
587
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
588
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
589
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
590
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
591
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
592
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
593
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
594
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
595
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
597
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
598
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
599
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
601
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
602
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
603
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
605
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
606
SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
607
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
608
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
609
SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
610
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
612
SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
613
SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
614
SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
615
SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
616
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
617
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
618
SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
619
SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
620
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
621
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
623
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
624
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
625
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
626
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
627
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
628
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
629
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
630
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
631
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
632
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
633
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
634
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
635
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
636
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
637
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
638
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
639
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
640
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
641
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
642
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
802
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
803
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
804
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
805
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
806
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
807
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
808
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
809
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
810
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
811
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
812
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
813
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
814
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
815
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
816
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
817
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
818
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
819
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
820
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
821
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
822
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
823
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
824
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
825
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
826
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
827
SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
828
SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
829
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
830
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
831
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
832
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
833
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
834
SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
835
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
836
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
837
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
838
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
839
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
840
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
841
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
842
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
843
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
844
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
845
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
846
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
847
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
848
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
849
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
850
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
851
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
852
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
853
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
854
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
855
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
856
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
857
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
858
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
859
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
861
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
862
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
863
SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
865
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
866
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
867
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
869
SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
870
SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
871
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
872
SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
873
SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
874
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
876
SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
877
SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
878
SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
879
SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
880
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
881
SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
882
SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
883
SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
884
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
885
SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
887
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
888
SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
889
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
890
SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
891
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
892
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
893
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
894
SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
895
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
896
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
897
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
898
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
899
SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
900
SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h
901
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
180
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
181
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
182
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
183
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
184
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
185
SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
186
SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
187
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
188
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
189
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
190
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
191
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
192
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
193
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
194
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
195
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
196
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
197
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
198
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
199
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
200
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
201
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
202
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
203
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
204
SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
205
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
206
SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
207
SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
208
SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
209
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
210
SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
211
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
212
SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
213
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
214
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
215
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
216
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
217
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
218
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
219
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
220
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
221
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
222
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
223
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
224
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
225
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
226
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
227
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
228
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
229
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
230
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
231
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
232
SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
233
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
234
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
235
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
236
SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
237
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
238
SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
239
SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
240
SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
241
SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
242
SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
243
SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
244
SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
245
SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
246
SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
247
SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
248
SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
249
SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
250
SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
251
SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
252
SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
253
SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
254
SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
255
SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
256
SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
257
SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
258
SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
259
SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
260
SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
261
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
262
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
263
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
264
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
265
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
266
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
267
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
268
SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
269
SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
270
SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
271
SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_PWL_DISABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
272
SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
273
SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT_CURRENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
274
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM_1DLUT_LUT_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
275
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM_1DLUT_LUT_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
276
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
277
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
278
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_HOST_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
279
SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_CONFIG_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
280
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
281
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
282
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
283
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
284
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
285
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
286
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
287
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM_1DLUT_RAMA_OFFSET_B, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
288
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
289
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
290
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
291
SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
292
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
293
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
294
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
295
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
296
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
297
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
298
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
299
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
300
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
301
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
302
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
303
SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h
304
SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
100
SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
101
SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
102
SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
103
SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh)
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
70
SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
71
SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
72
SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
73
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
74
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
75
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
76
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
77
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
78
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
79
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
80
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
81
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
82
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
83
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
84
SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
85
SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
86
SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
87
SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
88
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
89
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
90
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
91
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
92
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
93
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
94
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
95
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
96
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
97
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
98
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
99
SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
219
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
220
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
221
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
222
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
223
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
224
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
225
SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
226
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
227
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
228
SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
229
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
230
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
231
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
232
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
233
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
234
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
235
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
236
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
237
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
238
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
239
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
240
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
241
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
242
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
243
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
244
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
245
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
246
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
247
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
248
SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
249
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
250
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
251
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
252
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
253
SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
254
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
255
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
256
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
257
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
258
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
259
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
260
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
261
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
262
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
263
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
264
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
265
SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
266
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
267
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
268
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
269
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
270
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
271
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
272
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
273
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
274
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
275
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
276
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
277
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
278
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
279
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
280
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
281
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
282
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
283
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
284
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
285
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
286
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
287
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
288
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
289
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
290
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
291
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
292
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
293
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
294
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
295
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
296
SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
297
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
298
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
299
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
300
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
301
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
302
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
303
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
304
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
305
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
306
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
307
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
308
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
309
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
310
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
311
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
312
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
313
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
314
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
315
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
316
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
317
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
318
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
319
SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
320
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
321
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
322
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
323
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
324
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
325
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
326
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
327
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
328
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
329
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
330
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
331
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
332
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
333
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
334
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
335
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
336
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
337
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
338
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
339
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
340
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
341
SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
342
SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
343
SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
344
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
345
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
346
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
347
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
348
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
349
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
350
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
351
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
352
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
353
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
354
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
355
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
359
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
360
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
361
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
362
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
363
SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
364
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
365
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
366
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
367
SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
368
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
369
SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
370
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
371
SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
51
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
52
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
53
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
54
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
55
SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
56
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
57
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
58
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
59
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
60
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
61
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
62
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
63
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
64
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
65
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
66
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
67
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
68
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
69
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
70
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
71
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
72
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
73
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
74
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
75
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
76
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
77
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
78
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
79
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
80
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
81
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
82
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
83
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
84
SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h
85
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
46
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
47
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
48
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
49
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
50
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
51
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
52
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
53
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
54
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
55
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
56
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
57
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
58
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
59
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
60
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
61
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
62
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
63
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
64
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
65
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
66
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
67
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.h
68
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
118
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
119
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
120
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
121
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
122
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
123
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
124
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
125
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
126
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
127
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
128
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
129
SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
130
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
131
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
132
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
133
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
134
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
135
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
136
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
137
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
138
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
139
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
140
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
141
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
142
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
143
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
144
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
145
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
146
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
147
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
148
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
149
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
150
SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
151
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
152
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
153
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
154
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
155
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
156
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
157
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
158
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
159
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
160
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
161
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
162
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
163
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
164
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
165
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
166
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
167
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
168
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
170
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
171
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
172
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
173
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
174
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
175
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
176
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
177
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
178
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
179
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
180
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
181
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
182
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
183
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
184
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
185
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
186
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
187
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
188
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
189
SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_BLUE_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
190
SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_GREEN_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
191
SF(OTG0_OTG_BLANK_DATA_COLOR, OTG_BLANK_DATA_COLOR_RED_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
192
SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
193
SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
194
SF(OTG0_OTG_BLANK_DATA_COLOR_EXT, OTG_BLANK_DATA_COLOR_RED_CR_EXT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
195
SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
196
SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
197
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
198
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
199
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
200
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
201
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
202
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
203
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
204
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
205
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
206
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
207
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
208
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
209
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
210
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
211
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
212
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
213
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
214
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
215
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
216
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
217
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
218
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
219
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
220
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
221
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
222
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
223
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
224
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
225
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
226
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
227
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
228
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
229
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
230
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
231
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
232
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
233
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
234
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
235
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
236
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
237
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
238
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
239
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
240
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
241
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
242
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
243
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
244
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
245
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
246
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
247
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
248
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
249
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
253
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
254
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
255
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
256
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
257
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
258
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
259
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
260
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
261
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
262
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
263
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
264
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
265
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
266
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
267
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
268
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
269
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
270
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
271
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
272
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
273
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
274
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
275
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
276
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
277
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
278
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
279
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
280
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
281
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
282
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
283
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
284
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
285
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
286
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
290
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
291
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
292
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
293
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
294
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
295
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
296
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
297
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
298
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
299
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
300
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
301
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
302
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
303
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
304
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
305
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
306
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
307
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
308
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
309
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
310
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
311
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
312
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
313
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
314
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
315
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
316
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
317
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
318
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
319
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
320
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
321
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
322
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
323
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
324
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
325
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
326
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
327
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h
328
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
107
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
108
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
109
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
110
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
111
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
112
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
113
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
114
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
115
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
116
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
117
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
118
SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
119
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
120
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
121
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
122
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
123
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
124
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
125
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
126
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
127
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
128
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
129
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
130
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
131
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
132
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
133
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
134
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
135
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
136
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
137
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
138
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
139
SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
140
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
141
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
142
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
143
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
144
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
145
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
146
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
147
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
148
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
149
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
150
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
151
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
152
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
153
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
154
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
155
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
156
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
157
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
158
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
159
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
160
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
161
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
162
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
163
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
164
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
165
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
166
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
167
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
168
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
169
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
170
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
171
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
172
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
173
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
174
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
175
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
176
SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
177
SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
178
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
179
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
180
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
181
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
182
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
183
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
184
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
185
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
186
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
187
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
188
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
189
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
190
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
191
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
192
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
193
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
194
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
195
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
196
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
197
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
198
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
199
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
200
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
201
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
202
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
203
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
204
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
205
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
206
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
207
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
208
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
209
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
210
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
211
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
212
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
213
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
214
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
215
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
216
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
217
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
218
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
219
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
220
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
221
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
222
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
223
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
224
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
225
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
226
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
227
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
228
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
229
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
230
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
231
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
232
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
233
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
234
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
235
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
236
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
237
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
238
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
239
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
240
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
241
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
242
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
243
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
244
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
245
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
246
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
247
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
248
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
249
SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
250
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
251
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
252
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
253
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
254
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
255
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
256
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
257
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
258
SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
259
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
260
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
261
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
262
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
263
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
264
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
106
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
107
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
108
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
109
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
110
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
111
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
112
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
113
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
114
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
115
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
116
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
117
SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
118
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
119
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
120
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
121
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
122
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
123
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
124
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
125
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
126
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
127
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
128
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
129
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
130
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
131
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
132
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
133
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
134
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
135
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
136
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
137
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
138
SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
139
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
140
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
141
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
142
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
143
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
144
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
145
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
146
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
147
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
148
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
149
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
150
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
151
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
152
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
153
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
154
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
155
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
156
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
157
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
158
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
159
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
160
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
161
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
162
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
163
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
164
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
165
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
166
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
167
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
168
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
169
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
170
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
171
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
172
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
173
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
174
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
175
SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
176
SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
177
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
178
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
179
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
180
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
181
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
182
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
183
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
184
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
185
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
186
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
187
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
188
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
189
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
190
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
191
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
192
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
193
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
194
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
195
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
196
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
197
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
198
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
199
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
200
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
201
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
202
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
203
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
204
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
205
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
206
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
207
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
208
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
209
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
210
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
211
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
212
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
213
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
214
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
215
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
216
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
217
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
218
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
219
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
220
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
221
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
222
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
223
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
224
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
225
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
226
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
227
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
228
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
229
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
230
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
231
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
232
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
233
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
234
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
235
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
236
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
237
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
238
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
239
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
240
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
241
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
242
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
243
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
244
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
245
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
246
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
247
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
248
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
249
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
250
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
251
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
252
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
253
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
254
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
255
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
256
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
257
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
258
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
100
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
101
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
102
SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
103
SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
104
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
105
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
106
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
107
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
108
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
109
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
110
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
111
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
112
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
113
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
114
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
115
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
116
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
117
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
118
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
119
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
120
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
121
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
122
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
123
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
124
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
125
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
126
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
127
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
128
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
129
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
130
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
131
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
132
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
133
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
134
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
135
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
136
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
137
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
138
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
139
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
140
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
141
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
142
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
143
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
144
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
145
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
146
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
147
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
148
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
149
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
150
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
151
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
152
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
153
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
154
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
155
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
156
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
157
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
158
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
159
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
160
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
161
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
162
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
163
SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
164
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
165
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
166
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
167
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
168
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
169
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
170
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
171
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
172
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
173
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
174
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
175
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
176
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
177
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
178
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
179
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
180
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
181
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
182
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
183
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
184
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
185
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
186
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
32
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
33
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
34
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
35
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
36
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
37
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
38
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
39
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
40
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
41
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
42
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
43
SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
44
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
45
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
46
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
47
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
48
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
49
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
50
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
51
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
52
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
53
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
54
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
55
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
56
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
57
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
58
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
59
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
60
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
61
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
62
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
63
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
64
SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
65
SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
66
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
67
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
68
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
69
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
70
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
71
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
72
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
73
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
74
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
75
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
76
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
77
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
78
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
79
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
80
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
81
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
82
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
83
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
84
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
85
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
86
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
87
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
88
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
89
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
90
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
91
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
92
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
93
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
94
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
95
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
96
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
97
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
98
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
99
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
34
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
35
SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
36
SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
37
SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
38
SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
39
SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
40
SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
41
SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
42
SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
43
SF(OTG0_OTG_CRC3_DATA_B, CRC3_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
44
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
45
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
46
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
47
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
48
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
49
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
50
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
51
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
52
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
53
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG_CRC0_WINDOWA_X_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
54
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
55
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG_CRC0_WINDOWA_Y_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
56
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
57
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG_CRC0_WINDOWB_X_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
58
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
59
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG_CRC0_WINDOWB_Y_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
60
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
61
SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG_CRC1_WINDOWA_X_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
62
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
63
SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG_CRC1_WINDOWA_Y_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
64
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
65
SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
66
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_START_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
67
SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
68
SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
69
SF(OTG0_OTG_V_COUNT_STOP_CONTROL, OTG_V_COUNT_STOP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
70
SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
71
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
72
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
73
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
74
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
75
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
100
SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
101
SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
102
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
103
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
104
SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
105
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
106
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
107
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
108
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
109
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
11
SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
110
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
111
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
112
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
113
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
114
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
115
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
116
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
117
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
118
SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
119
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
12
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
120
SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
121
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
122
SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
123
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
124
SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
125
SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
126
SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
127
SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
128
SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
129
SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
13
SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
130
SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
131
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
132
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
133
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
134
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
135
SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
136
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
137
SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
138
SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
139
SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
14
SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
140
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
141
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
142
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
143
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
144
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
145
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
146
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
147
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
148
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
149
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
15
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
150
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
151
SF(ODM0_OPTC_WIDTH_CONTROL2, OPTC_SEGMENT_WIDTH_LAST, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
152
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
153
SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
154
SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
155
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
156
SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
157
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
158
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
159
SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
16
SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
160
SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
161
SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
162
SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
163
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
164
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
165
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
166
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
167
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
17
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
18
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
19
SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
20
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
21
SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
22
SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
23
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
24
SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
25
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
26
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
27
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
28
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
29
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
30
SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
31
SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
32
SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
33
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
34
SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
35
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
36
SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
37
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
38
SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
39
SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
40
SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
41
SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
42
SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
43
SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
44
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
45
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
46
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
47
SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
48
SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
49
SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
50
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
51
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
52
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
53
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
54
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
55
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
56
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
57
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
58
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
59
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
60
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
61
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
62
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
63
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
64
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
65
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
66
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
67
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
68
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
69
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
70
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
71
SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
72
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
73
SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
74
SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
75
SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
76
SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
77
SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
78
SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
79
SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
80
SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
81
SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
82
SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
83
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
84
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
85
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
86
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
87
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
88
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
89
SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
90
SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
91
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
92
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
93
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
94
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
95
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
96
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
97
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
98
SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
99
SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
368
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c
369
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
216
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
217
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
250
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
251
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
334
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
335
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
212
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
213
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
257
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
258
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
254
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
255
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
355
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
356
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
345
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
346
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
271
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
272
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
280
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
281
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
274
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
275
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
260
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
261
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
241
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
242
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
240
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
241
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
254
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
255
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
234
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
235
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
239
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
240
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
225
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
226
SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
usr.sbin/lpr/common_source/common.c
94
long SF; /* suppress FF on each print job */
usr.sbin/lpr/common_source/lp.h
70
extern long SF; /* suppress FF on each print job */
usr.sbin/lpr/lpd/printjob.c
1006
if (!SF && !tof)
usr.sbin/lpr/lpd/printjob.c
1034
if (!SF)
usr.sbin/lpr/lpd/printjob.c
1334
SF = (cgetcap(bp, "sf", ':') != NULL);
usr.sbin/lpr/lpd/printjob.c
306
if (!SF && !tof)
usr.sbin/lpr/lpd/printjob.c
566
if (!SF && !tof) { /* start on a fresh page */