sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

482

act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

487

if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

488

high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

611

temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

202

value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

468

act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

473

if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

474

high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

534

temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

68

RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

93

RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

140

RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

87

RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

37

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

53

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

98

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

101

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

42

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

63

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

38

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

55

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

93

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

43

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

46

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

49

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

36

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

109

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

49

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

61

tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

88

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/pci/drm/amd/amdgpu/df_v1_7.c

93

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

227

tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

270

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

283

tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

287

tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

316

tmp = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

323

tmp = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

342

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

647

hw_assert_msklo = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

649

hw_assert_mskhi = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/df_v4_15.c

37

tmp = RREG32_SOC15(DF, 0, regNCSConfigurationRegister1);

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

34

hw_assert_msklo = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

36

hw_assert_mskhi = RREG32_SOC15(DF, 0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10085

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10089

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10180

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10184

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3839

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3857

if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4482

return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4495

*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4558

data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4593

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4608

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5087

data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5088

data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5303

tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5309

tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5327

tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5328

RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5330

tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5331

RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5470

u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5489

rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5524

tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5865

tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5872

tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5889

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5895

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5926

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5932

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5963

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5969

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6000

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6006

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6036

cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6037

bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6075

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6090

if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6136

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6142

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6157

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6214

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6220

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6235

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6291

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6297

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6312

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6448

tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6460

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6666

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6672

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6687

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6730

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6736

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6757

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6779

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6786

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6794

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6816

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6825

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6837

mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6926

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6933

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6962

tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6972

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6999

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7004

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7009

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7036

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7039

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7294

data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7298

if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7310

data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7314

if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7466

data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7470

data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7584

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7599

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7616

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7637

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7671

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7675

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7681

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7859

rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7884

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7895

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7943

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7958

def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7965

def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7973

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7984

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7991

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8011

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8022

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8037

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8044

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8068

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8082

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8097

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8103

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8127

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8134

def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8141

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8148

def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8359

u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8557

wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8558

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9429

tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9439

tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9614

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1978

gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1982

gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1997

gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2001

gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2070

data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2115

uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2116

RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2137

tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2249

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2268

rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2366

tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2396

tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2415

tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2494

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2500

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2515

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2538

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2544

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2559

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2582

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2589

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2604

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2634

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2646

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2659

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2664

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2689

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2715

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2721

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2726

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2756

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2768

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2781

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2787

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2812

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2838

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2844

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2849

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2874

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2880

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2907

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2913

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2926

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2932

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2973

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2995

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3017

tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3040

cp_status = RREG32_SOC15(GC, 0, regCP_STAT);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3050

bootload_status = RREG32_SOC15(GC, 0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3053

bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3116

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3123

if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3245

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3257

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3270

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3275

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3300

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3326

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3332

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3337

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3463

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3475

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3488

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3494

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3519

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3545

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3551

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3556

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3682

tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3693

tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3818

data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3841

data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3968

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3974

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4001

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4007

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4020

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4026

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4047

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4394

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4397

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4678

tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4682

tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4695

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4731

data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4735

data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4835

adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4939

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4954

tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4975

val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5005

tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5048

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5049

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5050

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5061

if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5062

!RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5072

grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5085

grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5098

tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5106

if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5115

tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5168

clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5169

clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5170

clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5172

clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5177

clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5178

clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5179

clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5181

clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5295

rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5311

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5331

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5350

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5369

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5392

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5403

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5428

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5444

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5462

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5480

def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5489

data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5496

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5502

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5508

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5520

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5530

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5536

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5618

u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5724

data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5741

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5750

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5774

wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5775

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6706

tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6716

tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6871

reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6906

r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7442

data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7443

data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

977

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

990

*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c

91

rlc_status0 = RREG32_SOC15(GC, 0, regRLC_RLCS_FED_STATUS_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1339

data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1692

gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1696

gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1711

gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1715

gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1783

data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1914

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1933

rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2031

tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2129

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2151

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2173

tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2208

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2250

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2299

cp_status = RREG32_SOC15(GC, 0, regCP_STAT);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2300

bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2329

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2336

if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2409

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2421

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2434

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2439

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2463

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2469

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2474

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2553

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2565

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2578

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2584

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2608

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2614

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2619

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2678

tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2689

tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2776

data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2863

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2869

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2894

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2900

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2913

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2919

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2942

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3271

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3274

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3540

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3576

data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3580

data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3767

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3797

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3812

tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3908

rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3925

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3946

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4046

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4062

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4080

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4098

def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4107

data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4114

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4120

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4126

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4138

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4161

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4172

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4192

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4213

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4279

data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4296

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4305

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4329

wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4330

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5343

reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5377

r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5686

data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5687

data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

820

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

833

*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1061

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1737

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1786

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1936

return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1951

*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2051

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2078

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2088

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2099

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2525

data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2526

data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2647

tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2675

adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2722

if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2744

if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2757

tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3151

rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3243

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3432

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3526

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3576

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3583

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3613

tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3623

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3650

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3655

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3660

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3666

mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3700

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3703

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3797

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3802

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4001

tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4114

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4141

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4160

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4177

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4181

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4187

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4298

clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4299

((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4888

rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4906

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4965

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4984

def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4991

def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4999

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5013

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5020

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5039

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5047

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5062

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5069

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5085

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5097

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5112

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5118

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5163

data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5357

wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5358

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6866

data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6885

data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6906

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6919

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7019

RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7024

RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7029

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7034

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7213

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7746

data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7747

data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

708

data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

729

data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

752

data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

773

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

796

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

942

RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

947

RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

952

RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

957

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

962

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1750

data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1756

data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1762

data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1823

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1883

status = RREG32_SOC15(GC, 0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

757

data = RREG32_SOC15(GC, 0, regSQ_CONFIG1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1243

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1291

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1351

RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1392

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1402

rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1420

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1475

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1499

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1512

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1582

rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1806

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1852

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1859

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1892

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1902

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1929

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1934

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1939

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1945

mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1980

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1983

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2077

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2082

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2409

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2436

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2455

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2468

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2472

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2478

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2565

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2587

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2609

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2623

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2630

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2638

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2649

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2656

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2673

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2685

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2697

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2703

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

308

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3480

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3518

reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4520

data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4893

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4894

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4961

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

516

((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

723

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

738

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

792

xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

111

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

121

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

192

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

218

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

231

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

262

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

395

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

418

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

428

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

113

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

123

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

197

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

223

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

236

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

267

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

400

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

423

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

433

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

159

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

179

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

190

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

222

tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

357

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

36

return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

381

tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

53

xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

55

RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

60

xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_1.c

62

RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

176

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

204

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

230

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

278

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

460

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

470

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

494

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

601

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

603

RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

107

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

117

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

191

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

214

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

227

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

258

tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

373

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

397

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

110

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

120

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

195

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

220

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

233

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

264

tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

397

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

428

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

522

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

527

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

553

adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

554

adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

555

adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

556

adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

557

adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

558

adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

559

adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

560

adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

561

adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

562

adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

563

adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

564

adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

565

adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

566

adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

567

adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

568

adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

569

adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

581

adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

642

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

648

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

106

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

116

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

189

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

215

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

228

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

259

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

392

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

415

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

425

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

109

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

119

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

194

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

220

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

233

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

264

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

385

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

413

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

541

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

550

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

551

pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

532

u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

541

viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

542

pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1345

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1358

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1366

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1374

viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1846

adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

2140

RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

68

err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

80

RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

144

hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

180

tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

190

tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

203

tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

53

hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

54

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

147

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

176

tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

186

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

65

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

66

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

131

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

45

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

47

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

48

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

119

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

41

hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

42

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

339

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

359

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

364

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

373

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

380

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

384

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

682

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

715

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

778

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

311

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

330

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

335

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

344

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

351

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

355

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

657

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

692

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

755

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

311

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

330

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

335

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

344

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

351

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

355

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

647

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

682

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

745

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

135

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

158

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

164

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

174

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);

sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c

381

reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

130

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

152

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

156

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

167

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

309

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

311

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

313

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

315

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

317

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

319

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

321

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

323

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

325

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

327

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

329

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

331

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

333

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

335

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

337

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB);

sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c

394

reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

144

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

158

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

547

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

183

RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

286

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

296

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

309

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

319

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

372

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

418

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

435

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

689

return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

249

RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

303

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

313

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

320

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

332

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

376

ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

446

return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

463

return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

530

ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

819

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

82

harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

823

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

198

RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

248

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

258

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

266

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

278

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

392

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

437

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

454

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

481

ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

76

harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

227

RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

280

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

292

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

304

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

316

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

428

ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

461

header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

509

tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

533

resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

597

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

614

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

641

ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

828

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

832

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1346

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1350

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

322

tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

341

resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

392

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

499

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

511

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

524

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

536

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

260

RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

311

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

323

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

335

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

347

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

427

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

440

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

473

ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

488

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

558

ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

613

return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

630

return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

661

ret &= (((RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

194

RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

246

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

256

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

261

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

349

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

396

ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

413

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

473

ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

523

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

540

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

567

ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

271

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

520

tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

539

resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

962

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

966

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

109

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

55

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

87

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

109

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

55

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

87

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1062

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1068

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1218

data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1223

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1233

data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1517

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1520

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1525

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1548

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1559

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

419

if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

440

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

933

RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

936

RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

955

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

956

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

959

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

993

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1103

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1104

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1108

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1140

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1224

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1230

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1385

data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1390

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1400

data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1502

adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1504

adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1697

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1700

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1705

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1730

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

391

val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

444

if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

465

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

809

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

818

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

827

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

836

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

845

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

863

uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

131

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

142

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

165

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

176

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

203

tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

262

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

272

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

39

u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

40

u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

402

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

412

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

432

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

503

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

506

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

507

def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

509

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

566

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

608

data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

610

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

149

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

160

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

207

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

218

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

254

tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

386

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

39

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

396

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

40

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

416

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

486

def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

488

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

489

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

540

def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

577

data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

579

data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

186

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

199

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

217

tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

276

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

291

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

333

tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

40

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

41

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

486

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

494

tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

519

tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

546

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

252

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

263

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

288

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

301

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

332

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

457

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

464

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

486

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

578

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

581

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

582

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

638

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

690

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

693

data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

694

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

180

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

191

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

210

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

223

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

254

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

387

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

394

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

411

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

498

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

499

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

532

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

533

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

534

def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

591

data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

592

data1 = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

593

data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

594

data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

205

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

216

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

242

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

255

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

286

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

411

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

418

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

440

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

530

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

540

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

551

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

553

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

554

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

609

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

644

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

211

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

222

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

242

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

255

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

286

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

405

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

412

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

429

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

513

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

522

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

530

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

546

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

577

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

197

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

208

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

234

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

247

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

278

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

403

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

410

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

432

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

519

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

528

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

303

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

314

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

334

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

347

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

378

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

491

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

501

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

547

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

554

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

571

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

655

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

666

offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

678

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

694

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

725

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

198

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

209

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

235

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

248

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

279

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

404

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

411

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

434

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

524

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

534

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

546

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

548

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

549

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

589

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

626

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

42

u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

43

u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

697

data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

699

data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

113

ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

114

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

130

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

337

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

343

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

652

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

689

if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

112

doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

114

doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

188

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

227

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

299

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

308

data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

320

def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

327

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

350

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

357

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

362

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

367

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

373

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

394

def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

401

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

406

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

413

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

419

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

424

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

43

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

431

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

489

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

519

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

63

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

72

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

105

return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

189

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

213

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

386

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

430

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

436

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

466

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

472

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

538

reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

543

reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

86

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

108

doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

110

doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

184

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

223

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

246

def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

276

def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

293

data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

298

data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

343

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

353

data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

364

def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

371

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

376

def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

395

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

402

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

407

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

41

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

412

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

418

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

423

def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

430

def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

437

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

442

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

449

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

455

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

460

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

467

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

569

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

599

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

69

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

135

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

153

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

65

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

85

return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

119

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

135

data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

228

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

282

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) & ~BIT(23);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

45

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

64

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

142

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

177

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

204

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

268

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

282

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

296

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

325

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

334

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

353

data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

358

data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

42

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

104

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

155

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

218

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

399

data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

65

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

68

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

114

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

116

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

135

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

236

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

296

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

347

baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

370

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

372

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

427

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

429

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

460

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

462

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

505

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

507

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

112

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

148

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

176

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

240

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

251

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

265

def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

294

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

303

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

322

data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

327

data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

42

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

328

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

397

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

408

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

420

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

425

RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

451

baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

52

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

526

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

572

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

70

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

sys/dev/pci/drm/amd/amdgpu/nv.c

552

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

151

return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

153

sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

155

sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

160

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33),

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

161

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81));

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

195

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

277

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

591

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

632

reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

661

*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

156

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

158

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

115

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

136

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

258

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

260

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

79

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

144

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

329

psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

365

RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

499

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

501

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

696

reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

725

*fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

756

reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

836

return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

848

reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

877

reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

186

RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

317

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

319

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

64

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

233

RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

364

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

366

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

562

reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

592

*fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

626

reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

676

return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

99

sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

127

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

150

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

349

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

88

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1340

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1344

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1350

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

776

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

780

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

786

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

782

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

787

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

775

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

780

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

108

RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

187

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

195

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

198

reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

230

reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

249

reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

298

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

422

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

467

reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

468

reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

484

reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

51

uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

529

status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

530

enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

531

en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

87

u32 en_stat = RREG32_SOC15(SMUIO,

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

49

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0.c

70

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

46

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v11_0_6.c

67

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

102

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

119

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

136

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

48

def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

69

data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0.c

85

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

42

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

59

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v13_0_3.c

78

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

45

clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

46

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

48

clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

sys/dev/pci/drm/amd/amdgpu/smuio_v14_0_2.c

50

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

46

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/smuio_v9_0.c

67

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

sys/dev/pci/drm/amd/amdgpu/soc15.c

303

r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/soc15.c

325

r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);

sys/dev/pci/drm/amd/amdgpu/soc15.c

876

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/soc21.c

479

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/soc21.c

933

sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/soc21.c

935

sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/soc24.c

280

sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

129

data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

134

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

139

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

154

data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

167

RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO));

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

189

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

195

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

201

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL2);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

207

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL3);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

220

data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

235

data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

250

data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

254

data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

72

data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

76

data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

83

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1051

status = RREG32_SOC15(UVD, k, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

106

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1110

ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

124

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

126

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1269

tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

376

harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

748

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

75

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

770

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

774

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

90

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

92

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1021

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1039

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1159

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1171

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1239

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1255

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1258

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1261

tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1264

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1278

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1313

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1348

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1368

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1381

reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1408

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1428

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1472

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1486

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1679

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1681

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1696

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1698

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2023

adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

292

RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

508

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

519

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

524

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

534

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

557

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

581

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

608

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

635

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

644

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

649

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

658

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

681

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

789

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

804

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

859

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

870

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

883

tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

909

RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

922

tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

931

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

965

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

995

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1019

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1034

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1042

tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1077

tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1094

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1149

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1175

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1192

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1195

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1198

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1211

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1243

tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1281

RREG32_SOC15(VCN, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1303

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1348

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1383

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1429

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1446

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1655

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1657

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1675

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1680

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1909

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1936

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1940

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

328

RREG32_SOC15(VCN, 0, mmUVD_STATUS)))

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

552

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

561

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

584

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

608

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

635

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

714

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

723

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

746

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

801

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

820

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

864

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

984

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

996

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1018

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1145

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1157

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1186

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1204

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1213

tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1261

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1321

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1347

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1370

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1388

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1392

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1559

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1562

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1565

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1578

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1612

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1649

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1670

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1745

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1762

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1827

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1829

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1847

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1852

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1959

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2169

reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

239

harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

527

RREG32_SOC15(VCN, i, mmUVD_STATUS)))

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

765

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

774

data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

800

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

824

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

851

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

931

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

940

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

962

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1005

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1041

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1170

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1188

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1215

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1233

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1239

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1247

tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1290

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1350

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1380

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1553

tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1576

resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1608

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1611

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1614

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1627

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1661

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1685

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1688

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1704

RREG32_SOC15(VCN, i, mmUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1727

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1807

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1824

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2064

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2066

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2084

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2089

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2203

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2240

if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

456

RREG32_SOC15(VCN, i, mmUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

715

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

732

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

785

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

794

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

820

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

843

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

877

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

885

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

973

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

982

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1009

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1100

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1107

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1109

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1111

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1123

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1160

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1178

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1184

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1192

tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1235

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1290

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1297

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1299

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1301

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1309

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1515

tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1538

resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1582

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1595

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1638

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1662

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1665

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1681

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1710

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1755

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1775

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2048

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2101

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2268

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

381

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

666

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

692

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

750

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

756

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

781

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

804

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

831

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

921

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

927

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

950

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1135

tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1152

resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1200

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1220

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1226

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1234

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1279

status = RREG32_SOC15(VCN, vcn_inst,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1331

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1339

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1343

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1371

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1384

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1430

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1455

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1459

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1472

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1507

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1527

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1619

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1691

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1738

if (RREG32_SOC15(VCN, GET_INST(VCN, i),

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1968

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

311

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

345

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

656

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

662

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

679

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

694

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

718

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

803

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

809

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

823

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

859

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

964

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

972

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

974

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

985

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1013

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1020

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1022

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1024

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1035

RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1072

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1090

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1096

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1104

tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1147

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1203

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1210

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1212

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1214

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1221

RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1244

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1257

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1301

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1325

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1328

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1344

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1373

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1419

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1439

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1551

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1604

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

334

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

620

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

643

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

688

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

694

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

719

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

742

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

769

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

859

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

865

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

888

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

924

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1032

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1056

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1059

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1072

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1101

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1143

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1163

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1272

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1325

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

298

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

587

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

612

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

709

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

770

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

777

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

779

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

781

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

793

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

829

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

844

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

850

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

875

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

931

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

938

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

940

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

942

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

950

RREG32_SOC15(VCN, i, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

976

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

986

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1010

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1016

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1041

status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1095

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1101

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1108

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1110

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1112

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1120

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1150

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1160

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1202

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1226

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1229

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1239

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1392

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1438

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1595

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

316

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

634

reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

685

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

756

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

763

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

765

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

767

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

777

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

927

tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

944

resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

995

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

276

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

583

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

324

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

338

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

683

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

646

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1284

uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

340

reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

43

reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

57

reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4010

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

943

data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

104

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

132

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

135

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

141

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

144

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

161

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

165

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

263

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

274

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

322

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

339

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

389

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

415

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

421

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

74

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

76

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

150

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

189

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

48

reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

62

reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

87

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2280

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

124

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

126

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

152

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

163

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

206

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

223

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

260

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

95

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

98

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

59

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

76

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

171

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

173

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

74

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

83

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

155

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

80

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1180

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1183

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1220

tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1243

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1253

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1275

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1300

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1302

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

462

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

376

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2530

val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

372

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1045

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1167

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1170

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1185

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1195

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1224

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1249

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1251

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1284

tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1347

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1355

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1367

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1383

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1388

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1443

data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1633

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1637

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

89

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2309

reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

151

reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2027

val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1047

val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1089

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1092

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1110

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1120

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1171

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1201

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1209

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1221

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1237

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1242

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1304

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1342

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1355

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1881

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1931

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1938

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1943

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

630

reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1011

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

878

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

887

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

891

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

903

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

920

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

925

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

929

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

934

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

983

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

998

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);