REG_RD_IND
val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2);
val = REG_RD_IND(sc, sc->bnx_shmem_base +
val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB);
val = REG_RD_IND(sc, cpu_reg->mode);
val = REG_RD_IND(sc, cpu_reg->mode);
mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER);
mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER);
reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);
reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base +
val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE);
sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0 +
sc->bnx_shared_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base +
sc->bnx_port_hw_cfg = REG_RD_IND(sc, sc->bnx_shmem_base +