Symbol: RCS0
sys/dev/pci/drm/i915/display/intel_overlay.c
1411
engine = to_gt(dev_priv)->engine[RCS0];
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2210
if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2457
[I915_EXEC_DEFAULT] = RCS0,
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
2458
[I915_EXEC_RENDER] = RCS0,
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
171
case RCS0:
sys/dev/pci/drm/i915/gt/intel_engine.h
95
ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1707
[RCS0] = MSG_IDLE_CS,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1790
if (engine->id != RCS0)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1824
if (engine->id != RCS0)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1836
if (engine->id == RCS0)
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
402
[RCS0] = GEN11_GRDOM_RENDER,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
435
[RCS0] = GEN6_GRDOM_RENDER,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
64
[RCS0] = {
sys/dev/pci/drm/i915/gt/intel_engine_user.c
211
[RENDER_CLASS] = { RCS0, 1 },
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
3502
[RCS0] = GEN8_RCS_IRQ_SHIFT,
sys/dev/pci/drm/i915/gt/intel_mocs.c
569
[RCS0] = __GEN9_RCS0_MOCS0,
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
95
case RCS0:
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
983
GEM_BUG_ON(engine->id != RCS0);
sys/dev/pci/drm/i915/gt/selftest_gt_pm.c
104
if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1054
if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1155
[RCS0] = {
sys/dev/pci/drm/i915/gvt/cmd_parser.c
428
#define R_RCS BIT(RCS0)
sys/dev/pci/drm/i915/gvt/cmd_parser.c
600
[RCS0] = {
sys/dev/pci/drm/i915/gvt/execlist.c
49
[RCS0] = RCS_AS_CONTEXT_SWITCH,
sys/dev/pci/drm/i915/gvt/handlers.c
2104
id = RCS0;
sys/dev/pci/drm/i915/gvt/handlers.c
340
engine_mask |= BIT(RCS0);
sys/dev/pci/drm/i915/gvt/mmio_context.c
100
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
101
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
102
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
103
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
104
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
105
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
106
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
107
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
108
{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
109
{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
110
{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
111
{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
112
{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
113
{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
115
{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
116
{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
117
{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
118
{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
119
{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
120
{RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
121
{RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
122
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
123
{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
124
{RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
125
{RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
126
{RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
127
{RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
128
{RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */
sys/dev/pci/drm/i915/gvt/mmio_context.c
129
{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
130
{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
131
{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
132
{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
133
{RCS0, TRVADR, 0, true}, /* 0x4df0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
134
{RCS0, TRTTE, 0, true}, /* 0x4df4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
135
{RCS0, _MMIO(0x4dfc), 0, true},
sys/dev/pci/drm/i915/gvt/mmio_context.c
147
{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
148
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
149
{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
150
{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
152
{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
153
{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
154
{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
156
{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
157
{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
158
{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
159
{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
sys/dev/pci/drm/i915/gvt/mmio_context.c
169
[RCS0] = 0xc800,
sys/dev/pci/drm/i915/gvt/mmio_context.c
332
if (req->engine->id != RCS0)
sys/dev/pci/drm/i915/gvt/mmio_context.c
356
[RCS0] = 0x4260,
sys/dev/pci/drm/i915/gvt/mmio_context.c
391
if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9)
sys/dev/pci/drm/i915/gvt/mmio_context.c
413
[RCS0] = 0xc800,
sys/dev/pci/drm/i915/gvt/mmio_context.c
427
if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9)
sys/dev/pci/drm/i915/gvt/mmio_context.c
450
if (engine->id == RCS0) {
sys/dev/pci/drm/i915/gvt/mmio_context.c
60
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
61
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
62
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
63
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
64
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
65
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
66
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
67
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
68
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
69
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
70
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
71
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
sys/dev/pci/drm/i915/gvt/mmio_context.c
72
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
73
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
74
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
75
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
sys/dev/pci/drm/i915/gvt/mmio_context.c
76
{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
77
{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
78
{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
79
{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
80
{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
81
{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
88
{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
sys/dev/pci/drm/i915/gvt/mmio_context.c
92
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
sys/dev/pci/drm/i915/gvt/mmio_context.c
93
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
94
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
95
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
96
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
97
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
98
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
sys/dev/pci/drm/i915/gvt/mmio_context.c
99
{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
sys/dev/pci/drm/i915/gvt/scheduler.c
101
if (workload->engine->id != RCS0)
sys/dev/pci/drm/i915/gvt/scheduler.c
165
if (workload->engine->id == RCS0) {
sys/dev/pci/drm/i915/gvt/scheduler.c
1704
if (engine->id == RCS0) {
sys/dev/pci/drm/i915/gvt/scheduler.c
218
if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
sys/dev/pci/drm/i915/gvt/scheduler.c
505
if (workload->engine->id == RCS0 &&
sys/dev/pci/drm/i915/gvt/scheduler.c
978
if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
sys/dev/pci/drm/i915/i915_gpu_error.c
1417
case RCS0:
sys/dev/pci/drm/i915/i915_irq.c
1092
intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
sys/dev/pci/drm/i915/i915_irq.c
975
intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
sys/dev/pci/drm/i915/i915_pci.c
102
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
134
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
197
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/i915_pci.c
225
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
233
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
239
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
sys/dev/pci/drm/i915/i915_pci.c
265
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
sys/dev/pci/drm/i915/i915_pci.c
313
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
sys/dev/pci/drm/i915/i915_pci.c
380
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
sys/dev/pci/drm/i915/i915_pci.c
388
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
sys/dev/pci/drm/i915/i915_pci.c
447
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
453
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
498
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
sys/dev/pci/drm/i915/i915_pci.c
513
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
sys/dev/pci/drm/i915/i915_pci.c
560
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
581
BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
sys/dev/pci/drm/i915/i915_pci.c
614
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
620
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
627
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
sys/dev/pci/drm/i915/i915_pci.c
643
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
650
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
sys/dev/pci/drm/i915/i915_pci.c
667
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
sys/dev/pci/drm/i915/i915_pci.c
677
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
685
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
sys/dev/pci/drm/i915/i915_pci.c
734
BIT(RCS0) | BIT(BCS0) | \
sys/dev/pci/drm/i915/i915_pci.c
781
.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
sys/dev/pci/drm/i915/i915_pci.c
87
.platform_engine_mask = BIT(RCS0), \
sys/dev/pci/drm/i915/selftests/i915_request.c
217
ce = i915_gem_context_get_engine(ctx[0], RCS0);
sys/dev/pci/drm/i915/selftests/i915_request.c
235
ce = i915_gem_context_get_engine(ctx[1], RCS0);
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
240
to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0);
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
241
if (!to_gt(i915)->engine[RCS0])
sys/dev/pci/drm/i915/selftests/mock_gem_device.c
244
if (mock_engine_init(to_gt(i915)->engine[RCS0]))