PCI_COMMAND_STATUS_REG
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG: {
csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
status = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |=
if (REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) &
REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |=
REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |=
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
case PCI_COMMAND_STATUS_REG:
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG,
schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG));
csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG);
schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr);
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
reg = pci_conf_read(pc, csc->cc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->cc_tag, PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->csc_tag, PCI_COMMAND_STATUS_REG,
reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
command = pci_conf_read(pc, csc->ct_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->ct_tag, PCI_COMMAND_STATUS_REG, command);
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
reg = pci_conf_read(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(ca->ca_pc, ca->ca_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG,
HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr);
HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr);
case PCI_COMMAND_STATUS_REG:
cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, mod_cmd);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd |
status = (sc->sc_conf_read)(sc, PCI_COMMAND_STATUS_REG);
(sc->sc_conf_write)(sc, PCI_COMMAND_STATUS_REG, status);
#define TI_PCI_CMDSTAT PCI_COMMAND_STATUS_REG
command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG + 1);
status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1);
status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1);
command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command);
PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0);
cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1);
pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd);
pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1);
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
v = pci_conf_read(az->pc, az->tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(az->pc, az->tag, PCI_COMMAND_STATUS_REG,
fun = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
#define PCI_COMMAND PCI_COMMAND_STATUS_REG
(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
PCI_CLRBIT(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG));
csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG, reg);
PCI_COMMAND_STATUS_REG);
command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
PCI_COMMAND_STATUS_REG);
PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_COMMAND_STATUS_REG,
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr &
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr &
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG)),
csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_STATUS_REG, csr);
PCI_COMMAND_STATUS_REG, 0);
sc->sc_csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
csr = pci_conf_read(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr);
pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pcictl);
pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pcictl);
pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pcictl);
if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)
PCI_COMMAND_STATUS_REG, reg & 0xffff, (reg >> 16) & 0xffff);
if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)