PCI_COMMAND_MASTER_ENABLE
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE));
data |= PCI_COMMAND_MASTER_ENABLE;
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
data |= PCI_COMMAND_MASTER_ENABLE;
if (data & PCI_COMMAND_MASTER_ENABLE)
| PCI_COMMAND_MASTER_ENABLE
PCI_COMMAND_MASTER_ENABLE); /* XXX: good guess needed */
csc->cc_csr = PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_MASTER_ENABLE
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_MASTER_ENABLE,
csr | PCI_COMMAND_MASTER_ENABLE
csr | PCI_COMMAND_MASTER_ENABLE
csr = PCI_COMMAND_MASTER_ENABLE;
csr = PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
csr = PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;
command |= PCI_COMMAND_MASTER_ENABLE;
command &= ~PCI_COMMAND_MASTER_ENABLE;
PCI_COMMAND_MASTER_ENABLE);
PCI_COMMAND_MASTER_ENABLE);
reg &= ~PCI_COMMAND_MASTER_ENABLE;
csr |= PCI_COMMAND_MASTER_ENABLE;
csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
csr |= PCI_COMMAND_MASTER_ENABLE;
reg |= PCI_COMMAND_MASTER_ENABLE;