PCI_COMMAND_IO_ENABLE
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
(po->po_bridge_command & PCI_COMMAND_IO_ENABLE) == 0)) {
if ((old ^ po->po_bridge_command) & PCI_COMMAND_IO_ENABLE)
elroy_write32(&r->pci_cmdstat, htole32(PCI_COMMAND_IO_ENABLE |
csr | PCI_COMMAND_IO_ENABLE);
(val & PCI_COMMAND_IO_ENABLE) != PCI_COMMAND_IO_ENABLE)
(val & PCI_COMMAND_IO_ENABLE) == PCI_COMMAND_IO_ENABLE)
data |= PCI_COMMAND_IO_ENABLE;
if (data & PCI_COMMAND_IO_ENABLE)
data |= PCI_COMMAND_IO_ENABLE;
data |= PCI_COMMAND_IO_ENABLE;
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
command |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_IO_ENABLE |
csc->cc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
reg |= PCI_COMMAND_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
command |= (PCI_COMMAND_IO_ENABLE |
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE,
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
| PCI_COMMAND_IO_ENABLE);
csr |= PCI_COMMAND_IO_ENABLE;
csr |= PCI_COMMAND_IO_ENABLE;
HSET4(sc, PCIE_CMD, PCI_COMMAND_IO_ENABLE |
csr |= PCI_COMMAND_IO_ENABLE;
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
== (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
== (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
== (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
csr |= PCI_COMMAND_IO_ENABLE;
command &= ~PCI_COMMAND_IO_ENABLE;
command |= PCI_COMMAND_IO_ENABLE;
command &= ~PCI_COMMAND_IO_ENABLE;
command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
!= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE));
if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
reg &= ~PCI_COMMAND_IO_ENABLE;
if (csr & PCI_COMMAND_IO_ENABLE) {
if (csr & PCI_COMMAND_IO_ENABLE)
if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE));
if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
csr |= PCI_COMMAND_IO_ENABLE;
if (csr & PCI_COMMAND_IO_ENABLE)
csr & ~PCI_COMMAND_IO_ENABLE);
csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
csr & ~PCI_COMMAND_IO_ENABLE);
if ((csr & PCI_COMMAND_IO_ENABLE) == 0) {
csr |= PCI_COMMAND_IO_ENABLE;
& (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
!= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))