#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#define MACHINE_BUS_SPACE_MEM 0
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
#define PRIxBUSADDR "lx"
#define PRIxBUSSIZE "lx"
#define PRIuBUSSIZE "lu"
typedef int bus_space_tag_t;
typedef u_long bus_space_handle_t;
#define PRIxBSH "lx"
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
int bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t,
int, bus_space_handle_t *);
void bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
bus_addr_t rend, bus_size_t size, bus_size_t align,
bus_size_t boundary, int cacheable, bus_addr_t *addrp,
bus_space_handle_t *bshp);
void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t size);
#define bus_space_read_1(t, h, o) \
((void) t, (*(volatile u_int8_t *)((h) + (o)*4)))
#define bus_space_read_2(t, h, o) \
((void) t, (*(volatile u_int16_t *)((h) + (o)*2)))
#define bus_space_read_4(t, h, o) \
((void) t, (*(volatile u_int32_t *)((h) + (o))))
#define bus_space_read_multi_1(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_read_multi_2(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_read_multi_4(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_read_region_1(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a0@,%%a1@+ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_read_region_2(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a0@,%%a1@+ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_read_region_4(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a0@+,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0","memory"); \
} while (0)
#define bus_space_write_1(t, h, o, v) \
((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)*4) = (v))))
#define bus_space_write_2(t, h, o, v) \
((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)*2) = (v))))
#define bus_space_write_4(t, h, o, v) \
((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
#define bus_space_write_multi_1(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_write_multi_2(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_write_multi_4(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_write_region_1(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a1@+,%%a0@ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*4), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_write_region_2(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a1@+,%%a0@ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)*2), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_write_region_4(t, h, o, a, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a1@+,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" ((size_t)(c)) : \
"a0","a1","d0"); \
} while (0)
#define bus_space_set_multi_1(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movb %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)*4), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define bus_space_set_multi_2(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movw %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)*2), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define bus_space_set_multi_4(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movl %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define bus_space_set_region_1(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movb %%d1,%%a0@ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)*4), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define bus_space_set_region_2(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movw %%d1,%%a0@ ; \
addql #4,%%a0 ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)*2), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define bus_space_set_region_4(t, h, o, val, c) do { \
(void) t; \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movl %%d1,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h)+(o)), "g" ((u_long)val), \
"g" ((size_t)(c)) : \
"a0","d0","d1"); \
} while (0)
#define __MACHINE_copy_region_N(BYTES) \
static __inline void __CONCAT(bus_space_copy_region_,BYTES) \
(bus_space_tag_t, \
bus_space_handle_t bsh1, bus_size_t off1, \
bus_space_handle_t bsh2, bus_size_t off2, \
bus_size_t count); \
\
static __inline void \
__CONCAT(bus_space_copy_region_,BYTES)( \
bus_space_tag_t t, \
bus_space_handle_t h1, \
bus_size_t o1, \
bus_space_handle_t h2, \
bus_size_t o2, \
bus_size_t c) \
{ \
bus_size_t o; \
\
if ((h1 + o1) >= (h2 + o2)) { \
\
for (o = 0; c != 0; c--, o += BYTES) \
__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
__CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
} else { \
\
for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
__CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
} \
}
__MACHINE_copy_region_N(1)
__MACHINE_copy_region_N(2)
__MACHINE_copy_region_N(4)
#undef __MACHINE_copy_region_N
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01
#define BUS_SPACE_BARRIER_WRITE 0x02
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#define __HAVE_NO_BUS_DMA
#endif