#ifndef _HP300_BUS_H_
#define _HP300_BUS_H_
#define HP300_BUS_SPACE_INTIO 0
#define HP300_BUS_SPACE_DIO 1
#define HP300_BUS_SPACE_SGC 2
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
#define PRIxBUSADDR "lx"
#define PRIxBUSSIZE "lx"
#define PRIuBUSSIZE "lu"
typedef struct bus_space_tag *bus_space_tag_t;
typedef u_long bus_space_handle_t;
#define PRIxBSH "lx"
struct bus_space_tag {
u_int bustype;
uint8_t (*bsr1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint16_t (*bsr2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
uint32_t (*bsr4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
void (*bsrm1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bsrm2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bsrm4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bsrr1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bsrr2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bsrr4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bsw1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t);
void (*bsw2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t);
void (*bsw4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t);
void (*bswm1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bswm2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bswm4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bswr1)(bus_space_tag_t, bus_space_handle_t ,
bus_size_t, const uint8_t *, bus_size_t);
void (*bswr2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bswr4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bssm1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bssm2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bssm4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
void (*bssr1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bssr2)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bssr4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
};
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
int bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t,
int, bus_space_handle_t *);
void bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
static __inline paddr_t
bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags)
{
return -1;
}
int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
bus_addr_t rend, bus_size_t size, bus_size_t align,
bus_size_t boundary, int cacheable, bus_addr_t *addrp,
bus_space_handle_t *bshp);
void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t size);
#define bus_space_vaddr(t, h) (void *)(h)
int hp300_bus_space_probe(bus_space_tag_t t,
bus_space_handle_t bsh, bus_size_t offset, int sz);
#define bus_space_read_1(t, h, o) \
(((t)->bsr1 != NULL) ? ((t)->bsr1)(t, h, o) : \
(*(volatile uint8_t *)((h) + (o))))
#define bus_space_read_2(t, h, o) \
(((t)->bsr2 != NULL) ? ((t)->bsr2)(t, h, o) : \
(*(volatile uint16_t *)((h) + (o))))
#define bus_space_read_4(t, h, o) \
(((t)->bsr4 != NULL) ? ((t)->bsr4)(t, h, o) : \
(*(volatile uint32_t *)((h) + (o))))
#define bus_space_read_multi_1(t, h, o, a, c) \
do { \
if ((t)->bsrm1 != NULL) \
((t)->bsrm1)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_read_multi_2(t, h, o, a, c) \
do { \
if ((t)->bsrm2 != NULL) \
((t)->bsrm2)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_read_multi_4(t, h, o, a, c) do { \
if ((t)->bsrm4 != NULL) \
((t)->bsrm4)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a0@,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_read_region_1(t, h, o, a, c) \
do { \
if ((t)->bsrr1 != NULL) \
((t)->bsrr1)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a0@+,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_read_region_2(t, h, o, a, c) \
do { \
if ((t)->bsrr2 != NULL) \
((t)->bsrr2)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a0@+,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_read_region_4(t, h, o, a, c) \
do { \
if ((t)->bsrr4 != NULL) \
((t)->bsrr4)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a0@+,%%a1@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0","memory"); \
} \
} while ( 0)
#define bus_space_write_1(t, h, o, v) \
do { \
if ((t)->bsw1 != NULL) \
((t)->bsw1)(t, h, o, v); \
else \
((void)(*(volatile uint8_t *)((h) + (o)) = (v))); \
} while ( 0)
#define bus_space_write_2(t, h, o, v) \
do { \
if ((t)->bsw2 != NULL) \
((t)->bsw2)(t, h, o, v); \
else \
((void)(*(volatile uint16_t *)((h) + (o)) = (v))); \
} while ( 0)
#define bus_space_write_4(t, h, o, v) \
do { \
if ((t)->bsw4 != NULL) \
((t)->bsw4)(t, h, o, v); \
else \
((void)(*(volatile uint32_t *)((h) + (o)) = (v))); \
} while ( 0)
#define bus_space_write_multi_1(t, h, o, a, c) \
do { \
if ((t)->bswm1 != NULL) \
((t)->bswm1)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_write_multi_2(t, h, o, a, c) \
do { \
if ((t)->bswm2 != NULL) \
((t)->bswm2)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_write_multi_4(t, h, o, a, c) \
do { \
(void) t; \
if ((t)->bswm4 != NULL) \
((t)->bswm4)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a1@+,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_write_region_1(t, h, o, a, c) \
do { \
if ((t)->bswr1 != NULL) \
((t)->bswr1)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movb %%a1@+,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_write_region_2(t, h, o, a, c) \
do { \
if ((t)->bswr2) != NULL) \
((t)->bswr2)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movw %%a1@+,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_write_region_4(t, h, o, a, c) \
do { \
if ((t)->bswr4) != NULL) \
((t)->bswr4)(t, h, o, a, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%a1 ; \
movl %2,%%d0 ; \
1: movl %%a1@+,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (a), "g" (c) : \
"a0","a1","d0"); \
} \
} while ( 0)
#define bus_space_set_multi_1(t, h, o, val, c) \
do { \
if ((t)->bssm1 != NULL) \
((t)->bssm1)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movb %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define bus_space_set_multi_2(t, h, o, val, c) \
do { \
if ((t)->bssm2 != NULL) \
((t)->bssm2)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movw %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define bus_space_set_multi_4(t, h, o, val, c) \
do { \
if ((t)->bssm4 != NULL) \
((t)->bssm4)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movl %%d1,%%a0@ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define bus_space_set_region_1(t, h, o, val, c) \
do { \
if ((t)->bssr1 != NULL) \
((t)->bssr1)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movb %%d1,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define bus_space_set_region_2(t, h, o, val, c) \
do { \
if ((t)->bssr2 != NULL) \
((t)->bssr2)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movw %%d1,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define bus_space_set_region_4(t, h, o, val, c) \
do { \
(void) t; \
if ((t)->bssr4 != NULL) \
((t)->bssr4)(t, h, o, val, c); \
else { \
__asm volatile (" \
movl %0,%%a0 ; \
movl %1,%%d1 ; \
movl %2,%%d0 ; \
1: movl %%d1,%%a0@+ ; \
subql #1,%%d0 ; \
jne 1b" : \
: \
"r" ((h) + (o)), "g" (val), "g" (c) : \
"a0","d0","d1"); \
} \
} while ( 0)
#define __HP300_copy_region_N(BYTES) \
static __inline void \
__CONCAT(bus_space_copy_region_,BYTES)(bus_space_tag_t t, \
bus_space_handle_t h1, bus_size_t o1, bus_space_handle_t h2, \
bus_size_t o2, bus_size_t c) \
{ \
bus_size_t o; \
\
if ((h1 + o1) >= (h2 + o2)) { \
\
for (o = 0; c != 0; c--, o += BYTES) \
__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
__CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
} else { \
\
for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
__CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
__CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
} \
}
__HP300_copy_region_N(1)
__HP300_copy_region_N(2)
__HP300_copy_region_N(4)
#undef __HP300_copy_region_N
#define __BUS_SPACE_HAS_STREAM_METHODS 1
#define bus_space_read_stream_1 bus_space_read_1
#define bus_space_read_stream_2 bus_space_read_2
#define bus_space_read_stream_4 bus_space_read_4
#define bus_space_read_stream_8 bus_space_read_8
#define bus_space_read_multi_stream_1 bus_space_read_multi_1
#define bus_space_read_multi_stream_2 bus_space_read_multi_2
#define bus_space_read_multi_stream_4 bus_space_read_multi_4
#define bus_space_read_multi_stream_8 bus_space_read_multi_8
#define bus_space_read_region_stream_1 bus_space_read_region_1
#define bus_space_read_region_stream_2 bus_space_read_region_2
#define bus_space_read_region_stream_4 bus_space_read_region_4
#define bus_space_read_region_stream_8 bus_space_read_region_8
#define bus_space_write_stream_1 bus_space_write_1
#define bus_space_write_stream_2 bus_space_write_2
#define bus_space_write_stream_4 bus_space_write_4
#define bus_space_write_stream_8 bus_space_write_8
#define bus_space_write_multi_stream_1 bus_space_write_multi_1
#define bus_space_write_multi_stream_2 bus_space_write_multi_2
#define bus_space_write_multi_stream_4 bus_space_write_multi_4
#define bus_space_write_multi_stream_8 bus_space_write_multi_8
#define bus_space_write_region_stream_1 bus_space_write_region_1
#define bus_space_write_region_stream_2 bus_space_write_region_2
#define bus_space_write_region_stream_4 bus_space_write_region_4
#define bus_space_write_region_stream_8 bus_space_write_region_8
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01
#define BUS_SPACE_BARRIER_WRITE 0x02
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#define __HAVE_NO_BUS_DMA
#endif