MESG_OUT_PHASE
if (sbicxfstart(regs, 6, MESG_OUT_PHASE,
MESG_OUT_PHASE);
case MESG_OUT_PHASE:
while ((csr & 0x07) != MESG_OUT_PHASE) {
if ((csr & 0x07) != MESG_OUT_PHASE) {
case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
case SBIC_CSR_MIS | MESG_OUT_PHASE:
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
} else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
} while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE)
} else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) {
if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait))
sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE);
case MESG_OUT_PHASE:
while ((csr & 0x07) != MESG_OUT_PHASE) {
if ((csr & 0x07) != MESG_OUT_PHASE) {
case SBIC_CSR_XFERRED|MESG_OUT_PHASE:
case SBIC_CSR_MIS|MESG_OUT_PHASE:
case SBIC_CSR_MIS_1|MESG_OUT_PHASE:
case SBIC_CSR_MIS_2|MESG_OUT_PHASE:
case MESG_OUT_PHASE:
case MESG_OUT_PHASE:
if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE)
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
case SBIC_CSR_MIS | MESG_OUT_PHASE:
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
case SBIC_CSR_MIS | MESG_OUT_PHASE:
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
case SBIC_CSR_MIS | MESG_OUT_PHASE:
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
case MESG_OUT_PHASE: