MC_REGA
bus_space_write_1(st, sh, 0, MC_REGA);
bus_space_write_1(st, sh, 0, MC_REGA);
bus_space_write_1(st, sh, 0, MC_REGA);
reg_a = (*sc->sc_mcread)(sc, MC_REGA);
(*sc->sc_mcwrite)(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_16_Hz);
(*sc->sc_mcwrite)(sc, MC_REGA, reg_a);
(*sc->sc_mcwrite)(sc, MC_REGA,
mcclock_isa_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
bus_space_write_1(st, sh, 0, MC_REGA);
rtc_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
mcclock_frodo_write(sc, MC_REGA,
(mcclock_frodo_read(sc, MC_REGA) & ~MC_REGA_DVMASK) |
while ((mc_read(MC_REGA) & MC_REGA_UIP) != 0)
chiptime[MC_REGA] =
(chiptime[MC_REGA] & ~MC_REGA_DVMASK) | MC_BASE_32_KHz;
while (chiptime[MC_REGA] & MC_REGA_UIP)
while (mclock[MC_REGA] & MC_REGA_UIP)
clk[MC_REGA].datum = MC_BASE_32_KHz | MC_RATE_256_Hz;
clk[MC_REGA].datum = saved_rega;
saved_rega = clk[MC_REGA].datum;
mcclock_isa_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
mc146818_write(NULL, MC_REGA, MC_BASE_32_KHz | hzval);
mc146818_write(NULL, MC_REGA, /* XXX softc */
while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP)
mc146818_write(NULL, MC_REGA, /* XXX softc */
mc146818_write(sc, MC_REGA, rate);
if (((*sc->sc_mcread)(sc, MC_REGA) & MC_REGA_UIP) == 0)
while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \