MC_BASE_32_KHz
bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz);
bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz);
bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz);
(*sc->sc_mcwrite)(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_16_Hz);
MC_BASE_32_KHz | MC_RATE_1024_Hz);
mcclock_isa_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz);
rtc_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
MC_BASE_32_KHz);
(chiptime[MC_REGA] & ~MC_REGA_DVMASK) | MC_BASE_32_KHz;
clk[MC_REGA].datum = MC_BASE_32_KHz | MC_RATE_256_Hz;
mcclock_isa_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz);
mc146818_write(NULL, MC_REGA, MC_BASE_32_KHz | hzval);
MC_BASE_32_KHz | MC_RATE_1024_Hz);
MC_BASE_32_KHz | MC_RATE_1024_Hz);
rate = MC_BASE_32_KHz | MC_RATE_128_Hz;
rate = MC_BASE_32_KHz | MC_RATE_256_Hz;
rate = MC_BASE_32_KHz | MC_RATE_512_Hz;
rate = MC_BASE_32_KHz | MC_RATE_1024_Hz;
rate = MC_BASE_32_KHz | MC_RATE_2048_Hz;
rate = MC_BASE_32_KHz | MC_RATE_4096_Hz;
rate = MC_BASE_32_KHz | MC_RATE_8192_Hz;
rate = MC_BASE_32_KHz | MC_RATE_32_Hz;
rate = MC_BASE_32_KHz | MC_RATE_64_Hz;