MCR_RTS
sc->sc_mcr_rts = MCR_RTS;
sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
SET(sc->sc_mcr, MCR_RTS);
CLR(sc->sc_mcr, MCR_RTS);
ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
sc->sc_mcr_rts = MCR_RTS;
sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
SET(sc->sc_mcr, MCR_RTS);
CLR(sc->sc_mcr, MCR_RTS);
ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
ISSET(sc->sc_mcr, MCR_RTS) ? "+" : "-",
sc->sc_mcr_rts = MCR_RTS;
sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
SET(sc->sc_mcr, MCR_RTS);
CLR(sc->sc_mcr, MCR_RTS);
ym2149_dtr(!(sc->sc_mcr_active & MCR_RTS));
ym2149_rts(!(sc->sc_mcr_active & MCR_RTS));
ym2149_dtr(sc->sc_mcr_active & MCR_RTS);
ym2149_rts(sc->sc_mcr_active & MCR_RTS);
CSR_WRITE(com_port, com_mcr, MCR_RTS | MCR_DTR);
OUTB(com_mcr, MCR_DTR | MCR_RTS);
bus_space_write_1(bst, bsh, com_mcr, MCR_DTR | MCR_RTS);
apci->ap_mcr = MCR_DTR | MCR_RTS;
dca->dca_mcr = MCR_DTR | MCR_RTS;
REGWRITE_1(VR4181_SIU_ADDR, com_mcr, MCR_DTR | MCR_RTS);
outb(combase + com_mcr, MCR_DTR | MCR_RTS);
com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
com0addr[com_mcr] = htobe32(MCR_DTR|MCR_RTS);
bus_space_write_1(iot, ioh, com_mcr, MCR_DTR | MCR_RTS);
#define RTS_MODE (MCR_RTS|MCR_DTR)
CSR_WRITE(com_port, com_mcr, MCR_RTS | MCR_DTR);
SET(combits, MCR_RTS);
CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
if (ISSET(combits, MCR_RTS))
sc->sc_mcr_rts = MCR_RTS;
sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
SET(sc->sc_mcr, MCR_RTS);
CLR(sc->sc_mcr, MCR_RTS);
CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
SET(sc->sc_mcr, MCR_DTR | MCR_RTS);
(sc->sc_rts ? MCR_RTS : 0);