KV
(!badaddr((void *)KV(MCPCIA_BRIDGE_ADDR(gid, mid)), sizeof (uint32_t)))
if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls),
if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) {
dp = (pcireg_t *)KV(paddr);
dp = (pcireg_t *)KV(paddr);
badaddr((void *)KV(((((unsigned long) gid) << MCBUS_GID_SHIFT) | \
dp = (pcireg_t *)KV(paddr);
dp = (pcireg_t *)KV(paddr);
sfb_cnattach(KV(0x1c0000000) + 0x02000000);
#define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000)
{ KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(0x140000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - unused */
{ KV(0x160000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - unused */
{ KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 4 - TCDS ASIC */
{ KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 5 - IOCTL ASIC */
{ KV(0x1c0000000), C(TC_3000_300_DEV_BOGUS), }, /* 6 - CXTurbo */
#define TC_3000_300_IR KV(0x00000001e0000000) /* Dense */
#define TC_3000_300_CSR KV(0x00000001e0000008) /* Dense */
#define TC_3000_300_MCR KV(0x00000001e0000010) /* Dense */
#define TC_3000_300_LED KV(0x00000001e0000018) /* Dense */
sfb_cnattach(KV(0x1e0000000) + 0x02000000);
{ KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */
{ KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */
{ KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */
{ KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */
{ KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */
{ KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */
#define TC_3000_500_IOSLOT KV(0x00000001c2000000) /* Dense */
#define TC_3000_500_TCCONFIG KV(0x00000001c2000008) /* Dense */
#define TC_3000_500_FADR KV(0x00000001c2000010) /* Dense */
#define TC_3000_500_TCEREG KV(0x00000001c2000018) /* Dense */
#define TC_3000_500_MEMCONF KV(0x00000001c2200000) /* Dense */
#define TC_3000_500_IMR_READ KV(0x00000001c2400000) /* Dense */
#define TC_3000_500_IMR_WRITE KV(0x00000001c281fffc) /* Dense */
#define TC_3000_500_TCRESET KV(0x00000001c2a00000) /* Dense */
#define TC_3000_500_IR KV(0x00000001d4800000) /* Sparse */
#define TC_3000_500_IR_CLEAR KV(0x00000001d4c00000) /* Sparse */
#define TC_3000_500_SCMAP KV(0x00000001d5000000) /* Sparse */
KV((long)TLSB_NODE_ADDR((_node)) + (_reg))
#define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg)))
{ "mc146818", SYS_DEV_BOGUS, KV(KN02_SYS_CLOCK), 0 },
{ "dc", SYS_DEV_SCC0, KV(KN02_SYS_DZ), 0 },
{ "pm", SYS_DEV_BOGUS, KV(KN01_PHYS_FBUF_START), 0 },
{ "dc", SYS_DEV_SCC0, KV(KN01_SYS_DZ), 0 },
{ "lance", SYS_DEV_LANCE, KV(KN01_SYS_LANCE), 0 },
{ "sii", SYS_DEV_SCSI, KV(KN01_SYS_SII), 0 },
{ "mc146818", SYS_DEV_BOGUS, KV(KN01_SYS_CLOCK), 0 },
{ "dc", SYS_DEV_SCC0, KV(KN230_SYS_DZ0), 0 },
{ "lance", SYS_DEV_LANCE, KV(KN230_SYS_LANCE), 0 },
{ "sii", SYS_DEV_SCSI, KV(KN230_SYS_SII), 0 },
{ "mc146818", SYS_DEV_BOGUS, KV(KN230_SYS_CLOCK), 0 },
{ "dc", SYS_DEV_OPT0, KV(KN230_SYS_DZ1), 0 },
{ "dc", SYS_DEV_OPT1, KV(KN230_SYS_DZ2), 0 },
{ "nvram", SYS_DEV_BOGUS, KV(0x86400000), 0 },
{ KV(KN02_PHYS_TC_0_START), C(SYS_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(KN02_PHYS_TC_1_START), C(SYS_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(KN02_PHYS_TC_2_START), C(SYS_DEV_OPT2), }, /* 2 - opt slot 2 */
{ KV(KN02_PHYS_TC_3_START), C(SYS_DEV_BOGUS), }, /* 3 - unused */
{ KV(KN02_PHYS_TC_4_START), C(SYS_DEV_BOGUS), }, /* 4 - unused */
{ KV(KN02_PHYS_TC_5_START), C(SYS_DEV_SCSI), }, /* 5 - b`board SCSI */
{ KV(KN02_PHYS_TC_6_START), C(SYS_DEV_LANCE), }, /* 6 - b`board LANCE */
{ KV(KN02_PHYS_TC_7_START), C(SYS_DEV_BOGUS), }, /* 7 - system CSRs */
{ KV(KN03_PHYS_TC_0_START), C(SYS_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(KN03_PHYS_TC_1_START), C(SYS_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(KN03_PHYS_TC_2_START), C(SYS_DEV_OPT2), }, /* 2 - opt slot 2 */
{ KV(KN03_PHYS_TC_3_START), C(SYS_DEV_BOGUS), }, /* 3 - IOASIC */
{ KV(KMIN_PHYS_TC_0_START), C(SYS_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(KMIN_PHYS_TC_1_START), C(SYS_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(KMIN_PHYS_TC_2_START), C(SYS_DEV_OPT2), }, /* 2 - opt slot 2 */
{ KV(KMIN_PHYS_TC_3_START), C(SYS_DEV_BOGUS), }, /* 3 - IOASIC */
{ KV(XINE_PHYS_TC_0_START), C(SYS_DEV_OPT0), }, /* 0 - opt slot 0 */
{ KV(XINE_PHYS_TC_1_START), C(SYS_DEV_OPT1), }, /* 1 - opt slot 1 */
{ KV(XINE_PHYS_CFB_START), C(SYS_DEV_BOGUS), }, /* 2 - unused */
{ KV(XINE_PHYS_TC_3_START), C(SYS_DEV_BOGUS), }, /* 3 - IOASIC */