sys/arch/arm/clps711x/clpssoc.c

242

*(volatile uint32_t *)(ARM7XX_INTRREG_VBASE + PS711X_TC1EOI) = 1;

sys/arch/arm/clps711x/clpssoc.c

68

#define INTSR (*((volatile uint16_t *)(ARM7XX_INTRREG_VBASE + PS711X_INTSR)))

sys/arch/arm/clps711x/clpssoc.c

69

#define INTMR (*((volatile uint16_t *)(ARM7XX_INTRREG_VBASE + PS711X_INTMR)))

sys/arch/arm/clps711x/clpssoc.c

70

#define SYSCON (*((volatile uint32_t *)(ARM7XX_INTRREG_VBASE + PS711X_SYSCON)))

sys/arch/arm/clps711x/clpssoc.c

71

#define TC1D (*((volatile uint16_t *)(ARM7XX_INTRREG_VBASE + PS711X_TC1D)))

sys/arch/arm/clps711x/clpssoc.c

72

#define TC2D (*((volatile uint16_t *)(ARM7XX_INTRREG_VBASE + PS711X_TC2D)))

sys/arch/epoc32/epoc32/machdep.c

128

ARM7XX_INTRREG_VBASE, /* included com, lcd-ctrl */

sys/arch/epoc32/epoc32/machdep.c

564

if (clpscom_cnattach(ARM7XX_INTRREG_VBASE, 115200, mode) == 0)

sys/arch/epoc32/epoc32/machdep.c

569

vaddr_t vbase = ARM7XX_INTRREG_VBASE;

sys/arch/epoc32/epoc32/machdep.c

585

gpio = (uint8_t *)ARM7XX_INTRREG_VBASE + WINDERMERE_GPIO_OFFSET;

sys/arch/epoc32/windermere/windermere.c

196

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_INTR_OFFSET);

sys/arch/epoc32/windermere/windermere.c

218

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_INTR_OFFSET);

sys/arch/epoc32/windermere/windermere.c

230

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_INTR_OFFSET);

sys/arch/epoc32/windermere/windermere.c

249

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_TC_OFFSET + TC1_OFFSET);

sys/arch/epoc32/windermere/windermere.c

251

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_TC_OFFSET + TC2_OFFSET);

sys/arch/epoc32/windermere/windermere.c

275

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_TC_OFFSET + TC1_OFFSET);

sys/arch/epoc32/windermere/windermere.c

303

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_TC_OFFSET + TC2_OFFSET);

sys/arch/epoc32/windermere/windermere.c

315

(uint32_t *)(ARM7XX_INTRREG_VBASE + WINDERMERE_TC_OFFSET + TC2_OFFSET);